HP 16555A Service Manual page 63

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Testing Performance
To test the multiple-clock, multiple-edge, state acquisition
Check the clock period. Using the oscilloscope, verify that the master-to-master
2
clock time is 10.000 ns.
a In the oscilloscope Timebase menu, select Scale: 2.000 ns/div
b In the oscilloscope Timebase menu, select Position. Using the oscilloscope knob,
position the clock waveform so that a rising edge appears at the left of the display
c On the oscilloscope, select [Shift] Period: channel 2, then select [Enter] to display the
clock period (Period(2)). If the period is not less than 10.000 ns, go to step d. If the
period is less than 10.000 ns, go to step 3.
d In the oscilloscope Timebase menu, increase Position 10.000 ns. If the period is not
less than 10.000 ns, decrease the pulse generator Chan 2 Doub in 10 ps increments
until one of the two periods measured is less than 10.000 ns.
Check the data pulse width. Using the oscilloscope, verify that the data pulse width
3
is 4.480 ns, +20 ps or - 80 ps.
a In the oscilloscope Timebase menu, select Scale: 1.000 ns/div.
b In the oscilloscope Timebase menu, select Position. Using the oscilloscope knob,
position the data waveform so that the waveform is centered on the screen.
c On the oscilloscope, select [Shift] + width: channel 1, then select [Enter] to display the
data signal pulse width (+ width (1)).
d If the pulse width is outside the limits, adjust the pulse generator channel 1 width until
the pulse width is within limits.
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