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Testing Performance
To test the single-clock, multiple-edge, state acquisition
Check the setup/hold with single clock, multiple clock edges
Select the logic analyzer setup/hold time.
1
a In the logic analyzer Format menu, touch Master Clock.
b Select and activate any multiple clock edge.
c Touch the Setup/Hold field and select the setup/hold to be tested for all pods. The
first time through this test, select the top combination in the following table.
Setup/Hold Combinations
4.0/0.0 ns
0.0/4.0 ns
2.0/2.0 ns
d Touch Done to exit the setup/hold combinations.
3–48
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