HP 16555A Service Manual page 54

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In the logic analyzer Format menu, touch Run. The display should show an
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alternating pattern of "AA" and "55." If the "Search Failed" yellow bar message does
not appear, the test passes. Record the Pass or Fail in the performance test record.
Test the next clock.
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a Touch Listing, then touch Format.
b In the logic analyzer Format menu, touch Master Clock.
c Turn off the clock just tested.
d Repeat steps 4, 5, and 6 for the next clock edge listed in the table in step 4, until all
listed clock edges have been tested.
Enable the pulse generator channel 2 COMP (LED on).
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Using the Delay mode of the pulse generator channel 1, position the pulses
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according to the setup/hold combination selected, +0.0 ps or -100 ps.
a On the Oscilloscope, select [Define meas] Define ∆Time - Stop edge: falling.
b On the oscilloscope, select [Shift] - width: channel 2, then select [Enter] to verify the
clock signal pulse width (- width(2)). If the pulse width is outside the limits, adjust the
pulse generator channel 2 width until the clock pulse width is 3.480 ns, +20 ps or -80
ps.
c On the oscilloscope, select [Shift] ∆Time. Select Start src: channel 1, then select
[Enter] to display the setup time (∆Time(1)-(2)).
d Adjust the pulse generator channel 1 Delay until the pulses are aligned according the
the setup time of the setup/hold combination selected, +0.0 ps or -100 ps.
To test the single-clock, single-edge, state acquisition
Testing Performance
3–27

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