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MN102L25GGW(IC401):Unit CPU
Pin function
Symbol
I/O
Pin No.
1
Micon wait signal input
I
WAIT
2
Read enable
RE
O
3
Spindle muting output to IC251
O
SPMUTE
4
Write enable
WEN
O
5
Loading motor standby control
LMMUTE
O
6
Chip select for ODC
O
CS1
7
Chip select for CPPM
CS2
O
8
Connect to TP312
-
CS3
9
Driver mute
DRVMUTE
O
10
Spin kick (Non connect)
SPKICK
O
11
LSI reset
O
LSIRST
12
Bus selection input
WORD
O
13
Address bus 0 for CPU
O
A0
14
Address bus 1 for CPU
A1
O
15
Address bus 2 for CPU
O
A2
16
Address bus 3 for CPU
O
A3
17
Power supply
VDD
-
18
Connect to TP169
-
SYSCLK
19
Ground
VSS
-
20
Not use (Connect to vss)
-
XI
21
Connect to TP170
-
XO
22
Power supply
VDD
-
23
Clock signal input
I
OSCI
24
Clock signal output
OSCO
O
25
CPU Mode selection input
I
MODE
26
Address bus 4 for CPU
O
A4
27
Address bus 5 for CPU
A5
O
28
Address bus 6 for CPU
O
A6
29
Address bus 7 for CPU
A7
O
30
Address bus 8 for CPU
O
A8
31
Address bus 9 for CPU
O
A9
32
Address bus 10 for CPU
A10
O
33
Address bus 11 for CPU
O
A11
34
Power supply
VDD
-
35
Address bus 12 for CPU
O
A12
36
Address bus 13 for CPU
O
A13
37
Address bus 14 for CPU
A14
O
38
Address bus 15 for CPU
O
A15
39
Address bus 16 for CPU
A16
O
40
Address bus 17 for CPU
O
A17
41
Connect to TP913
A18
-
42
Connect to TP912
A19
-
43
Ground
-
VSS
44
Connect to TP911
A20
-
45
Connect to TP910
-
TXSEL
46
HAGUP
O
47
Connect to TP311
TCLOSE
-
48
Connect to TP310
-
TOPEN
49
HMFON
50
Detection switch of traverse
I
TRVSW
inside
Function
Pin No.
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
Symbol
I/O
I
Elevator UP/DOWN switch detect
SWUPDN
SWOPEN
I
Tray OPEN/CLOSE switch detect
Serial enable signal for ADSC
O
ADSCEN
Power supply
VDD
-
Serial enable signal for FEP
FEPEN
O
Standby signal for FEP
O
SLEEP
Non connect
BUSY
-
Communication Request
O
REQ
CIRC command select
CIRCEN
O
Connect to TP308
-
-
Ground
-
VSS
EEPROM chip select
EPCS
O
EEPROM clock
O
EPSK
EEPROM data input
DPDI
I
EEPROM data output
O
EPDO
Power supply
-
VDD
Communication clock
SCLKO
I
Communication input data
I
S2UDT
Communication output data
U2SDT
O
Clock for ADSC serial
O
CPSCK
ADSC serial data input
I
SDIN
ADSC serial data output
SDOUT
O
Not use
-
-
Not use
-
-
Not use
-
NMI
Interrupt input of ADSC
I
ADSCIRQ
Interrupt input of ODC
ODCIRQ
I
Interrupt input of ZIVA
I
DECIRQ
Not use
CSSIRQ
-
Interruption of system control
I
ODCIRQ2
Address data selection input
I
ADSEP
Reset input
RST
I
Power supply
-
VDD
Test signal 1 input
TEST1
I
Test signal 2 input
I
TEST2
Test signal 3 input
I
TEST3
Test signal 4 input
TEST4
I
Test signal 5 input
I
TEST5
Test signal 6 input
TEST6
I
Test signal 7 input
I
TEST7
Test signal 8 input
TEST8
I
Ground
VSS
-
Data bus 0 of CPU
I/O
D0
Data bus 1 of CPU
D1
I/O
Data bus 2 of CPU
I/O
D2
Data bus 3 of CPU
D3
I/O
Data bus 4 of CPU
D4
I/O
Data bus 5 of CPU
I/O
D5
Data bus 6 of CPU
D6
I/O
Data bus 7 of CPU
I/O
D7
XV-F80BK/XV-F85GD
Function
1-37
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