Block Diagram - Altera Cyclone III 3C120 Reference Manual

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Block Diagram

Figure 1–1. Cyclone III Development Board Block Diagram
Cyclone III 3C120 Development Board Reference Manual
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■ Power supply
14 V – 20 V DC input
■
On-board power measurement circuitry
■
Up to 19.8 W per HSMC interface
■
■ Mechanical
6" × 8" board
■
Bench-top design
■
1
The Cyclone III FPGA Development Kit ships with additional HSMC daughter card
loopback and break-out headers for convenient testing of some of the HSMC signals.
For more details regarding these test daughter cards, refer to their respective
schematics at these locations in the installed kit directory:
<path>\board_design_files\schematic\breakout_hsmc
■
debug_header_breakout.pdf
■ <path>\board_design_files\schematic\loopback_hsmc
loopback_test_lowcost.pdf
Figure 1–1 shows the functional block diagram of the Cyclone III development board.
Power
USB
Measure/
2.0
Display
2.5V CMOS
MAX II
Device (x32)
8MB SRAM
1.8V CMOS
(x32)
64MB Flash
SMA Input
(x16)
1.8V SSTL
256MB DDR2
Dual Channel
(x72)
HSMC Port A
HSMC Port B
125 MHz
XTAL
2.5V CMOS
2.5V CMOS
Cyclone III
EP3C120F780
SMA Output
2.5V CMOS
50 MHz
Buttons/ Quad 7-Seg/
Switches User LEDs
Chapter 1: Overview
General Description
RJ-45
Jack
10/100/1000
Ethernet
Graphics LCD
Character LCD
LP Filter and
Audio Amp
PC
Speaker
Header
© March 2009 Altera Corporation