Asynchronous Shift Register: Asft(052) - Omron CVM1D Operation Manual

Shift Instructions
Example
0000
05
0000
06
0000
07
0000
08
0000
09

5-14-3 ASYNCHRONOUS SHIFT REGISTER: ASFT(052)

Ladder Symbol
(052)
ASFT C
Variations
j ASFT(052)
Description
In the following example, CIO bits 000005, 000006, 000007, and 000008 are
used to control the bits of C used in j SFTR(051). The shift register is between
words 0020 and 0021, and it is controlled through bit 000009.
(051)
jSFTR
0050 0020 0021
Operand Data Areas
C: Control word
St E
St: Starting word
E: End word
When the execution condition is OFF, ASFT(052) is not executed. When the ex-
ecution condition is ON, ASFT(052) is used to create and control a reversible
asynchronous word shift register between St and E. This shift register reverses
the contents of adjacent words when the content of one of the words is zero and
the other is non-zero.
Bit 13 of C determines whether the non-zero is shifted toward St or toward E. By
repeating the instruction several times, all of the words with a content of zero
accumulate at the lower or higher end of the range defined by St and E. If no
words in the register contain zero or all of the words with a content of zero have
accumulated at one end of the range, nothing is shifted.
When the Reset Bit is ON, the content of every word from St to E is set to zero.
0050
12
Direction
0050
13
Status to input
0050
14
Shift pulse
0050
15
Reset
CIO, G, A, DM, DR, IR
CIO, G, A, DM
CIO, G, A, DM
Section 5-14
Address Instruction Operands
00000 LD 000005
00001 OUT 005012
00002 LD 000006
00003 OUT 005013
00004 LD 000007
00005 OUT 005014
00006 LD 000008
00007 OUT 005015
00008 LD 000009
jSFTR(051)
00009
0050
0020
0021
151