Omron CVM1D Operation Manual page 80

Mnemonic Code
Combining AND LOAD and
OR LOAD
0000 0000
00 01
Block
a
0000 0000
00 01
Block
a
The first of each pair of conditions is converted to LOAD with the assigned bit
operand and then ANDed with the other condition. The first two blocks can be
coded first, followed by OR LOAD, the last block, and another OR LOAD, or the
three blocks can be coded first followed by two OR LOADs. The mnemonic code
for both methods is shown to the right of the ladder diagram.
Again, with the second method, a maximum of eight blocks can be combined.
There is no limit to the number of blocks that can be combined with the first meth-
od.
Both of the coding methods described above can also be used when using AND
LOAD and OR LOAD, as long as the number of blocks being combined does not
exceed eight.
The following diagram contains only two logic blocks as shown. It is not neces-
sary to further separate block b components, because it can be coded directly
using only AND and OR.
0000 0000
02 03
0002
01
0000
04
Block
b
Although the following diagram is similar to the one above, block b in the diagram
below cannot be coded without separating it into two blocks combined with OR
LOAD. In this example, the three blocks have been coded first and then OR
LOAD has been used to combine the last two blocks followed by AND LOAD to
combine the execution condition produced by the OR LOAD with the execution
condition of block a.
When coding the logic block instructions together at the end of the logic blocks
they are combining, they must, as shown below, be coded in reverse order, i.e.,
the logic block instruction for the last two blocks is coded first, followed by the
one to combine the execution condition resulting from the first logic block
instruction and the execution condition of the logic block third from the end, and
on back to the first logic block that is being combined.
Block
b1
0000 0000
02 03
0000 0002
04 02
Block
b2
Block
b
0005
01
Address Instruction
00000
00001
00002
00003
00004
00005
00006
00007
Address Instruction Operands
00000 LD NOT
0005
02
00001 AND
00002 LD
00003 AND NOT
00004 LD NOT
00005 AND
00006 OR LD
00007 AND LD
00008 OUT
Section 4-4
Operands
LD 000000
AND NOT 000001
LD 000002
AND 000003
OR 000201
OR 000004
AND LD —
OUT 000501
000000
000001
000002
000003
000004
000202
—
—
000502
75