Renesas RZ/T2M User Manual page 26

Renesas Starter Kit+ for RZ/T2M
Ethernet signal
ETH2_TXCLK
ETH2_TXEN
ETH2_TXD0
ETH2_TXD1
ETH2_TXD2
ETH2_TXD3
ETH2_RXCLK
ETH2_RXDV
ETH2_RXD0
ETH2_RXD1
ETH2_RXD2
ETH2_RXD3
ETH2_REFCLK
Ethernet signal
ETH_MDIO
ETH2_MDIO
ETH_MDC
ETH2_MDC
Default PHY setting items
PHY Address
MAC Interface
Isolate
Speed
Duplex
Auto negotiation
R20UT4939EG0100 Rev. 1.00
Apr 20, 2022
Table 5-17: Ethernet Connections (ETH2)
RGMII: Transmit clock output
RGMII: Transmit data enable / Transmit data error
RGMII: Transmit data0
RGMII: Transmit data1
RGMII: Transmit data2
RGMII: Transmit data3
RGMII: Receive clock input
RGMII: Receive data valid / Receive data error
RGMII: Receive data0
RGMII: Receive data1
RGMII: Receive data2
RGMII: Receive data3
Outputs 25MHz clock for EtherPHY2
Table 5-18: Ethernet Connections (ETH0/ETH1/ETH2)
Management data I/O
Management data I/O
Management data clock
Management data clock
Table 5-19: Default PHY setting
Function
Function
Default PHY setting contents
ETH0 (IC35): = 0
ETH1 (IC31): = 1
ETH2 (IC16): = 2
RGMII
Disable
Depends auto negotiation
Full-Duplex
Enable
5. User Circuitry
MPU
Port Pin
P00_6 D3
P00_2 B1
P01_5 F3
P01_4 H5
P01_3 D1
P01_2 D2
P24_1 C3
P00_1 F5
P23_7 B3
P24_0 C4
P24_2 E5
P00_0 B2
P00_3 C2
MPU
Port Pin
P09_0 T7
P01_0 E3
P08_7 W5
P01_1 H6
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