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Internal I/O Connectors
X
LPC Connector
JP4
CPU FAN
DDR4_1
USB7/8
2
System
4
1
1
1
+12V Power
PS2
Fan 1
1
5
8
5
2
6
JP2
Battery
1
5
2
6
JP3
VGA
1
5
2
6
COM 1
Socket LGA1151
JP1
1
5
HDMI
DP++
LAN 2
USB3_1/2
USB2_1/2
LAN 1
USB3_3/4
USB2_3/4
1
JP27
Mic-in
M.2 M Key
Line-out
Line-in (opt.)
PCIe 1 (PCIe x16)
DDR4_2
1
2
LAN LED
PCI 1
7
8
Intel
1
10
USB2_5/6
PCIe 2 (PCIe x4)
Front Audio
USB3_5/6
Q470E/H420E
20
11
1
2
PCI 2
9
10
JP26
S/PDIF
PCI 3
1
1
M.2 E Key
2
6
2230
PCI 4
1
5
(Opt.)
JP23
5
1
1
JP10
PCI 5
Buzzer
6
2
5
1
JP8
6
2
JP6
5
1
2
10
1
10
1
6
2
2
2
2
5
1
1
1
1
1
1
JP7
1
11
1
9
1
9
6
2
1
Digital I/O
JP11/12/13/14/15
DIO
COM5
COM6
USB2_
USB2_10
Power
9/14
The Low Pin Count Interface was defined by Intel
tion towards legacy free systems. It allows the integration of low-bandwidth legacy I/O compo-
nents within the system, which are typically provided by a Super I/O controller. Furthermore, it
can be used to interface firmware hubs, Trusted Platform Module (TPM) devices and embed-
ded controller solutions. Data transfer on the LPC bus is implemented over a 4 bit serialized
data interface, which uses a 33MHz LPC bus clock. For more information about LPC bus refer
to the Intel
Low Pin Count Interface Specification Revision 1.1'. The table below indicates the
®
pin functions of the LPC connector.
Pin
Assignment
1
CLK
3
RST#
5
FRAME#
7
LAD3
9
LAD2
11
SERIRQ
13
5V5B
User's Manual | CMS631
„ LPC Connector
14
13
DDR4_3
14
13
LPC
2
1
12
24
2
1
ATX Power
1
13
1
2
Front
Panel
11
SPI Flash
BIOS
10
USB2
2
1
11/12
DDR4_4
SATA 0
SATA 1
(R0)
(R1)
SATA 2
SATA 3
(R2)
(R3)
JP28
SATA 4
1
1
(R4)
1
CN37
6
1
M.2 M Key
JP24
SATA 5
(R5)
9
COM4
2
1
SDJ2
System Fan 2
1
2
1
9
1
9
COM2
COM3
System Fan 3
Corporation to facilitate the industry's transi-
®
Pin
Assignment
2
L_AD1
4
L_AD0
6
VCC3
8
GND
10
---
12
GND
14
5V
Chapter 2
HARDWARE INSTALLATION
26
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