Holtek HT68F Series Manual page 71

HT68F20/HT68F30/HT68F40/HT68F50/HT68F60
HT68FU30/HT68FU40/HT68FU50/HT68FU60
Enhanced I/O Flash Type 8-Bit MCU with EEPROM
When the reset pin is driven low by external hardware, most of the microcontroller pins will
be forced into a high impedance condition. However special attention must be made to the
PA5/C1X/SDO and PB2/OSC2 pins as these two pins will be forced into a logical output low
condition when the reset pin is held low. For this reason it is recommended that these two pins
are not connected to low impedance sources in the application circuit to eliminate the possibility
of two low impedance sources being connected together. This situation only occurs when the
reset pin is pulled low by external hardware and not during a power on or other reset type.
• Low Voltage Reset – LVR
The microcontroller contains a low voltage reset circuit in order to monitor the supply voltage
of the device, which is selected via a configuration option. If the supply voltage of the device
drops to within a range of 0.9V~V
will automatically reset the device internally. The LVR includes the following specifications:
For a valid LVR signal, a low voltage, i.e., a voltage in the range between 0.9V~V
for greater than the value t
not exceed t
LVR
specified voltage values for V
• Watchdog Time-out Reset during Normal Operation
The Watchdog time-out Reset during normal operation is the same as a hardware RES pin reset
except that the Watchdog time-out flag TO will be set to "1".
• Watchdog Time-out Reset during SLEEP or IDLE Mode
The Watchdog time-out Reset during SLEEP or IDLE Mode is a little different from other kinds
of reset. Most of the conditions remain unchanged except that the Program Counter and the Stack
Pointer will be cleared to "0" and the TO flag will be set to "1". Refer to the A.C. Characteristics
for t details.
SST
Note: The t is 15~16 clock cycles if the system clock source is provided by ERC or HIRC.
SST
The t is 1024 clock for HXT or LXT. The t
SST
Rev. 2.10
Pin Name
PA5/C1X/SDO
PB2/OSC2
Other pins
Reset Pin Forced Low – Pin Status
such as might occur when changing the battery, the LVR
LVR
specified in the A.C. characteristics. If the low voltage state does
LVR
, the LVR will ignore it and will not perform a reset function. One of a range of
can be selected using configuration options.
LVR
L V R
I n t e r n a l R e s e t
Low Voltage Reset Timing Chart
W D T T i m e - o u t
I n t e r n a l R e s e t
Note: t is power-on delay, typical time=100ms
RSTD
WDT Time-out Reset during Normal Operation Timing Chart
W D T T i m e - o u t
I n t e r n a l R e s e t
WDT Time-out Reset during SLEEP or IDLE Timing Chart
71
Pin Status
O�tp�t Low
O�tp�t Low
High Impedance
t t
R S T D + S S T
t t
R S T D + S S T
t
S S T
is 1~2 clock for LIRC.
SST
must exist
LVR
���� 02� 201�