Holtek HT68F Series Manual page 248

Enhanced i/o flash type 8-bit mcu with eeprom
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Mnemonic
Data Move
MOV A�[m]
Move Data Memor� to ACC
MOV [m]�A
Move ACC to Data Memor�
MOV A�x
Move immediate data to ACC
Bit Operation
CLR [m].i
C�ear bit of Data Memor�
SET [m].i
Set bit of Data Memor�
Branch Operation
�MP addr
��mp �nconditiona���
SZ [m]
Skip if Data Memor� is zero
SZA [m]
Skip if Data Memor� is zero with data movement to ACC
SZ [m].i
Skip if bit i of Data Memor� is zero
SNZ [m].i
Skip if bit i of Data Memor� is not zero
SIZ [m]
Skip if increment Data Memor� is zero
SDZ [m]
Skip if decrement Data Memor� is zero
SIZA [m]
Skip if increment Data Memor� is zero with res��t in ACC
SDZA [m]
Skip if decrement Data Memor� is zero with res��t in ACC
CALL addr
S�bro�tine ca��
RET
Ret�rn from s�bro�tine
RET A�x
Ret�rn from s�bro�tine and �oad immediate data to ACC
RETI
Ret�rn from interr�pt
Table Read Operation
TABRD [m]
Read table (specific page) to TBLH and Data Memory
TABRDC [m]
Read tab�e (c�rrent page) to TBLH and Data Memor�
TABRDL [m]
Read tab�e (�ast page) to TBLH and Data Memor�
Miscellaneous
NOP
No operation
CLR [m]
C�ear Data Memor�
SET [m]
Set Data Memor�
CLR WDT
C�ear Watchdog Timer
CLR WDT1
Pre-c�ear Watchdog Timer
CLR WDT2
Pre-c�ear Watchdog Timer
SWAP [m]
Swap nibb�es of Data Memor�
SWAPA [m]
Swap nibb�es of Data Memor� with res��t in ACC
HALT
Enter power down mode
Note: 1. For skip instructions, if the result of the comparison involves a skip then two cycles are required, if no
skip takes place only one cycle is required.
2. Any instruction which changes the contents of the PCL will also require 2 cycles for execution.
3. For the "CLR WDT1" and "CLR WDT2" instructions the TO and PDF flags may be affected by the
execution status. The TO and PDF flags are cleared after both "CLR WDT1" and "CLR WDT2"
instructions are consecutively executed. Otherwise the TO and PDF flags remain unchanged.
Rev. 2.10
HT68F20/HT68F30/HT68F40/HT68F50/HT68F60
HT68FU30/HT68FU40/HT68FU50/HT68FU60
Enhanced I/O Flash Type 8-Bit MCU with EEPROM
Description
2�8
Cycles
Flag Affected
1
None
1
Note
None
1
None
1
Note
None
1
Note
None
2
None
1
Note
None
1
Note
None
1
Note
None
1
Note
None
1
Note
None
1
Note
None
1
Note
None
1
Note
None
2
None
2
None
2
None
2
None
2
Note
None
2
Note
None
2
Note
None
1
None
1
Note
None
1
Note
None
1
TO� PDF
1
TO� PDF
1
TO� PDF
Note
1
None
1
None
1
TO� PDF
���� 02� 201�

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