Enhanced Tm Operation - Holtek HT68F Series Manual

HT68F20/HT68F30/HT68F40/HT68F50/HT68F60
HT68FU30/HT68FU40/HT68FU50/HT68FU60
Enhanced I/O Flash Type 8-Bit MCU with EEPROM

Enhanced TM Operation

At its core is a 10-bit count-up/count-down counter which is driven by a user selectable internal
or external clock source. There are three internal comparators with the names, Comparator A,
Comparator B and Comparator P. These comparators will compare the value in the counter with the
CCRA, CCRB and CCRP registers. The CCRP comparator is 3-bit wide whose value is compared
with the highest 3-bit in the counter while CCRA and CCRB are 10-bit wide and therefore compared
with all counter bits.
The only way of changing the value of the 10-bit counter using the application program, is to
clear the counter by changing the TnON bit from low to high. The counter will also be cleared
automatically by a counter overflow or a compare match with one of its associated comparators.
When these conditions occur, a TM interrupt signal will also usually be generated. The Enhanced
Type TM can operate in a number of different operational modes, can be driven by different clock
sources including an input pin and can also control output pins. All operating setup conditions are
selected using relevant internal registers.
Enhanced Type TM Register Description
Overall operation of the Enhanced TM is controlled using a series of registers. A read only register
pair exists to store the internal counter 10-bit value, while two read/write register pairs exist to store
the internal 10-bit CCRA and CCRB value. The remaining three registers are control registers which
setup the different operating and control modes as well as the three CCRP bits.
Name Bit 7
TM1C0 T1PAU
TM1C1 T1AM1
TM1C2 T1BM1
TM1DL D7
TM1DH —
TM1AL D7
TM1AH —
TM1BL D7
TM1BH —
Rev. 2.10
Bit 6 Bit 5 Bit 4
T1CK2 T1CK1 T1CK0
T1AM0 T1AIO1 T1AIO0
T1BM0 T1BIO1 T1BIO0
D6 D5 D�
— — —
D6 D5 D�
— — —
D6 D5 D�
— — —
10-bit Enhanced TM Register List (if ETM is TM1)
1�3
Bit 3 Bit 2 Bit 1
T1ON T1RP2 T1RP1
T1AOC T1APOL T1CDN
T1BOC T1BPOL T1PWM1 T1PWM0
D3 D2 D1
— — D9
D3 D2 D1
— — D9
D3 D2 D1
— — D9
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Bit 0
T1RP0
T1CCLR
D0
D8
D0
D8
D0
D8