Holtek HT68F Series Manual page 117

HT68F20/HT68F30/HT68F40/HT68F50/HT68F60
HT68FU30/HT68FU40/HT68FU50/HT68FU60
Enhanced I/O Flash Type 8-Bit MCU with EEPROM
Co�nter Va��e
CCRA > 0 Co�nter c�eared b� CCRA va��e
0x3FF
CCRA
CCRP
TnON
TnPAU
TnPOL
CCRA Int.
F�ag TnAF
CCRP Int.
F�ag TnPF
TnPF not
generated
TM O/P Pin
O�tp�t Togg�e with
O�tp�t pin set to
initia� Leve� Low
if TnOC=0
Here TnIO [1:0] = 11
Togg�e O�tp�t se�ect
Note: 1. With TnCCLR=1, a Comparator A match will clear the counter
2. The TM output pin is controlled only by the TnAF flag
3. The output pin is reset to its initial state by a TnON bit rising edge
4. The TnPF flag is not generated when TnCCLR=1
Rev. 2.10
TnCCLR = 1; TnM [1:0] = 00
Res�me
Pa�se
O�tp�t not affected b�
TnAF f�ag. Remains High
�nti� reset b� TnON bit
TnAF f�ag
Note TnIO [1:0] = 10
Active High O�tp�t se�ect
Compare Match Output Mode -- TnCCLR=1
117
CCRA = 0
Co�nter overf�ow
CCRA=0
Stop Co�nter Restart
Time
No TnAF f�ag
generated on
CCRA overf�ow
O�tp�t does
not change
O�tp�t Inverts
when TnPOL is high
O�tp�t Pin
Reset to Initia� va��e
O�tp�t contro��ed b�
other pin-shared f�nction
���� 02� 201�