Holtek HT68F Series Manual page 154

Co�nter Va��e
CCRA > 0 Co�nter c�eared b� CCRA va��e
0x3FF
CCRA
CCRB
TnON
TnPAU
TnBPOL
CCRA Int.
F�ag TnAF
CCRB Int.
F�ag TnBF
TPnB O/P
Pin
O�tp�t Togg�e with
TnBF f�ag
O�tp�t pin set to
initia� Leve� Low
if TnBOC=0
Here TnBIO [1:0] = 11
Togg�e O�tp�t se�ect
ETM CCRB Compare Match Output Mode -- TnCCLR=1
Note: 1. With TnCCLR=1, a Comparator A match will clear the counter
2. The TPnB output pin is controlled only by the TnBF flag
3. The TPnB output pin is reset to its initial state by a TnON bit rising edge
4. The TnPF flag is not generated when TnCCLR=1
Rev. 2.10
HT68F20/HT68F30/HT68F40/HT68F50/HT68F60
HT68FU30/HT68FU40/HT68FU50/HT68FU60
Enhanced I/O Flash Type 8-Bit MCU with EEPROM
TnCCLR = 1; TnBM [1:0] = 00
Res�me
Pa�se
O�tp�t not affected b�
TnBF f�ag. Remains High
�nti� reset b� TnON bit
Note TnBIO [1:0] = 10
Active High O�tp�t se�ect
15�
CCRA = 0
Co�nter overf�ow
CCRA=0
Stop Co�nter Restart
Time
No TnAF f�ag
generated on
CCRA overf�ow
O�tp�t Inverts
when TnBPOL is high
O�tp�t Pin
Reset to Initia� va��e
O�tp�t contro��ed b�
other pin-shared f�nction
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