Holtek HT68F Series Manual page 59

HT68F20/HT68F30/HT68F40/HT68F50/HT68F60
HT68FU30/HT68FU40/HT68FU50/HT68FU60
Enhanced I/O Flash Type 8-Bit MCU with EEPROM
Bit 3 LTO: Low speed system oscillator ready flag
0: Not ready
1: Ready
This is the low speed system oscillator ready flag which indicates when the low speed
system oscillator is stable after power on reset or a wake-up has occurred. The flag
will be low when in the SLEEP0 Mode but after a wake-up has occurred, the flag will
change to a high level after 1024 clock cycles if the LXT oscillator is used and 1~2
clock cycles if the LIRC oscillator is used.
Bit 2 HTO: High speed system oscillator ready flag
0: Not ready
1: Ready
This is the high speed system oscillator ready flag which indicates when the high speed
system oscillator is stable. This flag is cleared to "0" by hardware when the device is
powered on and then changes to a high level after the high speed system oscillator is
stable. Therefore this flag will always be read as "1" by the application program after
device power-on. The flag will be low when in the SLEEP or IDLE0 Mode but after
a wake-up has occurred, the flag will change to a high level after 1024 clock cycles if
the HXT oscillator is used and after 15~16 clock cycles if the ERC or HIRC oscillator
is used.
IDLEN: IDLE Mode control
Bit 1
0: Disable
1: Enable
This is the IDLE Mode Control bit and determines what happens when the HALT
instruction is executed. If this bit is high, when a HALT instruction is executed the
device will enter the IDLE Mode. In the IDLE1 Mode the CPU will stop running
but the system clock will continue to keep the peripheral functions operational, if
FSYSON bit is high. If FSYSON bit is low, the CPU and the system clock will all stop
in IDLE0 mode. If the bit is low the device will enter the SLEEP Mode when a HALT
instruction is executed.
HLCLK: system clock selection
Bit 0
0: f
1: f
This bit is used to select if the f
system clock. When the bit is high the f
f /2~f
H
to the f
Rev. 2.10
/2~f /64 or f
H H L
H
clock or the f
H
/64 or f clock will be selected. When system clock switches from the f
H L
clock and the f clock will be automatically switched off to conserve power.
L H
59
/2~f /64 or f clock is used as the
H H L
clock will be selected and if low the
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clock
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