Uart Data Transfer Scheme; Uart Commands - Holtek HT68F Series Manual

HT68F20/HT68F30/HT68F40/HT68F50/HT68F60
HT68FU30/HT68FU40/HT68FU50/HT68FU60
Enhanced I/O Flash Type 8-Bit MCU with EEPROM

UART Data Transfer Scheme

The following block diagram shows the overall data transfer structure arrangement for the UART.
The actual data to be transmitted from the MCU is first transferred to the TXR register by the
application program. The data will then be transferred to the Transmitter Shift Register named TSR
from where it will be shifted out, LSB first, onto the TX pin at a rate controlled by the Baud Rate
Generator. Only the TXR register is accessible to the application program, the Transmitter Shift
Register is not mapped into the Data Memory area and is inaccessible to the application program.
Data to be received by the UART is accepted on the external RX pin, from where it is shifted in,
LSB first, to the Receiver Shift Register named RSR at a rate controlled by the Baud Rate Generator.
When the shift register is full, the data will then be transferred from the shift register to the internal
RXR register, where it is buffered and can be manipulated by the application program. Only the
RXR register is accessible to the application program, the Receiver Shift Register is not mapped
into the Data Memory area and is inaccessible to the application program. It should be noted that the
actual register for data transmission and reception, although referred to in the text, and in application
programs, as separate TXR and RXR registers, only exists as a single shared register physically.
This shared register known as the TXR/RXR register is used for both data transmission and data
reception.
Transmitter Shift Register (TSR)
MSB
..............................
TX Register (TXR)
Data to be transmitted

UART Commands

There are both read and write commands for the UART Module. For reading and writing to registers
both command and address information is contained within a single byte. The format for reading and
writing is shown in the following table.
Command Type
Read FIFO
Read Register
Write FIFO
Write Register
Rev. 2.10
LSB TX Pin RX Pin
Ba�d Rate
Generator
UART Data Transfer Scheme
UART Data Transfer Scheme
Bit 7 Bit 6 Bit 5
0 0 0
0 0 0
0 0 0
0 0 0
227
Receiver Shift Register (RSR)
MSB
..............................
RX Register (RXR)
Data received
Bit 4 Bit 3 Bit 2 Bit 1
0 0 ×
1 0 A2
0 1 ×
1 1 A2
Note: "×" here stands for "don't care"
LSB
B�ffer 3
B�ffer 2
B�ffer 1
Bit 0
× ×
A1 A0
× ×
A1 A0
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