Index
gate-rising edge type
generating pulses
,
group delay
78
H
hardware features
high-edge gate type
high-level gate type
hot-swapping
34
I
IEPE features
77
IEPE support
120
inprocess buffers
input
channels
76
configuration, single-ended
ranges
76
resolution
77
input FIFO
83
Input Trigger LED
internal
clock
93
gate type
124
internal clock
123
internal excitation current source
interrupts
115
L
LabVIEW
21
,
LED
34
35
Input Trigger
80
Output Trigger
,
Power
177
179
,
USB
177
179
LED status indicator
legacy CPL elevated
lines, digital I/O
locking USB cable
low-edge gate type
low-level gate type
LV-Link
21
M
master and slave synchronization
master oscillator, specifications
MATLAB
21
188
125
,
97
98
85
16
124
124
116
48
,
,
,
80
81
177
179
120
,
,
,
81
177
179
,
,
88
177
179
176
38
103
34
124
124
115
155
MaxDifferentialChannels
MaxExtClockDivider
123
MaxFrequency
123
MaxMultiScanCount
116
MaxRetriggerFreq
116
MaxSingleEndedChannels
measure counters
features
99
wiring
59
measuring pulses
96
MinExtClockDivider
123
MinFrequency
123
MinRetriggerFreq
116
muting the output voltage
N
negative threshold trigger
number of
differential channels
117
gains
117
I/O channels
117
resolutions
118
scans per trigger
116
single-ended channels
voltage ranges
118
NumberOfChannels
117
NumberOfRanges
118
NumberOfResolutions
118
NumberOfSupportedGains
Nyquist Theorem
77
O
olDiagReadReg
182
olDiagWriteReg
182
one-shot pulse output
97
Open Layers Control panel
Open Layers Control Panel applet
operation modes
continuous analog input
continuous digital input
continuous digital output
single-value analog input
single-value analog output
single-value digital I/O
single-values analog input
waveform generation
85
oscillator, specifications
output
clock sources
84
117
117
115
,
121
122
117
117
,
124
38
129
79
103
103
78
85
103
78
155
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