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External Clock Drive Waveforms
Figure 67. External Clock
VIL1
Table 37. External Clock Drive
Symbol
Parameter
1/t
Oscillator Frequency
CLCL
t
Clock Period
CLCL
t
High Time
CHCX
t
Low Time
CLCX
t
Rise Time
CLCH
t
Fall Time
CHCL
Note:
See "External Data Memory Timing" on page 84. for a description of how the duty cycle influences the timing for the External
Data Memory
Figure 68. External RAM Timing
System Clock O
Address [15..8]
Data / Address [7..0]
Data / Address [7..0]
Note: Clock cycle T3 is only present when external SRAM waitstate is enabled
T3 is only present when wait-state is enabled.
VIH1
T1
0
ALE
4
Prev. Address
Prev. Address
3a
WR
Prev. Address
Address
RD
V
= 2.7V to 4.0V
CC
Min
Max
0
4
250
100
100
1.6
1.6
T2
1
7
Address
2
13
Address
6
3b
5
10
8
AT90S4414/8515
V
= 4.0V to 6.0V
CC
Min
Max
0
8
125
50
50
0.5
0.5
T3
T4
15
Data
16
11
Data
9
12
Units
MHz
ns
ns
ns
µs
µs
Addr.
14
Addr.
83
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