Casio QT-8000 Service Manual page 37

CPU & PCI BUS CONTROL:
The options for these items are found in its sub menu. By pressing the <ENTER> key,
you are prompt to enter the sub menu of the detailed options as shown below:
CPU to PCI Write Buffer
PCI Master 0 WS Write
PCI Delay Transaction
↑↓→←:Move Enter: Select +/-/PU/PD:Value F10:Save ESC:Exit F1:General Help
F5: Previous Values
Descriptions on each item above are as follows:
1. CPU to PCI Write Buffer
When Enabled, the CPU can write up to four dwords of data to the PCI write buffer
before the CPU must wait for the PCI bus cycles to finish. When Disabled, the
CPU must wait after each write cycle until the PCI bus signals that it is ready to
receive more data.
2. PCI Master 0 WS Write
When Enabled, writes to the PCI bus are executed with zero wait states.
3. PCI Delay Transaction
The chipset has an embedded 32-bit posted write buffer to support delay
transactions cycles. Select Enabled to support compliance with PCI specification
version 2.1.
MEMORY HOLE:
In order to improve performance, certain space in memory can be reserved for ISA
cards. This memory must be mapped into the memory space below 16MB.
SYSTEM BIOS CACHEABLE:
This item allows you to enable caching of the system BIOS ROM at F0000h-FFFFFh,
resulting in better system performance. However, if any program writes to this memory
area, a system error may result.
Phoenix – AwardBIOS CMOS Setup Utility
CPU & PCI Bus Control
[Enabled]
[Enabled]
[Disabled]
F6:Fail-Safe Defaults
Table 3 – CPU & PCI Bus Control sub menu
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Item Help
Menu Level }}
F7:Optimized Defaults