Renesas RL78/I1D Application Note page 36

RL78/I1D
4.7.20. Flash operation mode switching (LP) processing
Figure 4.23 shows the flowchart of the flash operation mode switching (LP) processing.
switch_flashmode_to_LP
Set the middle-speed on-chip
oscillator clock frequency to 1MHz
No
Middle-speed on-chip oscillator
Set the middle-speed on-chip
the main on-chip oscillator clock
Set the high-speed on-chip oscillator
Set the regulator mode to
Set flash operation mode to
LP (low-power main) mode
Set the regulator mode to
the low-power consumption setting
Updated status flag variable of
flash operation mode
Figure 4.23
R01AN3597EJ0100 Rev.1.00
Jan. 31, 2017
MCS1 = 0?
Yes
operating
oscillator clock to
MCS1 = 1?
Yes
to stop
the normal setting
return
Flash operation mode switching (LP normal) processing
MOCODIV register 02H
Main on-chip oscillator clock status in the case of
high-speed on-chip oscillator clock, switch to
the middle-speed on-chip oscillator clock.
MIOEN bit 0 : Middle-speed on-chip oscillator operating
MCM1 bit 1 : Select middle-speed on-chip oscillator clock
Wait until the status of the main on-chip oscillator clock is
No
switched to the middle-speed on-chip oscillator clock
HIOSTOP bit 1 : High-speed on-chip oscillator stop
PMMC register
MCSEL bit 0
FLMWEN bit 1 :Rewriting the FLMODE register is enabled
FLMODE register 40H : LV (low-power main) mode
FLMWEN bit 0 : Rewriting the FLMODE register is disabled
PMMC register
MCSEL bit 1
g_flash_mode _08_FLAHMODE_LP
Operation state switching IAR
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