Renesas RL78/I1D Application Note page 34

RL78/I1D
4.7.17. A/D converter initialization
Figure 4.20 shows the flowchart of A/D converter initialization.
R_ADC_Create
Reset control of A/D converter
A/D converter clock provision
A/D converter circuit operation stop
INTAD interrupt disable
Clear INTAD interrupt request flag
A/D converter interrupt priority level 0 setting
A/D converter initialization
Set conversion time about 76us
Set select mode
Set software trigger mode
Set one shot conversion mode
Reference voltage power supply setting
12-bit resolution
Set + side power supply from AV
Set – side power supply from AV
Conversion result comparison upper/Lower limit setting
Set comparison upper limit value to FFH
Set comparison lower limit value to 00H
Analog input channel/ input source definition
Set analog input source to internal reference
voltage (1.45V)
return
R01AN3597EJ0100 Rev.1.00
Jan. 31, 2017
PRR0 register
ADCRES bit
ADCRES bit
PER0 register
ADCEN bit
ADM0 register
ADMK bit
ADIF bit
ADPR0 bit
ADPR1 bit
ADM0 register
FR2-FR0 bit=010B
ADMD bit=0
ADM1 register
ADTMD1-ADTMD0 bits= 00B :Software trigger mode
ADM2 register
ADTYP = 0： 12-bit resolution
ADREFP1-ADREF0 bits = 00B :Provide from AV
DD
ADREFM = 0
SS
ADUL register
Conversion result comparison upper value setting
ADLL register
Conversion result comparison lower value setting
ADS register
ADS4-ADS0 bits = 00001B
ADISS bit = 1
Figure 4.20 A/D converter initialization
Operation state switching IAR
1: A/D converter reset state
0: A/D converter reset release
1: Start input clock provision
00H
1: A/D conversion complete interrupt disable
0: Interrupt request flag clear
0
0
14H
: f
CLK
: Select mode
00H
00H
:Provide from AV
FFH
00H
81H
/8 (f =8 MHz)
CLK
DD
SS
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