Renesas RL78/I1D Application Note page 22

RL78/I1D
Setting up the CPU/peripheral hardware clock (f

System clock control register (CKC)
f initial value: High-speed on-chip oscillator clock (f
CLK
Symbol: CKC
7 6
CLS CSS
0 0
Bit 6
CSS
0 Main system clock (f
1 Subsystem clock (f
Bit 4
MCM0
Selects the high-speed on-chip oscillator clock (f
0
clock (f )
MAIN
1 Selects the high-speed system clock (f
Bit 0
MCM1
0 High-speed on-chip oscillator clock
1 Middle-speed on-chip oscillator clock
Caution: For details on the register setup procedures, refer to RL78/I1D User's Manual: Hardware.
R01AN3597EJ0100 Rev.1.00
Jan. 31, 2017
CLK
5 4 3
MCS MCM0 0
0 0 0
Selection of CPU/peripheral hardware clock (f
)
MAIN
)
SUB
Main system clock (f
MAIN
) as the main system clock (f
MX
Main system clock (f
MAIN
)
)
IH
2 1
0 MCS1 MCM1
0 0
)
CLK
) operation control
) as the main system
IH
MAIN
) operation control
Operation state switching IAR
0
0
).
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