Renesas RL78/I1D Application Note page 24

RL78/I1D
4.7.7. Clock output initialization
Figure 4.8 shows the flowchart of clock output initialization.
4.7.8. INTP0 initialization
Figure 4.9 shows the flowchart of INTP0 initialization.
R01AN3597EJ0100 Rev.1.00
Jan. 31, 2017
Figure 4.8
R_INTP0_Create
INTPn interrupt disabled
Clear INTPn interrupt request flag
INTP0 interrupt priority:
Set to level 3(lowest)
INTP0 valid edge setting:
Enable the falling edge
return
Figure 4.9
Operation state switching IAR
clock output initialization
PMK6-PMK0 bit
PIF6-PIF0 bit
PPR10 bit 1
PPR00 bit 1
EGN0 bit 1
EGP0 bit 0
INTP0 initialization
1
0
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