Texas Instruments ADS867 Series Manual page 51

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For a read cycle, the next eight bits (bits 7-0) on SDI are don't care bits and SDO stays low. From the 16th SCLK
falling edge and onwards, SDO outputs the 8-bit data from the addressed register during the next eight clocks, in
MSB-first fashion. A typical timing diagram for a program register read cycle is shown in
PIN
SDI
SDO
CS
1
SCLK
SDI
SDO
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Table 8. Read Cycle Command Word
REGISTER ADDRESS
(Bits 15-9)
ADDR[6:0]
0000 000
2 6 7 8 9
ADDR [6:0]
RD
Figure 108. Program Register Read Cycle Timing Diagram
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WR/RD
(Bit 8)
0
0
15 16 17 18
10
X X X X X X
DOUT [7:0]
ADS8674 ADS8678
ADS8674, ADS8678
SBAS627 – JULY 2015
Figure 108.
DATA
(Bits 7-0)
XXXXX
DOUT[7:0]
23 24
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