Texas Instruments CDCM7005 User Manual
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Texas Instruments CDCM7005 User Manual

Texas instraments hpa/high speed communications model cdcm7005 module manual
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CDCM7005 (QFN Package)
Evaluation Module Manual
HPA/High Speed Communications
User's Guide
2005
Clock Drivers
SCAU015

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Summary of Contents for Texas Instruments CDCM7005

  • Page 1 CDCM7005 (QFN Package) Evaluation Module Manual HPA/High Speed Communications User’s Guide 2005 Clock Drivers SCAU015...
  • Page 2 TI product or service and is an unfair and deceptive business practice. TI is not responsible or liable for any such statements. Following are URLs where you can obtain information on other Texas Instruments products and application solutions:...
  • Page 3 Texas Instruments (TI) provides the enclosed product(s) under the following conditions: This evaluation kit being sold by TI is intended for use for ENGINEERING DEVELOPMENT OR EVALUATION PURPOSES ONLY and is not considered by TI to be fit for commercial use. As such, the goods being provided may not be complete in terms of required design-, marketing-, and/or manufacturing-related protective considerations, including product safety measures typically found in the end product incorporating the goods.
  • Page 4 EVM schematic located in the EVM User’s Guide. When placing measurement probes near these devices during operation, please be aware that these devices may be very warm to the touch. Copyright  2004, Texas Instruments Incorporated Mailing Address: Texas Instruments...

  • Page 5: Read This First

    About This Manual This manual explains how to use the CDCM7005 evaluation module (EVM) and provides guidelines to build the customer’s own systems. The manual includes schematics, layout, bill of materials, and a software description. How to Use This Manual This document contains the following chapters: Chapter 1—Introduction...

  • Page 6: Table Of Contents

    ..............CDCM7005 Functional Block Diagram Quick Start .
  • Page 7 ..............CDCM7005 With a Passive Loop Filter Configuration 5−1 5−2 CDCM7005 With an External Active Loop Filter Using OPA341 6−1 Component View and Silkscreen (Top Side) 6−2 Component View and Silkscreen (Bottom Side) 6−3...

  • Page 8: Introduction

    Loop bandwidth can be selected as low as 10 Hz or less, allowing the device to clean the system’s clock jitter. In non PLL mode, the CDCM7005 can be used as a simple LVPECL or LVCMOS buffer with divider options.

  • Page 9: Cdcm7005 Functional Block Diagram

    CDCM7005 Functional Block Diagram 1.1 CDCM7005 Functional Block Diagram Selected REF Signal Manual & REF_SEL Automatic freq. detect CLK Select > 2 MHz PRI_REF LVCMOS Reference Clock SEC_REF Feedback Clock SPI LOGIC CTRL_LE CTRL_DATA CTRL_CLK RESET or HOLD ÷ 1 ÷...

  • Page 10: Quick Start

    After power up, D1 is on if there is a valid reference clock and D2 is on if there is a valid VC(X)O clock for the CDCM7005. If D3 turns on, then the reference clock and the VC(X)O clocks are phase locked.

  • Page 11: Evm Hardware

    This chapter discusses the EVM hardware. Topic Board View and Connector Location Hardware Configuration ........Chapter 3 EVM Hardware Page...

  • Page 12: Board View And Connector Location

    3-state and all counters (N, M, P) are rest to zero (the initial divider settings are maintained in SPI. The three status outputs of the CDCM7005 are fed to LED indicators. D1 on indicates a valid reference input clock signal. D2 is on if the VC(X)O input clock is valid and D3 turns on if the PLL has been locked.

  • Page 13: Programming Interfaces (J30, J31)

    3.2.5 High-Speed Outputs and Inputs (J1−J4, J6−J11, J13, J14, J22, and J23) The CDCM7005 drives five differential LVPECL outputs. All PECL outputs are ac-coupled and terminated with 150 Ω to GND. This is in contrast to typical LVPECL termination, which requires V reason is to simplify the power supply scheme.

  • Page 14: Vcxo Inputs And Outputs (J16−J18)

    Hardware Configuration When the CDCM7005 is powered up, it defaults to five LVPECL outputs. However, this EVM is configured as follows: Y0 − Y2 = LVPECL Y3, Y4 = LVCMOS (in addition Y4 has an option for a custom filter) The reference input clock signal has to be applied to J1 or J6.

  • Page 15: Serial Peripheral Interface (Spi) Software

    Serial Peripheral Interface (SPI) Software This chapter discusses the serial peripheral interface software. Topic Functional Description Software Installation Chapter 4 .........

  • Page 16: Functional Description

    4.1 Functional Description Programming software here as described is intended for programming the in- ternal control register of the CDCM7005. The software runs under Win- dows98, NT, 2000, and XP. A quick installation is required prior to use. See the Software Installation section.

  • Page 17: Application Circuit Diagram

    Chapter 5 Application Circuit Diagram This chapter discusses the application circuit diagram. Topic Page Application Circuit Diagram ........Application Circuit Diagram...

  • Page 18: Application Circuit Diagram

    R1, C1, and C2 generate the dominant pole of the system. A second pole is introduced by R2 and C3. Figure 5−1. CDCM7005 With a Passive Loop Filter Configuration 130 Ω 82 Ω...

  • Page 19: External Active Loop Filter Using Opa341

    5.1.2 External Active Loop Filter Using OPA341 Figure 5−2. CDCM7005 With a External Active Loop Filter Using OPA341 PRI_REF SEC_REF CTRL_LE CTRL_DATA CTRL_CLK 130 Ω 130 Ω VC(X)O_IN VC(X)O_IN 82 Ω 82 Ω VC(X)O 491.52 MHz PECL_OUT_B V_CTRL PECL_OUT CDCM7005 10 kΩ...

  • Page 20: Parts List, Board Layouts, And Schematics

    Parts List, Board Layout, and Schematics This chapter contains the parts list, board layout, and schematics for the CDCM7005 EVM. Topic Parts List ........... . .

  • Page 21: Parts List

    Parts List 6.1 Parts List Item QTY Reference Designator C1−C9, C12, C13, C15, C17, C26, C40, C41, C46, C47, C53, C54, C56−C58, C72, C10 C11, C32, C62−C64, C68, C14, C16 C20, C22 C27−C29, C75, C76, C79, C80 C33−C35 C36, C42, C48, C37, C43, C50, C55, C65 C38, C44, C51...

  • Page 22: Board Layout

    Item QTY Reference Designator D1−D3 FLT1 J1−J4, J6−J8 J9−J11, J13, J14, J16, J18, J22, J23 J12, J25, J26, J17, J15 J21, J20 J24, J28, J29 J33, J32 JUMPER3_SMD_WVIA_CD L4, L3 L5−L7 R1, R2, R7, R9, R10, R11, R16, R18−R20, R22, R24, R26, R27, R30, R35, R48, R3, R12...
  • Page 23 4.7 kΩ smd_res_0402 smd_res_0402 NU 12K 1% smd_cap_0402 1.5 kΩ smd_res_0402 180 Ω smd_res_0402 22 Ω switch_reset PUSHBUTTON testpin_30dia T POINT R mbga_pt8mm_64_skt CDCM7005 soic14 SN74LV125 soic_round_4 NU SGA−4586 soic8 OPA341 VCXO_6 VCXO_6 STAND OFF SCREW Part Number Panasonic ERJ−2RKF1000X Panasonic ERJ−2RKF1500X...

  • Page 24: Board Layout

    Parts List 6.2 Board Layout Figure 6−1. Component View and Silkscreen (Top View) Parts List, Board Layout, and Schematics...
  • Page 25 Parts List Figure 6−2. Component View and Silkscreen (Bottom View)

  • Page 26: Top Layer View

    Parts List Figure 6−3. Top Layer View Parts List, Board Layout, and Schematics...

  • Page 27: Bottom Layer View

    Parts List Figure 6−4. Bottom Layer View...

  • Page 28: Ground Plane View

    Parts List Figure 6−5. Ground Plane View Parts List, Board Layout, and Schematics...

  • Page 29: Schematic

    Parts List Figure 6−6. Power Layer View 6.3 Schematics The following pages contain the schematics for the CDCM7005 (QFN package). 6-10...
  • Page 30 Parts List, Board Layout, and Schematics Parts List 6-11...
  • Page 31 Parts List 6-12...
  • Page 32 Parts List, Board Layout, and Schematics Parts List 6-13...
  • Page 33 Parts List 6-14 OUTB...
  • Page 34 Parts List Parts List, Board Layout, and Schematics 6-15...

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