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Summary of Contents for Texas Instruments SPRU938B
- Page 1 TMS320DM643x DMP VLYNQ Port User's Guide Literature Number: SPRU938B September 2007...
- Page 2 SPRU938B – September 2007 Submit Documentation Feedback...
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Page 3: Table Of Contents
Receive Address Map Size 4 Register (RAMS4) 3.16 Receive Address Map Offset 4 Register (RAMO4) 3.17 Chip Version Register (CHIPVER) 3.18 Auto Negotiation Register (AUTNGO) Remote Configuration Registers Appendix A VLYNQ Protocol Specifications Introduction SPRU938B – September 2007 Submit Documentation Feedback Contents Table of Contents... - Page 4 Special 8b/10b Code Groups Supported Ordered Sets VLYNQ 2.0 Packet Format VLYNQ 2.X Packets Appendix B Write/Read Performance Introduction Write Performance Read Performance Appendix C Revision History Contents SPRU938B – September 2007 Submit Documentation Feedback...
- Page 5 Receive Address Map Size 4 Register (RAMS4) Receive Address Map Offset 4 Register (RAMO4) Chip Version Register (CHIPVER) Auto Negotiation Register (AUTNGO) Packet Format (10-bit Symbol Representation) SPRU938B – September 2007 Submit Documentation Feedback List of Figures List of Figures...
- Page 6 Packet Format (10-bit Symbol Representation) Description Scaling Factors Expected Throughput (VLYNQ Interface Running at 76.5 MHZ and 99 MHZ) Relative Performance with Various Latencies Document Revision History List of Tables List of Tables SPRU938B – September 2007 Submit Documentation Feedback...
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Page 7: Preface
SPRAA84 — TMS320C64x to TMS320C64x+ CPU Migration Guide. Describes migrating from the Texas Instruments TMS320C64x digital signal processor (DSP) to the TMS320C64x+ DSP. The objective of this document is to indicate differences between the two cores. Functionality in the devices that is identical is not included. -
Page 8: Introduction
Simple packet-based transfer protocol for memory-mapped access – Write request/data packet – Read request packet – Read response data packet – Interrupt request packet Auto width negotiation VLYNQ Port User's Guide SPRU938B – September 2007 VLYNQ Port SPRU938B – September 2007 Submit Documentation Feedback... -
Page 9: Functional Block Diagram
Figure 1. VLYNQ Port Functional Block Diagram System CPU/EDMA CPU/EDMA initiated System memory Industry Standard(s) Compliance Statement VLYNQ is an interface defined by Texas Instruments and does not conform to any other industry standard. SPRU938B – September 2007 Submit Documentation Feedback VLYNQ module Slave config Interface... -
Page 10: Peripheral Architecture
2. The internal clock source is shown in Figure 2. External Clock Block Diagram VLYNQ device CLKDIR=0 VLYNQ_CLK CLKDIR=0 Figure 3. Internal Clock Block Diagram VLYNQ device CLKDIR=1 CLKDIR=1 VLYNQ_CLK www.ti.com Figure VLYNQ VLYNQ Don’t care SPRU938B – September 2007 Submit Documentation Feedback... -
Page 11: Signal Descriptions
VLYNQ relies on 8b/10b block coding to minimize the number of serial pins and allows for in-band packet delineation and control. Appendix A provides general information on 8b/10b coding definitions and their implementation within the VLYNQ module in the DM643x device. SPRU938B – September 2007 Submit Documentation Feedback Table Table 1. VLYNQ Signal Descriptions Signal Type... -
Page 12: Vlynq Functional Description
Outbound TxSM command FIFO (FIFO3) Return data FIFO (FIFO2) Return data FIFO (FIFO0) Inbound command RxSM FIFO (FIFO1) www.ti.com 8B/10B Serial Serializer encoding TxData Serial TxClk Serial RxClk 8B/10B Serial Deserializer decoding RxData SPRU938B – September 2007 Submit Documentation Feedback... -
Page 13: Write Operations
Address Outbound config bus translation commands interface Registers Master Address Inbound config bus translation commands interface SPRU938B – September 2007 Submit Documentation Feedback Figure 5. Write Operations System clock VLYNQ clock Outbound command TxSM FIFO Return data FIFO Return data... -
Page 14: Read Operations
FIFO Return data FIFO Inbound RxSM command FIFO www.ti.com Serial TxData 8B/10B Serializer encoding Local VLYNC Serial RxData 8B/10B Deserializer decoding Serial TxData 8B/10B Serializer encoding Remote VLYNQ Serial RxData 8B/10B Deserializer decoding SPRU938B – September 2007 Submit Documentation Feedback... -
Page 15: Initialization
VLYNQ. This better determines the capabilities of the connected VLYNQ device. This is software readable via the VLYNQ auto-negotiation register (AUTNGO), bit 16 (0 = Ver 1.x , 1 = Ver 2.x), after the link has been established. SPRU938B – September 2007 Submit Documentation Feedback Peripheral Architecture Appendix B for more information. -
Page 16: Address Translation
The remote map is programmed in the RX address map size register (RAMSn) and in the RX address map offset (RAMOn) in the remote device. VLYNQ Port www.ti.com SPRU938B – September 2007 Submit Documentation Feedback... -
Page 17: Example Address Memory Map
Table 2. Address Translation Example (Single Mapped Region) Register TX Address Map RX Address Map Size 1 RX Address Map Offset 1 SPRU938B – September 2007 Submit Documentation Feedback Figure 7. Example Address Memory Map VLYNQ device Map region 1... -
Page 18: Address Translation Example (Single Mapped Region)
Remote VLYNQ Module Do not care 0400 : 0000h 0000 : 0100h Do not care 0200 : 0000h Do not care 0000 : 0100h Do not care 8200 : 0000h Do not care www.ti.com SPRU938B – September 2007 Submit Documentation Feedback... -
Page 19: Flow Control
When sufficient RX FIFO resources have been made available, a flow control disable request, /C/, is transmitted to the remote device. In response, the remote device will resume transmission of data. Appendix SPRU938B – September 2007 Submit Documentation Feedback RX Address Map Size 2 Register +... -
Page 20: 2.10 Reset Considerations
VLYNQINT to pulse. If the system writes to INTSTATCLR while interrupts are still pending, a new VLQINT interrupt is generated. VLYNQ Port Section 2.13. Additionally, there is a software reset CAUTION SPRU938B – September 2007 Submit Documentation Feedback www.ti.com... -
Page 21: Interrupt Generation Mechanism Block Diagram
INTLOCAL bit in the VLYNQ control register (CTRL), this will result in a local interrupt (to the device interrupt controller) or an interrupt packet transmitted over the serial interface to the remote device. SPRU938B – September 2007 Submit Documentation Feedback Figure... -
Page 22: 2.12 Edma Event Support
The VLYNQ module uses a 16-word deep FIFO to buffer the burst writes. Since the EDMA3 controller is much faster compared to the serial VLYNQ interface, a data back-up can occur. Therefore, configuring EDMA3 for optimal transfer size, etc. is essential. VLYNQ Port Section 2.11.2. Submit Documentation Feedback www.ti.com SPRU938B – September 2007... -
Page 23: 2.13 Power Management
During debug, the CPU may be halted for single stepping, bench marking, profiling, or other debug uses using the emulator. VLYNQ does not support emulation halts/suspend operation. VLYNQ operations continue during emulation halt/suspend. SPRU938B – September 2007 Submit Documentation Feedback Peripheral Architecture... -
Page 24: Vlynq Port Registers
Section 3.2 Section 3.3 Section 3.4 Section 3.5 Section 3.6 Section 3.7 Section 3.8 Section 3.9 Section 3.10 Section 3.11 Section 3.12 Section 3.13 Section 3.14 Section 3.15 Section 3.16 Section 3.17 Section 3.18 SPRU938B – September 2007 Submit Documentation Feedback... -
Page 25: Revision Register (Revid)
31-16 Unique module ID. 15-8 REVMAJ 0-FFh Major revision. Current major revision. REVMIN 0-FFh Minor revision. Current minor revision. SPRU938B – September 2007 Submit Documentation Feedback Table Figure 9. Revision Register (REVID) R-1h VLYNQ Port Registers REVMIN R-6h VLYNQ Port... -
Page 26: Control Register (Ctrl)
Figure 10. Control Register (CTRL) RTMVALIDWR RTMENABLE R/W- 3h R/W- 0 R/W- 0 INTVEC INT2CFG Reserved R/W-0 R/W-0 www.ti.com Figure 10 TXFASTPATH Reserved CLKDIV R/W- 0 R/W- 0 AOPTDISABLE ILOOP RESET R/W- 0 R/W- 0 R/W- 0 SPRU938B – September 2007 Submit Documentation Feedback... - Page 27 You have to reprogram the VLYNQ registers if they must have a different value after a software reset. Normal operation. All internal state machines are reset, the serial interface is disabled, and the link is lost. SPRU938B – September 2007 Submit Documentation Feedback VLYNQ Port Registers VLYNQ Port...
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Page 28: Status Register (Stat)
Indicates that the internal flow control threshold has been reached (FIFO1 or FIFO2 is full) and a flow control enable request has been sent to the remote device. www.ti.com Reserved IFLOW OFLOW RERROR W1C-0 SPEND MPEND LINK SPRU938B – September 2007 Submit Documentation Feedback... - Page 29 NFEMPTY1 NFEMPTY0 SPEND MPEND LINK SPRU938B – September 2007 Submit Documentation Feedback Description Remote Error. Write a 1 to this bit to clear it. No error This bit indicates that a downstream VLYNQ module has detected a packet error. This bit is set when an error indication, /E/, is received from the serial interface.
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Page 30: Interrupt Priority Vector Status/Clear Register (Intpri)
If there is a bit set in this register and if the INTLOCAL bit in the control register (CTRL) is also set, the VLYNQ interrupt (VLQINT) is asserted. www.ti.com Table INSTAT R/W-0 SPRU938B – September 2007 Submit Documentation Feedback... -
Page 31: Interrupt Pending/Set Register (Intpendset)
Table 12. Interrupt Pointer Register (INTPTR) Field Descriptions Field Value 31-2 INTPTR 0-3FFF FFFFh Reserved SPRU938B – September 2007 Submit Documentation Feedback INTSET R/W-0 Description This field indicates the unmasked status of each pending interrupt. Writing a 0 has no effect. -
Page 32: Transmit Address Map Register (Xam)
This field is subtracted from the slave configuration bus address [25:0] to obtain the zero relative transmit packet address. This field should be programmed with a value of 0 (reset value). Reserved. Always read as 0. Writes have no effect. www.ti.com Table Reserved SPRU938B – September 2007 Submit Documentation Feedback... -
Page 33: Receive Address Map Size 1 Register (Rams1)
Table 15. Receive Address Map Offset 1 Register (RAMO1) Field Descriptions Field Value 31-2 RXADROFFSET1 0-3FFF FFFFh Reserved SPRU938B – September 2007 Submit Documentation Feedback Figure 17 and described in RXADRSIZE1 R/W-0 Description The RXADRSIZE1 field is used to determine if receive packets are destined for the first of four mapped address regions. -
Page 34: Receive Address Map Size 2 Register (Rams2)
RAMS2, the packet address is added to the contents of this register to obtain the translated address. Reserved. Always read as 0. Writes have no affect. www.ti.com Table Reserved Reserved SPRU938B – September 2007 Submit Documentation Feedback... -
Page 35: Receive Address Map Size 3 Register (Rams3)
Table 19. Receive Address Map Offset 3 Register (RAMO3) Field Descriptions Field Value 31-2 RXADROFFSET3 0-3FFF FFFFh Reserved SPRU938B – September 2007 Submit Documentation Feedback Figure 21 and described in RXADRSIZE3 R/W-0 Description The RXADRSIZE3 field is used to determine if receive packets are destined for the third of four mapped address regions. -
Page 36: Receive Address Map Size 4 Register (Rams4)
RAMS4, the packet address is added to the contents of this register to obtain the translated address. Reserved. Always read as 0. Writes have no effect. www.ti.com Table Reserved Reserved SPRU938B – September 2007 Submit Documentation Feedback... -
Page 37: Chip Version Register (Chipver)
Indicates that a link was established with a remote device that has a version 2.x VLYNQ module in it. 15-0 Reserved Reserved. Always read as 0. Writes have no effect. SPRU938B – September 2007 Submit Documentation Feedback Figure 25 and described in Figure 25. -
Page 38: Remote Configuration Registers
Remote Receive Address Map Offset 4 Register Remote Chip Version Register Remote Auto Negotiation Register Remote Manual Negotiation Register Remote Negotiation Status Register Remote Interrupt Vector 3-0 Register Remote Interrupt Vector 7-4 Register www.ti.com SPRU938B – September 2007 Submit Documentation Feedback... -
Page 39: A-1 Special 8B/10B Code Groups
VLYNQ modules at opposite ends of the serial connection. VLYNQ 2.0 and later versions do not require some of the following ordered sets. Code SPRU938B – September 2007 Submit Documentation Feedback Table A-1. Special 8b/10b Code Groups... -
Page 40: Packet Format (10-Bit Symbol Representation)
1 cmd 2 pkttype adrmask VLYNQ Protocol Specifications Figure A-1 and described in 10 bits <4*10 bits N*10 bits bytecnt address data www.ti.com Table A-3, where 0 < N < 65. 10 bits SPRU938B – September 2007 Submit Documentation Feedback... -
Page 41: Packet Format (10-Bit Symbol Representation) Description
The CMD2 bit is only included in the packet, if the packet type indicates extended command (PKTTYPE = 0110). Use configuration packet types to remotely access VLYNQ module registers. The configuration packet types do not depend on control register bit settings. SPRU938B – September 2007 Submit Documentation Feedback VLYNQ 2.0 Packet Format VLYNQ Protocol Specifications... - Page 42 1 indicates a data return channel (it is actually the return data command) and a 0 indicates a command channel, which is the command for the transaction. IIIIclaaaaddddIcldddIII1ddddII0dddddddddddddIIIIII0dddTIIIII1dTIIII VLYNQ Protocol Specifications Example A-1. This protocol can be extended to apply to multiple channels; www.ti.com SPRU938B – September 2007 Submit Documentation Feedback...
- Page 43 0 when a flow is received again for channel 0. Channel 0 then receives a flow disable, completes its packet, followed by channel 1 flow disable, where the channel 1 packet is also completed. SPRU938B – September 2007 Submit Documentation Feedback VLYNQ 2.X Packets...
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Page 44: Appendix B Write/Read Performance
VLYNQ interface running at 76.5 MHZ and 99 MHZ. Write/Read Performance No. of Pins 8b/10b encoding overhead 0.8 = 316.8 Mbps. Table B-1. The actual throughput is then calculated as the [scaling www.ti.com 4 or 396 Mbps. After the 8B10B SPRU938B – September 2007 Submit Documentation Feedback... -
Page 45: Scaling Factors
Burst Size in 32-bit words Table B-2. Expected Throughput (VLYNQ Interface Running at 76.5 MHZ and 99 MHZ) Burst Size in Number of VLYNQ Pins 32-bit Words SPRU938B – September 2007 Submit Documentation Feedback Table B-1. Scaling Factors Data Bytes Overhead Bytes Interface Running at 76.5 MHZ... -
Page 46: Relative Performance With Various Latencies
8 + 16 316.8Mbps) Burst Size in 32-bit Words Latency (μsec) www.ti.com 8 + Latency 316.8Mbps) 8 + Latency 316.8Mbps) Table B-3. Throughput Mbits/sec Mbytes/sec 277.74 34.72 179.70 22.46 43.02 5.38 5.00 0.62 SPRU938B – September 2007 Submit Documentation Feedback... -
Page 47: Appendix C Revision History
Reference Additions/Modifications/Deletions Section 2.8 Changed fourth paragraph. Added NOTE. Section 3.17 Changed paragraph. Figure 25 Changed DEVID reset value. Table 22 Changed DEVID Description. SPRU938B – September 2007 Submit Documentation Feedback Table C-1. Document Revision History Appendix C Revision History... -
Page 48: Important Notice
TI as compliant with ISO/TS 16949 requirements. Buyers acknowledge and agree that, if they use any non-designated products in automotive applications, TI will not be responsible for any failure to meet such requirements. Following are URLs where you can obtain information on other Texas Instruments products and application solutions: Products Amplifiers amplifier.ti.com...
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