Texas Instruments ADS867 Series Manual page 44

ADS8674, ADS8678
SBAS627 – JULY 2015
8.4.2.4 Power-Down Mode (PWR_DN)
The devices support a hardware and software power-down mode (PWR_DN) in which all internal circuitry is
powered down, including the internal reference and buffer. A minimum time of 15 ms is required for the device to
power up and convert the selected analog input channel after exiting PWR_DN mode, if the device is operating
in the internal reference mode (REFSEL = 0). The hardware power mode for the device is explained in the
RST/PD (Input) section. The primary difference between the hardware and software power-down modes is that
the program registers are reset to default values when the devices wake up from hardware power-down, but the
previous settings of the program registers are retained when the devices wake up from software power-down.
To enter PWR_DN mode using software, execute a valid write operation on the command register with a
software PWR_DN command of 8300h, as shown in
PWR_DN mode on the next CS rising edge following this write operation. The device remains in PWR_DN mode
if no valid conversion command (AUTO_RST or MAN_Ch_n) is executed and SDI remains low (see the
Continued Operation in the Selected Mode
operates in PWR_DN mode, the program register settings can be updated (as explained in the
Read/Write Operation section) using 16 SCLK cycles. However, if 32 complete SCLK cycles are provided, then
the device returns invalid data on the SDO line because there is no ongoing conversion in PWR_DN mode. The
program register read operation can take place normally during this mode.
Sample N
CS
SCLK 1 2
PWR_DN Command ± 8300h
SDI
SDO
Figure 98. Enter and Remain in PWR_DN Mode Timing Diagram
In order to exit from PWR_DN mode a valid 16-bit write command must be executed, as shown in
device comes out of PWR_DN mode on the next CS rising edge. For operation in internal reference mode
(REFSEL = 0), 15 ms are required for the device to power-up the reference and other internal circuits and settle
to the required accuracy before valid conversion data are output for the selected input channel.
CS
SCLK 1 2 3 4
SDI
SDO
44 Submit Documentation Feedback
section) during the subsequent data frames. When the device
CS can go high immediately after PWR_DN
command or after reading frame data.
14 15 16 17 18
X
X X
Data from Sample N
D13 D12 D1
5
6 7 8 9 10 11
AUTO_RST Command
MAN_CH_n Command
Figure 99. Exit PWR_DN Mode Timing Diagram
Product Folder Links:
Figure 98. The command is executed and the device enters
Enters PWR_DN on
CS Rising Edge
30 31 32 1
X X
X X X
D0
Device exits PWR_DN Mode, but
waits 15ms for 16-bit settling
12 13 14 15 16
Invalid
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Program Register
2 14 15 16
Stays in PWR_DN
if SDI is Low in a
Data Frame
Figure
First 16-bit accurate data
frame after recovery from
PWR_DN mode
Data
99. The