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This is the user's guide for the DAC328x EVM. The EVM includes the TRF372017 quadrature modulator
to facilitate measuring the output signals at a desired RF frequency. The TRF372017 includes an
integrated RF synthesizer used for the LO. The EVM also includes the CDCE62005 clocking source which
provides the clocks required for the DAC, the pattern generator, and the synthesizer reference of the RF
modulator. This EVM is ideally suited for mating with the TSW3100 pattern generation card for evaluating
WCDMA, LTE, or other high-performance modulation schemes.
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2.1
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3.1
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3.4
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4.1
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4.4
4.5
4.6
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EVM Block Diagram
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Two-Tone IMD Performance: LO = 2400 MHz, DAC Clk = 614.4 MHz, 2× Interpolation, IF = 20, 21
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WCDMA ACPR: LO = 1966.4 MHz, DAC Clk = 614.4 MHz, 2× Interpolation, f
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WCDMA ACPR (DAC Ch. B): DAC Clk = 614.4 MHz, 2× Int, f
SLAU304C - February 2010 - Revised November 2010
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Copyright © 2010, Texas Instruments Incorporated
SLAU304C - February 2010 - Revised November 2010
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User's Guide
DAC3282
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DAC3282
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Related Manuals for Texas Instruments DAC3282
Summary of Contents for Texas Instruments DAC3282
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Page 1: Table Of Contents
WCDMA ACPR (DAC Ch. B): DAC Clk = 614.4 MHz, 2× Int, 30-MHz Offset ..WCDMA ACPR (DAC Ch. B): DAC Clk = 614.4 MHz, 2× Int, f /4 Mixing, 30-MHz Offset; 183.6-MHz IF SLAU304C – February 2010 – Revised November 2010 DAC3282 Submit Documentation Feedback Copyright © 2010, Texas Instruments Incorporated... -
Page 2: Evm Block Diagram
2. Run Setup.exe 3. Follow the on-screen instructions 4. Once installed, launch by clicking on the DAC328x_GUI_vxpx program in Start >Texas Instruments DACs. 5. When plugging in the USB cable for the first time, you will be prompted to install the USB drivers. - Page 3 Shows the VCO output frequency from the CDC device. This frequency is changed by adjusting the appropriate register configuration in the CDC tab or by loading a different configuration file. SLAU304C – February 2010 – Revised November 2010 DAC3282 Submit Documentation Feedback Copyright © 2010, Texas Instruments Incorporated...
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Page 4: Basic Test Procedure
Basic Test Procedure www.ti.com Figure 2. DAC3282 GUI Front Panel Basic Test Procedure This section outlines the basic test procedure for testing the EVM. Test Block Diagram The test setup for general testing of the DAC328x with the TSW3100 pattern generation card is shown in... -
Page 5: Test Setup Connection
2. Enter desired offset frequency (i.e., 30 MHz) for each desired carrier 3. Select the BwDDR output button 4. Check the LOAD and Run box 5. Press the green Create button SLAU304C – February 2010 – Revised November 2010 DAC3282 Submit Documentation Feedback Copyright © 2010, Texas Instruments Incorporated... -
Page 6: Tsw3100 Multitonepattern Programming Gui
Basic Test Procedure www.ti.com Figure 4. TSW3100 MultiTonePattern Programming GUI Figure 5. TSW3100 CommsSignalPattern (WCDMA) Programming GUI DAC3282 SLAU304C – February 2010 – Revised November 2010 Submit Documentation Feedback Copyright © 2010, Texas Instruments Incorporated... -
Page 7: Dac328X Software Quick-Start Guide
DA3282 Performance Results Figure Figure 7, and Figure 8 show the typical two-tone and ACPR performance of the DAC3282 EVM from the setup in Section 3.4. This performance incorporates the DAC device and the TRF372017 modulator device. R B W... -
Page 8: Wcdma Acpr: Lo = 2120 Mhz, Dac Clk = 614.4 Mhz, 2× Interpolation, 30-Mhz Offset
Note that there are some part-to-part performance variations that can yield significantly improved two-tone IP3 or ACPR performance. The performance plots in this document show conservative typical responses. DAC3282 SLAU304C – February 2010 – Revised November 2010 Submit Documentation Feedback Copyright © 2010, Texas Instruments Incorporated... -
Page 9: Optional Configurations
- 7 6 . 7 6 d B Figure 10. WCDMA ACPR (DAC Ch. B): DAC Clk = 614.4 MHz, 2× Int, f /4 Mixing, 30-MHz Offset; 183.6-MHz IF SLAU304C – February 2010 – Revised November 2010 DAC3282 Submit Documentation Feedback Copyright © 2010, Texas Instruments Incorporated... -
Page 10: Dac Output To Filter Network And 4:1 Transformer
The main 6V is stepped down initially by two TPS7A4501 LDOs (U17 and U18). To bypass the DC/DC power supply, please modify the following: 1. Remove 0-Ω at R88, R96, and R165 DAC3282 SLAU304C – February 2010 – Revised November 2010 Submit Documentation Feedback Copyright © 2010, Texas Instruments Incorporated... -
Page 11: Revision Changes
Changed CDCE62005 (U4) LVPECL output termination network at DACCLK and FIFO_OSTR clocks. • Changed CDCE62005 (U4) LVPECL input termination network at J25 for external clock mode. SLAU304C – February 2010 – Revised November 2010 DAC3282 Submit Documentation Feedback Copyright © 2010, Texas Instruments Incorporated... - Page 12 Evaluation Board/Kit Important Notice Texas Instruments (TI) provides the enclosed product(s) under the following conditions: This evaluation board/kit is intended for use for ENGINEERING DEVELOPMENT, DEMONSTRATION, OR EVALUATION PURPOSES ONLY and is not considered by TI to be a finished end-product fit for general consumer use. Persons handling the product(s) must have electronics training and observe good engineering practice standards.
- Page 13 IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, modifications, enhancements, improvements, and other changes to its products and services at any time and to discontinue any product or service without notice. Customers should obtain the latest relevant information before placing orders and should verify that such information is current and complete.
- Page 14 Authorized Distribution Brand： Website： Welcome to visit www.ameya360.com Contact Us： Address： 401 Building No.5, JiuGe Business Center, Lane 2301, Yishan Rd Minhang District, Shanghai , China Sales： Direct +86 (21) 6401-6692 Email amall@ameya360.com 800077892 Skype ameyasales1 ameyasales2 Customer Service： Email service@ameya360.com Partnership：...
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