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Summary of Contents for Texas Instruments VLYNQ Port
- Page 1 TMS320DM644x DMSoC VLYNQ Port User's Guide Literature Number: SPRUE36A September 2007...
- Page 2 SPRUE36A – September 2007 Submit Documentation Feedback...
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Page 3: Table Of Contents
Interrupt Support 2.13 DMA Event Support 2.14 Power Management 2.15 Emulation Considerations VLYNQ Port Registers Revision Register (REVID) Control Register (CTRL) Status Register (STAT) Interrupt Priority Vector Status/Clear Register (INTPRI) Interrupt Status/Clear Register (INTSTATCLR) Interrupt Pending/Set Register (INTPENDSET) Interrupt Pointer Register (INTPTR) - Page 4 Supported Ordered Sets VLYNQ 2.0 Packet Format VLYNQ 2.X Packets Appendix B Write/Read Performance Write Performance Read Performance Appendix C Revision History Contents SPRUE36A – September 2007 Submit Documentation Feedback...
- Page 5 VLYNQ Port Functional Block Diagram External Clock Block Diagram Internal Clock Block Diagram VLYNQ Module Structure Write Operations Read Operations Example Address Memory Map Interrupt Generation Mechanism Block Diagram Revision Register (REVID) Control Register (CTRL) Status Register (STAT) Interrupt Priority Vector Status/Clear Register (INTPRI)
- Page 6 Receive Address Map Size 4 Register (RAMS4) Field Descriptions Receive Address Map Offset 4 Register (RAMO4) Field Descriptions Chip Version Register (CHIPVER) Field Descriptions Auto Negotiation Register (AUTNGO) Field Descriptions VLYNQ Port Remote Controller Registers Special 8b/10b Code Groups Supported Ordered Sets Packet Format (10-bit Symbol Representation) Description Scaling Factors Expected Throughput (VLYNQ Interface Running at 76.5 MHZ and 99 MHZ)
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Page 7: Preface
SPRAA84 — TMS320C64x to TMS320C64x+ CPU Migration Guide. Describes migrating from the Texas Instruments TMS320C64x digital signal processor (DSP) to the TMS320C64x+ DSP. The objective of this document is to indicate differences between the two cores. Functionality in the devices that is identical is not included. - Page 8 SPRAAA6 — EDMA v3.0 (EDMA3) Migration Guide for TMS320DM644x DMSoC. Describes migrating from the Texas Instruments TMS320C64x digital signal processor (DSP) enhanced direct memory access (EDMA2) to the TMS320DM644x Digital Media System-on-Chip (DMSoC) EDMA3. This document summarizes the key differences between the EDMA3 and the EDMA2 and provides guidance for migrating from EDMA2 to EDMA3.
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Page 9: Introduction
The read transactions to the remote/external device follow the same process, but the remote device's VLYNQ module serializes the read return data and transfers it to the VLYNQ port (RX pins). The read return data is finally deserialized and released to the device internal bus. -
Page 10: Functional Block Diagram
Figure 1. VLYNQ Port Functional Block Diagram ARM/EDMA CPU/EDMA initiated System memory Industry Standard(s) Compliance Statement VLYNQ is an interface defined by Texas Instruments and does not conform to any other industry standard. VLYNQ Port VLYNQ module Slave config Interface... -
Page 11: Peripheral Architecture
Submit Documentation Feedback Figure 2. The internal clock source is shown in Figure 2. External Clock Block Diagram VLYNQ device VLYNQ.CLK Figure 3. Internal Clock Block Diagram VLYNQ device VLYNQ.CLK Peripheral Architecture Figure VLYNQ CLKDIR=0 VLYNQ Don't care CLKDIR=0 VLYNQ Port... -
Page 12: Signal Descriptions
8b/10b coding definitions and their implementation within the VLYNQ module in the DM644x device. VLYNQ Port Table Table 1. VLYNQ Port Pins Description The VLYNQ reference clock supports the internally or externally generated clock. The VLYNQ serial clock run request allows remote requests for the VLYNQ serial clock to be turned off for system power management. -
Page 13: Vlynq Functional Description
System clock VLYNQ clock Outbound TxSM command FIFO (FIFO3) Return data FIFO (FIFO2) Return data FIFO (FIFO0) Inbound command RxSM FIFO (FIFO1) Peripheral Architecture 8B/10B Serial Serializer encoding TxData Serial TxClk Serial RxClk 8B/10B Serial Deserializer decoding RxData VLYNQ Port... -
Page 14: Write Operations
Slave Address Outbound config bus translation commands interface Registers Master Address Inbound config bus translation commands interface VLYNQ Port Figure 5. Write Operations System clock VLYNQ clock Outbound TxSM command FIFO Return data FIFO Return data FIFO Inbound command... -
Page 15: Read Operations
FIFO Return data FIFO Return data FIFO Inbound command RxSM FIFO Peripheral Architecture Serial TxData 8B/10B Serializer encoding Local VLYNC Serial RxData 8B/10B Deserializer decoding Serial TxData 8B/10B Serializer encoding Remote VLYNQ Serial RxData 8B/10B Deserializer decoding VLYNQ Port... -
Page 16: Initialization
(as shown in VLYNQWD For detailed information on the processor pin multiplexing and configuration register, see the pin multiplexing information in the device-specific data manual. VLYNQ Port Appendix B Table 2. Serial Interface Width VLYNQ TXD[0] , VLYNQ RXD[0]... -
Page 17: Address Translation
The remote map is programmed in the RX address map size register (RAMSn) and in the RX address map offset register (RAMOn) in the remote device. SPRUE36A – September 2007 Submit Documentation Feedback Peripheral Architecture VLYNQ Port... -
Page 18: Example Address Memory Map
Table 3. Address Translation Example (Single Mapped Region) Register TX Address Map RX Address Map Size 1 RX Address Map Offset 1 VLYNQ Port Figure 7. Example Address Memory Map DMxxx device (local) Map region 1 Map region 2 Map region 3... -
Page 19: Address Translation Example (Single Mapped Region)
DM644x VLYNQ Module Do not care 0000 : 0100h 0200 : 0000h 0000 : 0100h 8200 : 0000h Peripheral Architecture Remote VLYNQ Module 0400 : 0000h Do not care Do not care Do not care Do not care VLYNQ Port... -
Page 20: 2.10 Flow Control
When sufficient RX FIFO resources have been made available, a flow control disable request, /C/, is transmitted to the remote device. In response, the remote device will resume transmission of data. Appendix VLYNQ Port RX Address Map Size 2 Register + RX Address Map Size 3 Register)) {... -
Page 21: 2.11 Reset Considerations
If the system writes to INTSTATCLR while interrupts are still pending, a new VLQINT interrupt is generated. The VLYNQ interrupt generation mechanism is shown in SPRUE36A – September 2007 Submit Documentation Feedback CAUTION Figure Peripheral Architecture (Section 2.14). VLYNQ Port... -
Page 22: Interrupt Generation Mechanism Block Diagram
(INTPENDSET), then depending on the value of the INTLOCAL bit in the VLYNQ control (CTRL) register, this will result in a local interrupt (to the device interrupt controller) or an interrupt packet transmitted over the serial interface to the remote device. VLYNQ Port Serial interrupt packet from... -
Page 23: 2.13 Dma Event Support
The VLYNQ module uses a 16-word deep FIFO to buffer the burst writes. Since the EDMA3 controller is much faster compared to the serial VLYNQ interface, a data back-up can occur. Therefore, configuring EDMA3 for optimal transfer size, etc. is essential. SPRUE36A – September 2007 Submit Documentation Feedback Section 2.12.2. Peripheral Architecture VLYNQ Port... -
Page 24: 2.14 Power Management
During debug, the ARM CPU may be halted for single stepping, bench marking, profiling, or other debug uses using the emulator. VLYNQ does not support emulation halts/suspend operation. VLYNQ operations continue during emulation halt/suspend. VLYNQ Port www.ti.com SPRUE36A – September 2007... -
Page 25: Vlynq Port Registers
VLYNQ Remote Memory Map Table 6 lists the memory-mapped registers for the VLYNQ port controller. See the device-specific data manual for the memory address of these registers. The first 128 bytes map to the VLYNQ configuration registers that are maintained by the local (device) VLYNQ register control module while the second 128 bytes map to the remote configuration registers that are physically located in the remote device linked by the VLYNQ serial interface. -
Page 26: Revision Register (Revid)
VLYNQ Port Registers Revision Register (REVID) The revision register (REVID) contains the major and minor revisions for the VLYNQ module. The REVID is shown in Figure 9 and described in REVMAJ R-2h LEGEND: R = Read only; -n = value after reset Table 7. -
Page 27: Control Register (Ctrl)
Submit Documentation Feedback Figure 10. Control Register (CTRL) RTMVALIDWR RTMENABLE R/W- 3h R/W- 0 R/W- 0 INTVEC INT2CFG Reserved R/W-0 R/W-0 VLYNQ Port Registers Figure 10 TXFASTPATH Reserved CLKDIV R/W- 0 R/W- 0 AOPTDISABLE ILOOP RESET R/W- 0 R/W- 0... - Page 28 VLYNQ Port Registers Table 8. Control Register (CTRL) Field Descriptions (continued) Field Value Description INT2CFG Interrupt to configuration register. Determines which register is written with the status contained in interrupt packets that are received over the serial interface. Always write 1 to this bit and configure the interrupt pointer register to point to the interrupt pending/set register.
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Page 29: Status Register (Stat)
Indicates that the internal flow control threshold is not yet reached. Indicates that the internal flow control threshold has been reached (FIFO1 or FIFO2 is full) and a flow control enable request has been sent to the remote device. VLYNQ Port Registers Reserved IFLOW... - Page 30 VLYNQ Port Registers Table 9. Status Register (STAT) Field Descriptions (continued) Field Value RERROR LERROR NFEMPTY3 NFEMPTY2 NFEMPTY1 NFEMPTY0 SPEND MPEND LINK VLYNQ Port Description Remote Error. Write a 1 to this bit to clear it. No error This bit indicates that a downstream VLYNQ module has detected a packet error. This bit is set when an error indication, /E/, is received from the serial interface.
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Page 31: Interrupt Priority Vector Status/Clear Register (Intpri)
This field indicates the unmasked status of each interrupt. Writing a 1 to any set bit in this field clears the corresponding interrupt. If there is a bit set in this register and if the INTLOCAL bit in the control register (CTRL) is also set, the VLYNQ interrupt (VLQINT) is asserted. VLYNQ Port Registers Table INSTAT... -
Page 32: Interrupt Pending/Set Register (Intpendset)
VLYNQ Port Registers Interrupt Pending/Set Register (INTPENDSET) The interrupt pending/set register (INTPENDSET) indicates the pending interrupt status when the INTLOCAL bit in the control register (CTRL) is not set. When the interrupt packet is forwarded on the serial interface, these bits are cleared. The INTPENDSET is shown in Table Figure 14. -
Page 33: Transmit Address Map Register (Xam)
This field is subtracted from the slave configuration bus address [25:0] to obtain the zero relative transmit packet address. This field should be programmed with a value of 0 (reset value). Reserved. Always read as 0. Writes have no effect. VLYNQ Port Registers Table Reserved VLYNQ Port... -
Page 34: Receive Address Map Size 1 Register (Rams1)
VLYNQ Port Registers Receive Address Map Size 1 Register (RAMS1) The receive address map size 1 register (RAMS1) is used to identify the intended destination of inbound serial packets. The RAMS1 is shown in Figure 17. Receive Address Map Size 1 Register (RAMS1) LEGEND: R/W = Read/Write;... -
Page 35: Receive Address Map Size 2 Register (Rams2)
If the received packet address is less than the value in RAMS2, the packet address is added to the contents of this register to obtain the translated address. Reserved. Always read as 0. Writes have no affect. VLYNQ Port Registers Table Reserved Reserved... -
Page 36: Receive Address Map Size 3 Register (Rams3)
VLYNQ Port Registers 3.13 Receive Address Map Size 3 Register (RAMS3) The receive address map size 3 register (RAMS3) is used to identify the intended destination of inbound serial packets. The RAMS3 is shown in Figure 21. Receive Address Map Size 3 Register (RAMS3) LEGEND: R/W = Read/Write;... -
Page 37: Receive Address Map Size 4 Register (Rams4)
If the receive packet address is less than the value in RAMS4, the packet address is added to the contents of this register to obtain the translated address. Reserved. Always read as 0. Writes have no effect. VLYNQ Port Registers Table Reserved Reserved... -
Page 38: Chip Version Register (Chipver)
VLYNQ Port Registers 3.17 Chip Version Register (CHIPVER) VLYNQ allows inter-connection of many VLYNQ devices. In order for software to control the device functions, there must be a mechanism that allows the software to identify VLYNQ devices. Each device that has a VLYNQ module in it has a unique device ID associated with it, which is software readable via a memory-mapped register within the VLYNQ module called the chip version register (CHIPVER). -
Page 39: Remote Configuration Registers
Refer to the remote device data sheet for a precise description of the VLYNQ registers that exist in the remote device. Table 25. VLYNQ Port Remote Controller Registers Offset Acronym... -
Page 40: Sprue36A – September
Appendix A Appendix A VLYNQ Protocol Specifications VLYNQ relies on 8b/10b block coding to minimize the number of serial pins and allow for in-band packet delineation and control. The following sections include general 8b/10b coding definitions and their implementation. Special 8b/10b Code Groups Code Group Name Octet Value K28.0... -
Page 41: Packet Format (10-Bit Symbol Representation)
www.ti.com A.2.1 Idle (/I/) The idle ordered sets are transmitted continuously and repetitively whenever the serial interface is idle. Idle is also used in the place of the flowed code in VLYNQ versions 2.0 and later. A.2.2 End of Packet (/T/) An end of packet delimiter delineates the ending boundary of a packet. -
Page 42: Packet Format (10-Bit Symbol Representation) Description
VLYNQ 2.0 Packet Format Table A-3. Packet Format (10-bit Symbol Representation) Description Field Value Description PKTTYPE[3:0] This field indicates the packet type. 0000 Reserved 0001 Write with address increment. 0010 Reserved 0011 Write 32-bit word with address increment. 0100 Reserved 0101 Configuration write with address increment. - Page 43 www.ti.com VLYNQ 2.X Packets An example of what can happen to a write burst due to remote and local FIFO state changes and the link pulse timer expiring is shown in therefore, the data return channel is logically isolated from the command channel. Example A-1.
- Page 44 VLYNQ 2.X Packets A command, length, address, and start receive data from the idle stream. A flow enable was received for the command channel, but there is data to return, so the flow is followed by a channel 1 descriptor (the command for return data actually indicates a channel 1), and the channel 1 packet is now under way.
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Page 45: Appendix B Write/Read Performance
www.ti.com Appendix B Write/Read Performance The following sections discuss the write versus read performance and how the throughput (read or write) should be calculated for a given data width and serial clock frequency. Note: The data and throughput calculations shown here are sample calculations for most ideal situations. -
Page 46: Scaling Factors
Write Performance Burst Size in 32-bit words Table B-2. Expected Throughput (VLYNQ Interface Running at 76.5 MHZ and 99 MHZ) Burst Size in Number of VLYNQ Pins 32-bit Words Write/Read Performance Table B-1. Scaling Factors Data Bytes Overhead Bytes Interface Running at 76.5 MHZ Mbits/sec Mbytes/sec 24.19... -
Page 47: Relative Performance With Various Latencies
www.ti.com Read Performance Since reads must complete a transmit-remote read-receive cycle before starting another read transaction, the data throughput is lower as compared to writes. There is latency involved in reading the data from the remote device; and in some cases, a local latency in writing the returned data before the next read can start. -
Page 48: Appendix C Revision History
Appendix C Appendix C Revision History Table C-1 lists the changes made since the previous version of this document. Reference Additions/Modifications/Deletions Section 2.9 Changed fourth paragraph. Added NOTE. Table 8 Changed Description of INTLOCAL. Section 3.17 Changed paragraph. Figure 25 Changed DEVID reset value. -
Page 49: Important Notice
TI as compliant with ISO/TS 16949 requirements. Buyers acknowledge and agree that, if they use any non-designated products in automotive applications, TI will not be responsible for any failure to meet such requirements. Following are URLs where you can obtain information on other Texas Instruments products and application solutions: Products Amplifiers amplifier.ti.com...
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