Texas Instruments ADS867 Series Manual page 25

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Figure 69 shows the voltage versus current response of the internal overvoltage protection circuit when the
device is powered on. According to this current-to-voltage (I-V) response, the current flowing into the device input
pins is limited by the 1-MΩ input impedance. However, for voltages beyond ±20 V, the internal node voltages
surpass the break-down voltage for internal transistors, thus setting the limit for overvoltage protection on the
input pins.
The same overvoltage protection circuit also provides protection to the device when the device is not powered on
and AVDD is floating with an impedance > 30 kΩ. This condition can arise when the input signals are applied
before the ADC is fully powered on. The overvoltage protection limits for this condition are shown in
Table 2. Input Overvoltage Protection Limits When AVDD = Floating with Impedance > 30 kΩ
INPUT CONDITION
(V = ±11 V)
OVP
|V | < |V | Within overvoltage range
IN OVP
|V | > |V | Beyond overvoltage range
IN OVP
(1) AVDD = floating, GND = 0, AIN_nGND = 0 V, |V
break-down voltage for the internal OVP circuit. Assume that R
Figure 70 shows the voltage versus current response of the internal overvoltage protection circuit when the
device is not powered on. According to this I-V response, the current flowing into the device input pins is limited
by the 1-MΩ input impedance. However, for voltages beyond ±11 V, the internal node voltages surpass the
break-down voltage for internal transistors, thus setting the limit for overvoltage protection on the input pins.
30
---- ± 2.5*V ---- “ 1.25*V
REF,
---- “ 0.625*V ------“0.3125*V
REF,
-------“0.156 V
18
REF,
---- + 1.25*V ---- + 0.625*V
REF,
---- + 0.3125*V
REF
6
±6
±18
±30
±30 ±20 ±10
Figure 69. I-V Curve for an Input OVP Circuit
Copyright © 2015, Texas Instruments Incorporated
TEST
CONDITION
All input ranges
All input ranges
| is the maximum input voltage for any selected input range, and |V
RANGE
REF
REF
---- + 2.5*V
REF
REF
0 10 20
Input Voltage (V)
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ADC OUTPUT
Device is not functional but is protected internally by
Invalid
the OVP circuit.
This usage condition may cause irreversible damage
Invalid
to the device.
is approximately 0.
S
20
12
4
±4
±12
±20
30
±20 ±12
C003
Figure 70. I-V Curve for an Input OVP Circuit
ADS8674 ADS8678
ADS8674, ADS8678
SBAS627 – JULY 2015
Table
COMMENTS
| is the
OVP
4 12
±4
Input Voltage (V)
(AVDD = Floating)
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2.
(1)
20
C004
25