Texas Instruments ADS867 Series Manual page 42

ADS8674, ADS8678
SBAS627 – JULY 2015
8.4.2.2 Frame Abort Condition (FRAME_ABORT)
As explained in the Data Acquisition Example
frame starts with a falling edge of the CS signal. During the first 16 SCLK cycles, the device reads the 16-bit
command word on the SDI line. The device waits to execute the command until the last bit of the command is
received, which is latched on the 16th SCLK falling edge. During this operation, the CS signal must stay low. If
the CS signal goes high for any reason before the data transmission is complete, the device goes into an
INVALID state and waits for a proper command to be written. This condition is called the FRAME_ABORT
condition. When the device is operating in this INVALID mode, any read operation on the device returns invalid
data on the SDO line. The output of the ALARM pin will continue to reflect the status of input signal on the
previously selected channel.
8.4.2.3 STANDBY Mode (STDBY)
The devices support a low-power standby mode (STDBY) in which only part of the circuit is powered down. The
internal reference and buffer is not powered down, and therefore, the devices can be quickly powered up in 20
µs on exiting the STDBY mode. When the device comes out of STDBY mode, the program registers are not
reset to the default values.
To enter STDBY mode, execute a valid write operation to the command register with a STDBY command of
8200h, as shown in Figure
rising edge following this write operation. The device remains in STDBY mode if no valid conversion command
(AUTO_RST or MAN_Ch_n) is executed and SDI remains low (see the
Mode section) during the subsequent data frames. When the device operates in STDBY mode, the program
register settings can be updated (as explained in the
SCLK cycles. However, if 32 complete SCLK cycles are provided, then the device returns invalid data on the
SDO line because there is no ongoing conversion in STDBY mode. The program register read operation can
take place normally during this mode.
Sample N
CS
SCLK 1 2
STDBY Command ± 8200h
SDI
SDO
Figure 96. Enter and Remain in STDBY Mode Timing Diagram
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section, the device digital interface is designed such that each data
96. The command is executed and the device enters STDBY mode on the next CS
CS can go high immediately after Standby
command or after reading frame data.
14 15 16 17 18
X
X X
Data from Sample N
D11
D13 D1
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Continued Operation in the Selected
Program Register Read/Write Operation
Enters STDBY on
CS Rising Edge
30 31 32 1
X X
X X X
D0
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section) using 16
2 14 15 16
Stays in STDBY
if SDI is Low in a
Data Frame