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ADLINK Technology NuDAQ / NuIPC LPCI-7200S User Manual

12mb/s high speed digital input/ output card
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PCI-7200 / cPCI-7200 / LPCI-7200S
12MB/S High Speed
Digital Input/ Output Card
User's Guide
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Summary of Contents for ADLINK Technology NuDAQ / NuIPC LPCI-7200S

  • Page 1 ® ® NuDAQ / NuIPC PCI-7200 / cPCI-7200 / LPCI-7200S 12MB/S High Speed Digital Input/ Output Card User’s Guide Recycled Paper...
  • Page 3 ©Copyright 2003 ADLINK Technology Inc. All Rights Reserved. Manual Rev. 2.30: October 13, 2003 Part No: 50-11102-101 The information in this document is subject to change without prior notice in order to improve reliability, design, and function and does not represent a commitment on the part of the manufacturer.
  • Page 4 Getting Service from ADLINK Customer Satisfaction is top priority for ADLINK TECHNOLOGY INC. If you need any help or service, please contact us. Web Site http://www.adlinktech.com Sales & Service Service@adlinktech.com +886-2-82265877 Address 9F, No. 166, Jian Yi Road, Chungho City, Taipei, 235 Taiwan Please email or FAX your detailed information for prompt, satisfactory, and consistent service.

  • Page 5: Table Of Contents

    Table of Contents Chapter 1 Introduction ... 1 Applications... 1 Features ... 2 Specifications ... 2 Software Supporting... 4 1.4.1 Programming Library ... 4 1.4.2 PCIS-LVIEW: LabVIEW 1.4.3 PCIS-VEE: HP-VEE Driver ... 5 1.4.4 DAQBench 1.4.5 DASYLab 1.4.6 PCIS-DDE: DDE Server and InTouch 1.4.7 PCIS-ISG: ISaGRAF 1.4.8...
  • Page 6 External Clock Mode ... 31 Handshaking ... 31 Timing Characteristic ... 33 Chapter 5 C/C++ Libraries ... 37 Libraries Installation ... 37 Programming Guide ... 38 5.2.1 Naming Convention ... 38 5.2.2 Data Types ... 38 _7200_Initial ... 39 _7200_Switch_Card_No ... 40 _7200_AUX_DI ...

  • Page 7: How To Use This Guide

    How to Use This Guide This manual is designed to help users use the PCI-7200, cPCI-7200, and LPCI-7200S. The functionality of PCI-7200, cPCI-7200, and LPCI-7200S are the same except that the cPCI-7200 has 4 auxiliary digital inputs and outputs. In this guide, “PCI-7200” represents PCI-7200, cPCI-7200, and LPCI-7200S if not specified.

  • Page 9: Chapter 1 Introduction

    Introduction The PCI-7200, cPCI-7200, and LPCI-7200S are PCI/CompactPCI/Low profile PCI form factor high-speed digital I/O cards, consisting of 32 digital input channels, and 32 digital output channels. High performance design and state-of-the-art technology make this card suitable for high-speed digital input and output applications.

  • Page 10: Features

    1.2 Features The PCI-7200 high-speed DIO Card provides the following advanced features: 32 TTL digital input channels 32 TTL digital output channels Transfer up to 12M Bytes per second High output driving and low input loading 32-bit PCI bus, Plug and Play On-board internal timer pacer clock Internal timer controls input sampling rate Internal timer controls digital output rate...
  • Page 11 Input Voltage: Low: Min. 0V; Max. 0.8V High: Min. +2.0V Input Load: Low: +0.5V @ -0.6mA max. High: +2.7V @ +20µA max. Output Voltage: Low: Min. 0V; Max. 0.5V High: Min. +2.7V Driving Capacity: Low: Max. +0.5V at 24mA (Sink) High: Min.

  • Page 12: Software Supporting

    1.4 Software Supporting ADLINK provides versatile software drivers and packages for users’ different approach to building a system. We not only provide programming library for many Windows systems, but also provide drivers for many software packages ® including LabVIEW ISaGRAF , etc.

  • Page 13: Pcis-Lview: Labview Driver

    1.4.2 PCIS-LVIEW: LabVIEW PCIS-LVIEW contains VIs to interface with NI’s LabVIEW PCIS-LVIEW supports Windows 95/98/NT/2000. The LabVIEW shipped free with the board. Users can install and use them without a license. For detailed information about PCIS-LVIEW, please refer to the user’s guide on the CD.

  • Page 14: Pcis-Isg: Isagraf

    1.4.7 PCIS-ISG: ISaGRAF The ISaGRAF WorkBench is an IEC1131-3 SoftPLC control program development environment. The PCIS-ISG includes ADLINK products’ target drivers for ISaGRAF under the Windows NT environment. The PCIS-ISG is included on the ADLINK CD. It requires a license. 1.4.8 PCIS-ICL: InControl PCIS-ICL is the InControl driver, which support the Windows NT.

  • Page 15: Chapter 2 Installation

    Installation This chapter describes how to install the PCI-7200. Package contents and unpacking information are described. Because the PCI-7200 is a Plug and Play device, there are no more jumper or DIP switch settings for configuration. The interrupt number and I/O port address are assigned by the system BIOS during system boot up.

  • Page 16: Unpacking

    2.2 Unpacking The PCI-7200 card contains sensitive electronic components that can be easily damaged by static electricity. The work area should have a grounded anti-static mat. The operator should be wearing an anti-static wristband, grounded at the same point as the anti-static mat.

  • Page 17: Pci-7200/Cpci-7200/Lpci-7200S's Layout

    2.4 PCI-7200/cPCI-7200/LPCI-7200S’s Layout Figure 2.1(a) PCI-7200 Layout Diagram Installation • 9...
  • Page 18 Figure 2.1(b) cPCI-7200 Layout Diagram 10 • Installation...
  • Page 19 CN1A CN1B Figure 2.1(c) LPCI-7200S Layout Diagram Installation • 11...
  • Page 20 Figure 2.1(d) LPCI-7200S with standard PCI bracket Layout Diagram 12 • Installation...

  • Page 21: Hardware Installation Outline

    2.5 Hardware Installation Outline Hardware configuration These PCI cards (or CompactPCI, Low Profile PCI cards) are equipped with a Plug and Play PCI controller that requests base addresses and interrupts according to PCI standard. The system BIOS will install the system resource based on the PCI cards’...

  • Page 22: Connector Pin Assignments

    2.6 Connector Pin Assignments 2.6.1 PCI-7200 Pin Assignments The PCI-7200 comes equipped with one 37-pin D-Sub connector (CN2) located on the rear mounting plate and one 40-pin female flat cable header connector (CN1). The CN2 is located on the rear mounting plate; the CN1 is on front of the board.
  • Page 23 DI 0 DI 1 DI 2 DI 3 DI 4 DI 5 DI 6 DI 7 DI 8 DI 9 DI10 DI11 DI12 DI13 DI14 DI15 I_ACK I_REQ Figure 2.3 CN2 Pin Assignments DO10 DO11 DO12 DO13 DO14 DO15 I_TRG Installation •...

  • Page 24: Cpci-7200 Pin Assignments

    2.6.2 cPCI-7200 Pin Assignments (1) DO0 (51) (52) (2) DO2 (53) (3) DO4 (4) DO6 (5) DO8 (6) DO10 (7) DO12 (8) DO14 (9) GND (10) DO16 (11) DO18 (12) DO20 (13) DO22 (14) DO24 (15) DO26 (16) DO28 (17) DO30 (18) GND (19) +5Vout (20) +5Vout...

  • Page 25: Lpci-7200S Pin Assignments

    2.6.3 LPCI-7200S Pin Assignments Figure 2.5 CN1A Pin Assignments DIN0 A1 A35 GND DIN1 A2 A36 GND DIN2 A3 A37 GND DIN3 A4 A38 GND DIN4 A5 A39 GND DIN5 A6 A40 GND DIN6 A7 A41 GND DIN7 A8 A42 GND DIN8 A9 A43 GND DIN9 A10 A44 GND...
  • Page 26 Figure 2.6 CN1B Pin Assignments 18 • Installation DOUT0 B1 B35 GND DOUT1 B2 B36 GND DOUT2 B3 B37 GND DOUT3 B4 B38 GND DOUT4 B5 B39 GND DOUT5 B6 B40 GND DOUT6 B7 B41 GND DOUT7 B8 B42 GND DOUT8 B9 B43 GND DOUT9 B10 B44 GND...

  • Page 27: 8254 For Timer Pacer Generation

    2.7 8254 for Timer Pacer Generation “H” “H” 4MHz Clock “H” The internal timer/counter 8254 on the PCI-7200 is configured as the above diagram (Figure 2.7). Users can use it to generate the timer pacer for both digital input and digital output triggers. The digital input timer pacer is from OUT0 (Timer 0), and the digital output timer pacer is from OUT1 (Timer 1).

  • Page 28: Lpci-7200S Pci Bus Signaling

    2.8 LPCI-7200S PCI Bus Signaling Low-Profile PCI is a new PCI card standard for space-constrained system designs. The new form factor maintain the same electrical protocols, PCI signals, and software drivers as standard PCI v2.2 expansion cards. However, Low-Profile PCI bus interface only supports 3.3V signaling. To support both 5V and 3.3V signaling, LPCI-7200S implements 5V I/O tolerant bus switches to achieve the I/O voltage transition.

  • Page 29: Chapter 3 Register Format

    Register Format 3.1 I/O Registers Format The PCI-7200 occupies 8 consecutive 32-bit I/O addresses in the PC I/O address space. The cPCI-7200 occupies 9 consecutive 32-bit I/O addresses. Table 4.1 shows the I/O Map Address Base + 0 Base + 4 Base + 8 Base + C Base + 10...

  • Page 30: Digital Input Register (Base + 10)

    3.2 Digital Input Register (BASE + 10) 32 digital input channels can be read from this register Address: BASE + 10 Attribute: READ Only Data Format: Byte Base +10 Base +11 DI15 Base +12 DI23 Base +13 DI31 3.3 Digital Output Register (BASE + 14) 32 digital output channels can be written and read to/from this register Address: BASE + 14 Attribute: READ/WRITE...
  • Page 31 Digital Input Mode Setting: I_ACK: Input ACK Enable 1: Input ACK is enabled (input ACK will be asserted after input data is read by CPU or written to input FIFO) 0: Input ACK is disabled I_REQ: Input REQ Strobe Enabled 1: Use I_REQ edge to latch input data 0: I_REQ is disabled I_TIME0: Input Timer 0 Enable...

  • Page 32: Interrupt Status & Control Register (Base + 1C)

    O_TRG: Digital Output Trigger Signal This bit is used to control the O_TRG output of PCI-7200; the signal is on CN1 pin 36 of PCI-7200, CN1 pin 26 of cPCI-7200, CN2 pin 34 of LPCI 7200S when 1: O_TRG 1 goes High (1) 0: O_TRG 1 goes Low (0) Digital I/O FIFO Status: I_OVR: Input data overrun...
  • Page 33 T0_EN: Interrupt is triggered by timer 0 output. 1: Timer 0 interrupt is enabled 0: Timer 0 interrupt is disabled T1_EN: Interrupt is triggered by timer 1 output. 1: Timer 1 interrupt is enabled 0: Timer 1 interrupt is disabled T2_EN: Interrupt is triggered by timer 2 output.
  • Page 34 T1_T2: Timer 1 is cascaded with timer 2 1: Timer 1 and timer 2 are cascaded together; output of timer 2 connects to the clock input of timer 1. 0: Not cascaded, the 4MHz clock is connected to the timer 1 clock input.

  • Page 35: 8254 Timer Registers (Base + 0)

    3.6 8254 Timer Registers (BASE + 0) The 8254 timer/counter IC occupies 4 I/O address. Users can refer to Tundra's or Intel's data sheet for a full description of the 8254 features. Download the 8254 data sheet from the following web site: http://support.intel.com/support/controllers/peripheral/231164.htm or...

  • Page 37: Chapter 4 Operation Theory

    Operation Theory In PCI-7200, there are four data transfer modes can be used for digital I/O access and control, these modes are: 1. Direct Program Control: the digital inputs and outputs can be read/written and controlled by its corresponding I/O port address directly. 2.

  • Page 38: Timer Pacer Mode

    4.2 Timer Pacer Mode The digital I/O access control is clocked by timer pacer, which is generated by an interval programming timer/counter chip (8254). There are three timers on the 8254. Timer 0 is used to generate timer pacer for digital input and timer 1 is used for digital output.

  • Page 39: External Clock Mode

    4.3 External Clock Mode The digital input is clocked by external strobe, which is from Pin 19 (I_REQ) of CN2 (PCI-7200), Pin 24 of CN1 (cPCI-7200), or PIN 33 of CN1A (LPCI-7200S). The operation sequence is very similar to the Timer Pacer Trigger. The only difference is the clock source.
  • Page 40 IN_REQ IN_ACK PC's Main Memory O_REQ & O_ACK for Digital Output 1. Digital Output Data is moved from PC memory to FIFO of PCI-7200 by using DMA data mastering data transfer. 2. Move output data from FIFO to digital output circuit. 3.

  • Page 41: Timing Characteristic

    4.5 Timing Characteristic 1. I_REQ as input data strobe (Rising Edge Active) IN_ I_REQ D10~DI31 ≥ 60ns ≥ 2ns 2. I_REQ as input data strobe (Falling Edge Active) IN_R I_REQ D10~DI31 ≥ 60ns ≥ 2ns valid data ≥ 60ns ≥ 5 PCI CLK Cycle ≥...
  • Page 42 3. I_REQ & I_ACK Handshaking IN I_REQ IN I_ACK D10~DI31 ≥ 0ns ≥ 0ns Note: I_REQ must be asserted until I_ACK asserts, I_ACK will be asserted until I_REQ de-asserts. 4. O_REQ as output data strobe Out O_REQ D00~D031 ≥ 19ns 34 •...
  • Page 43 5. O_REQ & O_ACK Handshaking OUT_REQ O_REQ OUT_ACK O_ACK DO0~Do31 19ns Note: O_ACK must be de-asserted before O_REQ asserts, O_ACK can be asserted any time after O_REQ asserts, O_REQ will be reasserted after O_ACK is asserted. valid data 1 PCI CLK Cycle valid data 5 PCI CLK Cycle Operation Theory •...

  • Page 45: Chapter 5 C/C++ Libraries

    C/C++ Libraries This chapter describes the software library for operating the card. Only functions in DOS library and Windows 95 DLL are described. Please refer to the PCIS-DASK function reference manual, which included on the ADLINK CD, for the descriptions of the Windows 98/NT/2000 DLL functions. The function prototypes and some useful constants are defined in the header files LIB directory (DOS) and INCLUDE directory (Windows 95).

  • Page 46: Programming Guide

    5.2 Programming Guide 5.2.1 Naming Convention The functions of the NuDAQ PCI cards or NuIPC CompactPCI cards’ software drivers use full-names to represent the functions' real meaning. The naming convention rules are: In DOS: _{hardware_model}_{action_name}. e.g. _7200_Initial() . All functions in the PCI-7200 driver are named with 7200 as {hardware_model}. But they can be used by PCI-7200, cPCI-7200 and LPCI-7200S.

  • Page 47: 7200_Initial

    5.3 _7200_Initial @ Description A PCI-7200 card is initialized according to the card number. Because the PCI-7200 is PCI bus architecture and meets the Plug and Play design, the IRQ and base_address (pass-through address) are assigned by system BIOS directly. Every PCI-7200 card has to be initialized by this function before calling other functions.

  • Page 48: 7200_Switch_Card_No

    5.4 _7200_Switch_Card_No @ Description After initializing more than one PCI-7200 card, this function is used to select which card is currently used. @ Syntax Visual C++ (Windows 95) int W_7200_Switch_Card_No (U8 card_number) Visual Basic (Windows 95) W_7200_Switch_Card_No (ByVal card_number As Byte) As Long C/C++ (DOS) int _7200_Switch_Card_No (U8 card_number)

  • Page 49: 7200_Aux_Di_Channel

    5.6 _7200_AUX_DI_Channel @ Description Read data from the auxiliary digital input channel of cPCI-7200 card. There are 4 digital input channels on the cPCI-7200 auxiliary digital input port. When performing this function, the auxiliary digital input port is read and the value of the corresponding channel is returned.

  • Page 50: 7200_Aux_Do_Channel

    5.8 _7200_AUX_DO_Channel @ Description Write data to auxiliary digital output channel (bit). There are 4 auxiliary digital output channels on the cPCI-7200. When performing this function, the digital output data is written to the corresponding channel. * channel means each bit of digital input port @ Syntax Visual C++ (Windows 95) int W_7200_AUX_DO_Channel (U8 do_ch_no, Boolean aux_data)

  • Page 51: 7200_Di_Channel

    5.10 _7200_DI_Channel @ Description This function is used to read data from digital input channels (bit). There are 32 digital input channels on the PCI-7200. When performs this function, the digital input port is read and the value of the corresponding channel is returned.

  • Page 52: 7200_Do_Channel

    5.12 _7200_DO_Channel @ Description This function is used to write data to digital output channels (bit). There are 32 digital output channels on the PCI-7200. When performing this function, the digital output data is written to the corresponding channel. * channel means each bit of digital input port @ Syntax Visual C++ (Windows 95) int W_7200_DO_Channel (U8 do_ch_no, Boolean do_data)

  • Page 53: 7200_Alloc_Dma_Mem

    5.13 _7200_Alloc_DMA_Mem @ Description Contact Windows 95/98 system to allocate a block of contiguous memory for single-buffered DMA transfer. This function is only available in Windows 95/98. @ Syntax Visual C++ (Windows 95) int W_7200_Alloc_DMA_Mem (U32 *buff, U32 *handle, U32 buf_size, U32 *actual_size) Visual Basic (Windows 95) W_7200_Alloc_DMA_Mem (buff As Long, handle As Long, ByVal...

  • Page 54: 7200_Free_Dma_Mem

    5.14 _7200_Free_DMA_Mem @ Description Releases system DMA memory. This function is only available in Windows 95/98. @ Syntax Visual C++ (Windows 95) int W_7200_Free_DMA_Mem (U32 handle) Visual Basic (Windows 95) W_7200_Free_DMA_Mem (ByVal handle As Long ) As Long @ Argument handle: The handle of system DMA memory to release.

  • Page 55: 7200_Free_Dbdma_Mem

    denotes the actual size of allocated memory for each half of circular buffer. @ Return Code ERR_NoError ERR_SmallerDMAMemAllocated 5.16 _7200_Free_DBDMA_Mem @ Description Releases a system’s circular buffer DMA memory. This function is only available in Windows 95/98. For double-buffered transfer principle, please refer to Section 6 “Double Buffered Mode Principle”.
  • Page 56 Bus Mastering DMA mode of the PCI-7200: PCI bus mastering offers the highest possible speed available on the PCI-7200. When the function _7200_DI_DMA_Start is executed, it will enable PCI bus master operation. This is conceptually similar to DMA (Direct Memory Access) transfers in a PC but it is really PCI bus mastering.
  • Page 57 @ Syntax Visual C++ (Windows 95) int W_7200_DI_DMA_Start (U8 mode, U32 count, U32 handle, Boolean wait_trg, U8 trg_pol, Boolean clear_fifo, Boolean disable_di) Visual Basic (Windows 95) W_7200_DI_DMA_Start (ByVal mode As Byte, ByVal count As Long, ByVal handle As Long, ByVal wait_trg as Byte, ByVal trg_pol As Byte, ByVal clear_fifo As Byte, ByVal disable_di As Byte) As Long C/C++ (DOS)

  • Page 58: 7200_Di_Dma_Status

    clear_fifo: 0: retain the FIFO data 1: clear FIFO data before perform digital input disable_di: 0: digital input operation still active after DMA transfer complete 1: disable digital input operation immediately when DMA transfer complete @ Return Code ERR_NoError ERR_BoardNoInit ERR_InvalidDIOMode ERR_InvalidDIOCnt ERR_NotDWordAlign...

  • Page 59: 7200_Di_Dma_Stop

    5.19 _7200_DI_DMA_Stop @ Description This function is used to stop the DMA data transferring. After executing this function, the _7200_DI_DMA_Start function is stopped. The function returns the number of the data which has been transferred, no matter if the digital input DMA data transfer is stopped by this function or by the DMA terminal count, ISR.

  • Page 60: 7200_Checkhalfready

    5.21 _7200_CheckHalfReady @ Description When you use _7200_DI_DMA_Start to sample digital input data and double buffer _7200_CheckHalfReady to check data ready (data half full) or not in the circular buffer, and using _7200_DblBufferTransfer to get data. @ Syntax Visual C++ (Windows 95) int W_7200_CheckHalfReady (Boolean * halfReady) Visual Basic (Windows 95) W_7200_CheckHalfReady (halfReady As Byte) As Long...

  • Page 61: 7200_Getoverrunstatus

    5.23 _7200_GetOverrunStatus @ Description When using _7200_DI_DMA_Start to convert Digital I/O data with double buffer mode enabled, and not using _7200_DblBufferTransfer to move converted data then double buffer overrun will occur. Use this function to check overrun count. @ Syntax Visual C++ (Windows 95) int W_7200_GetOverrunStatus (U32 * overrunCount) Visual Basic (Windows 95)

  • Page 62: 7200_Do_Dma_Status

    C/C++ (DOS) int _7200_DO_DMA_Start (U8 mode, U32 count, U32 *do_buffer, Boolean repeat) @ Argument mode: Digital output trigger modes DO_MODE_0: Internal timer pacer (TIME 1) DO_MODE_1: Internal timer pacer with O_REQ enable DO_MODE_2: O_REQ & I_REQ handshaking count: the sample number of digital output data (in samples, not in bytes) handle (Win 95): the handle of system DMA memory.

  • Page 63: 7200_Do_Dma_Stop

    C/C++ (DOS) int _7200_DO_DMA_Status (U8 *status , U32 *count) @ Argument status: status of the DMA data transfer. 0: DO_DMA_STOP: DMA is completed 1: DO_DMA_RUN: DMA is not completed count: the amount of DO data which has been transferred. @ Return Code ERR_NoError 5.26 _7200_DO_DMA_Stop @ Description...

  • Page 64: 7200_Di_Timer

    5.27 _7200_DI_Timer @ Description This function is used to set the internal timer pacer for digital input. There are two configurations for the internal timer pacer: 1. Non-cascaded (One COUNTER 0 only) 4MHz Input Timer pacer frequency = 4Mhz / C0 2.

  • Page 65: 7200_Do_Timer

    mode: TIMER_NONCASCADE or TIMER_CASCADE @ Return Code ERR_NoError ERR_InvalidBoardNumber ERR_InvalidTimerMode ERR_BoardNoInit 5.28 _7200_DO_Timer @ Description This function is used to set the internal timer pacer for digital output. There are two configurations for the internal timer pacer: 1. Non-cascaded (One COUNTER 0 only) 4MHz Input Timer pacer frequency = 4Mhz / C1 2.
  • Page 66 @ Syntax Visual C++ (Windows 95) int W_7200_DO_Timer (U16 c1, U16 c2, Booelan mode) Visual Basic (Windows 95) W_7200_DO_Timer (ByVal c1 As Integer, ByVal c2 As Integer, ByVal mode As Byte) As Long C/C++ (DOS) int _7200_DO_Timer (U16 c1, U16 c2, Boolean mode) @ Argument frequency divider of Counter #1 c1 :...

  • Page 67: Chapter 6 Double Buffer Mode Principle

    Double Buffer Mode Principle The data buffer for a double-buffered DMA DI operation is logically a circular buffer divided into two equal halves. The double-buffered DI begins when the device starts writing data into the first half of the circular buffer (Figure 6-1a). After device begins writing to the second half of the circular buffer, users can copy the data from the first half into the transfer buffer (Figure 6-1b).
  • Page 68 The PCI-7200 double buffer mode functions were designed according to the principle described above. If using _7200_DblBufferMode() to enable double buffer mode, _7200_DI_DMA_Start() will perform double-buffered DMA DI. Call _7200_CheckHalfReady() to check if data in the circular buffer is half-full ready copying transfer...

  • Page 69: Chapter 7 Limitations

    Limitations The 12MB/sec data transfer rate can only be possibly achieved in systems where the PCI-7200 card is the only device using the bus, but the speed can not be guaranteed due to the limited FIFO depth. The PCI-7200 supports three input clock modes, internal clock, external clock, and handshaking modes.

  • Page 71: Warranty

    Warranty Policy Thank you for choosing ADLINK. To understand your rights and enjoy all the after-sales services we offer, please read the following carefully: Before using ADLINK’s products please read the user manual and follow the instructions exactly. When sending in damaged products for repair, please attach an RMA application form.

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