ADLINK Technology PCI-7442 User Manual
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ADLINK Technology PCI-7442 User Manual

128-ch/64-ch isolated digital i/o cards
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PCI-7442/7443/7444
128-CH/64-CH Isolated Digital I/O Cards
Manual Rev.
Revision Date:
Part No:
Advance Technologies; Automate the World.
NuDAQ
User's Manual
2.50
May 7, 2013
50-11218-2010
®

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Summary of Contents for ADLINK Technology PCI-7442

  • Page 1 NuDAQ ® PCI-7442/7443/7444 128-CH/64-CH Isolated Digital I/O Cards User’s Manual Manual Rev. 2.50 Revision Date: May 7, 2013 Part No: 50-11218-2010 Advance Technologies; Automate the World.
  • Page 2 Initial Release 2.50 2013/05/07 Updated Package Contents Copyright 2013 ADLINK TECHNOLOGY INC. All Rights Reserved. The information in this document is subject to change without prior notice in order to improve reliability, design, and function and does not represent a commitment on the part of the manufacturer.
  • Page 3 Sales & Service info@adlinktech.com Toll-Free +1-866-4-ADLINK (235465) Fax No. +1-949-727-2099 Mailing Address 8900 Research Drive, Irvine, CA 92618, USA ADLINK TECHNOLOGY EUROPEAN SALES OFFICE Sales & Service emea@adlinktech.com Toll-Free +49-211-4955552 Fax No. +49-211-4955557 Mailing Address Nord Carree 3, 40477 Düsseldorf, Germany ADLINK TECHNOLOGY SINGAPORE PTE LTD Sales &...
  • Page 4 ADLINK TECHNOLOGY BEIJING Sales & Service market@adlinkchina.com.cn Telephone No. +82-2-20570565 Fax No. +82-2-20570563 Mailing Address 4F, Kostech Building, 262-2, Yangjae-Dong, Seocho-Gu, Seoul, 137-130, Korea ADLINK TECHNOLOGY BEIJING Sales & Service market@adlinkchina.com.cn Telephone No. +86-10-5885-8666 Fax No. +86-10-5885-8625 Mailing Address Room 801, Building E, Yingchuangdongli Plaza, No.1 Shangdidonglu, Haidian District,...
  • Page 5 Using this manual 1.1 Audience and scope ® This manual guides you when using ADLINK NuDAQ digital input/output PCI cards. The card’s hardware and register informa- tion are provided for faster application building. This manual is intended for computer programmers and hardware engineers with advanced knowledge of data acquisition and high-level program- ming.
  • Page 6 1.3 Conventions Take note of the following conventions used throughout the man- ual to make sure that you perform certain tasks and instructions properly. NOTE Additional information, aids, and tips that help you per- form particular tasks. IMPORTANT Critical information and instructions that you MUST perform to complete a task.

  • Page 7: Table Of Contents

    DAQ-LVIEW PnP: LabVIEW® Driver ......6 DAQBenchTM: ActiveX Controls ........7 2 Hardware Information ............9 Card Layout ................. 9 Bracket Layout .............. 12 PCI-7442 Pin Assignments..........13 CN2 Connector ............. 13 CN1 Connector ............. 15 PCI-7443 Pin Assignments..........17 CN2 Connector ............. 17 CN1 Connector .............
  • Page 8 4 Register Format ..............33 PCI-7442 I/O Registers............33 Isolated Digital Input Register ........33 COS Interrupt Control Registers ........34 Interrupt Status, COS INT Control Read Back Registers 36 COS Setup/Latch Registers .......... 37 TTL IO Setup, Status, DO and DI Registers ....38 Isolated Digital Output and Read Back Registers ..
  • Page 9 List of Tables Table 2-1: TTL/IO (JP3) Connector Pin Assignments ..... 25 Table 2-2: TTL/IO (JP4) Connector Pin Assignments ..... 25 Table 2-3: Board ID Settings ........... 26 List of Tables...
  • Page 10 List of Tables...
  • Page 11 List of Figures Figure 2-1: PCI-7442 Layout............9 Figure 2-2: PCI-7443 Layout............10 Figure 2-3: PCI-7444 Layout............11 Figure 2-4: PCI-7440 Series Card Bracket ........ 12 Figure 2-5: PCI-7440 Series Connector Pin Reference ..... 12 Figure 3-1: Photo Coupler............27 Figure 3-2: COS Timing .............
  • Page 12 List of Figures...

  • Page 13: Introduction

    Introduction The ADLINK PCI-7442, PCI-7443, and PCI-7444 cards are high- density isolated digital I/O cards featuring 128 or 64 channels of digital input, 128 or 64 channels of digital output, and up to 32 TTL channels for a wide range of PCI bus-based industrial applica- tions.

  • Page 14: Features

    — function when WDT interruption occurs Watchdog timer — TTL I/O channels 1250 V isolation Board ID feature 1.2 Applications The PCI-7442/7443/7444 is suitable for these applications: Machine automation Industrial ON/OFF control External relay driving Signal switching Laboratory automation Introduction...

  • Page 15: Specifications

    1.3 Specifications Optical isolated digital input (PCI-7442/PCI-7443 only) Input channels 64 (PCI-7442) 128 (PCI-7443) (Note: Use an efficient cooling system and pay particular attention to the card and chassis temperature when using the digital input channels.) Input voltage High: 5 V – 28 V, non-polarity Low: 0 V –...
  • Page 16 C – 80 Humidity 5% to 85% non-condensing Power Power consumption PCI-7442: +5 V at 800 mA (typical) PCI-7443: +5 V at 550 mA (typical) PCI-7444: +5 V at 800 mA (typical) Specifications are subject to change without notice. Introduction...

  • Page 17: Unpacking Checklist

    Obtain authorization from your dealer before returning any product to ADLINK. Check if the following items are included in the package. PCI-7442/PCI-7443/PCI-7444 card ADLINK All-in-One CD User’s manual If any of the items is damaged or missing, contact your dealer immediately.

  • Page 18: Software Support

    1.5 Software Support ADLINK provides versatile software drivers and packages to address different approaches in building a system. Aside from pro- ® gramming libraries such as DLLs for many Windows -based sys- tems, ADLINK also provides drivers for other software packages ®...

  • Page 19: Daqbenchtm: Activex Controls

    DAQBenchTM: ActiveX Controls It is recommended for programmers familiar with ActiveX controls ™ and VB/VC++ programming to use the DAQBench ActiveX Con- trol component library developing applications. ™ ® DAQBench is designed under Windows NT/98 environment. ™ For more information about DAQBench , refer to the user’s guide in the All-in-One CD.
  • Page 20 Introduction...

  • Page 21: Hardware Information

    Hardware Information This chapter provides information on the PCI-7442/7443/7444 card layout, connectors, and pin assignments. 2.1 Card Layout Figure 2-1 shows the location of the PCI-7442 connectors, switch, and jumpers. Figure 2-1: PCI-7442 Layout 64-CH isolated digital output connector 64-CH isolated digital input connector...

  • Page 22: Figure 2-2: Pci-7443 Layout

    Figure 2-2 shows the location of the PCI-7443 connectors and DIP switch. Figure 2-2: PCI-7443 Layout 64-CH isolated digital input connector (IDI 64~127) 64-CH isolated digital input connector (IDI 0~63) Board ID DIP switch 16-CH (TTL0~16) TTL I/O connector 16-CH (TTL16~31) TTL I/O connector Hardware Information...

  • Page 23: Figure 2-3: Pci-7444 Layout

    Figure 2-3 shows the location of the PCI-7444 connectors and DIP switch. Figure 2-3: PCI-7444 Layout 64-CH isolated digital output connector (IDO 64~127) 64-CH isolated digital output connector (IDO 0~63) Board ID DIP switch 16-CH (TTL0~15) TTL I/O connector 16-CH (TTL15~31) TTL I/O connector Hardware Information...

  • Page 24: Bracket Layout

    Bracket Layout CN2A CN2B CN1A CN1B Figure 2-4: PCI-7440 Series Card Bracket Connector Pin Reference Terminal B68 Terminal B34 Terminal B68 Terminal B34 Terminal A1 Terminal A35 Terminal A1 Terminal A35 CN1B CN1A CN2B CN2A Terminal A68 Terminal A68 Terminal B35 Terminal B1 Terminal B35 Terminal B1 Terminal A34...

  • Page 25: Pci-7442 Pin Assignments

    2.2 PCI-7442 Pin Assignments CN2 Connector CN2B CN2A IDO_0 IDO_8 IGND IGND IDO_1 IDO_9 IGND IGND IDO_2 IDO_10 IGND IGND IDO_3 IDO_11 IGND IGND IDO_4 IDO_12 IGND IGND IDO_5 IDO_13 IGND IGND IDO_6 IDO_14 IGND IGND IDO_7 IDO_15 VDD8 VDD7...
  • Page 26 Pin Definition Definition IDO_n Isolated digital output channel n VDD1 common VDD junction for input channel 0-7 VDD2 common VDD junction for input channel 8-15 VDD3 common VDD junction for input channel 16-23 VDD4 common VDD junction for input channel 24-31 VDD5 common VDD junction for input channel 32-39 VDD6...

  • Page 27: Cn1 Connector

    CN1 Connector CN1B CN1A IDI_0 IDI_8 COM8 COM7 IDI_1 IDI_9 COM8 COM7 IDI_2 IDI_10 COM8 COM7 IDI_3 IDI_11 COM8 COM7 IDI_4 IDI_12 COM8 COM7 IDI_5 IDI_13 COM8 COM7 IDI_6 IDI_14 COM8 COM7 IDI_7 IDI_15 COM8 COM7 COM1 COM2 IDI_63 IDI_55 COM1 COM2 IDI_62...
  • Page 28 Pin Definition Definition IDI_n Isolated digital input channel n COM1 common junction for input channel 0-7 COM2 common junction for input channel 8-15 COM3 common junction for input channel 16-23 COM4 common junction for input channel 24-31 COM5 common junction for input channel 32-39 COM6 common junction for input channel 40-47 COM7...

  • Page 29: Pci-7443 Pin Assignments

    2.3 PCI-7443 Pin Assignments CN2 Connector CN2B CN2A IDI_64 IDI_72 COM16 COM15 IDI_65 IDI_73 COM16 COM15 IDI_66 IDI_74 COM16 COM15 IDI_67 IDI_75 COM16 COM15 IDI_68 IDI_76 COM16 COM15 IDI_69 IDI_77 COM16 COM15 IDI_70 IDI_78 COM16 COM15 IDI_71 IDI_79 COM16 COM15 COM9 COM10 IDI_127...
  • Page 30 Pin Definition Definition IDI_n Isolated digital input channel n COM9 common junction for input channel 64-71 COM10 common junction for input channel 72-79 COM11 common junction for input channel 80-87 COM12 common junction for input channel 88-95 COM13 common junction for input channel 96-103 COM14 common junction for input channel 104-111 COM15...

  • Page 31: Cn1 Connector

    CN1 Connector CN1B CN1A IDI_0 IDI_8 COM8 COM7 IDI_1 IDI_9 COM8 COM7 IDI_2 IDI_10 COM8 COM7 IDI_3 IDI_11 COM8 COM7 IDI_4 IDI_12 COM8 COM7 IDI_5 IDI_13 COM8 COM7 IDI_6 IDI_14 COM8 COM7 IDI_7 IDI_15 COM8 COM7 COM1 COM2 IDI_63 IDI_55 COM1 COM2 IDI_62...
  • Page 32 Pin Definition Definition IDI_n Isolated digital input channel n COM1 common junction for input channel 0-7 COM2 common junction for input channel 8-15 COM3 common junction for input channel 16-23 COM4 common junction for input channel 24-31 COM5 common junction for input channel 32-39 COM6 common junction for input channel 40-47 COM7...

  • Page 33: Pci-7444 Pin Assignments

    2.4 PCI-7444 Pin Assignments CN2 Connector CN2B CN2A IDO_64 IDO_72 IGND IGND IDO_65 IDO_73 IGND IGND IDO_66 IDO_74 IGND IGND IDO_67 IDO_75 IGND IGND IDO_68 IDO_76 IGND IGND IDO_69 IDO_77 IGND IGND IDO_70 IDO_78 IGND IGND IDO_71 IDO_79 VDD16 VDD15 VDD9 VDD10 IDO_127...
  • Page 34 Pin Definition Definition IDO_n Isolated digital output channel n VDD9 common VDD junction for input channel 64-71 VDD10 common VDD junction for input channel 72-79 VDD11 common VDD junction for input channel 80-87 VDD12 common VDD junction for input channel 88-95 VDD13 common VDD junction for input channel 96-103 VDD14...

  • Page 35: Cn1 Connector

    CN1 Connector CN1B CN1A IDO_0 IDO_8 IGND IGND IDO_1 IDO_9 IGND IGND IDO_2 IDO_10 IGND IGND IDO_3 IDO_11 IGND IGND IDO_4 IDO_12 IGND IGND IDO_5 IDO_13 IGND IGND IDO_6 IDO_14 IGND IGND IDO_7 IDO_15 VDD8 VDD7 VDD1 VDD2 IDO_63 IDO_55 IGND IGND IDO_62...
  • Page 36 Pin Definition Definition IDO_n Isolated digital output channel n VDD1 common VDD junction for input channel 0-7 VDD2 common VDD junction for input channel 8-15 VDD3 common VDD junction for input channel 16-23 VDD4 common VDD junction for input channel 24-31 VDD5 common VDD junction for input channel 32-39 VDD6...

  • Page 37: Ttl I/O Connector Pin Assignments

    2.5 TTL I/O Connector Pin Assignments Function Function TTLIO_0 TTLIO_8 TTLIO_1 TTLIO_9 TTLIO_2 TTLIO_10 TTLIO_3 TTLIO_11 SGND SGND TTLIO_4 TTLIO_12 TTLIO_5 TTLIO_13 TTLIO_6 TTLIO_14 TTLIO_7 TTLIO_15 SGND SGND Table 2-1: TTL/IO (JP3) Connector Pin Assignments Function Function TTLIO_16 TTLIO_24 TTLIO_17 TTLIO_25 TTLIO_18 TTLIO_26...

  • Page 38: Board Id (S1)

    2.6 Board ID (S1) The Board ID feature helps you identify the modules when two or more PCI-7440 Series cards are installed in one system. Accord- ing to a DIP switch configuration located in the S1, you can assign a specific board ID to a designated card and access it correctly through simple software programming.

  • Page 39: Operation Theory

    Operation theory 3.1 Isolated digital input The PCI-7442/7443 card comes with 64/128 opto-isolated digital input channels. The circuit diagram of the isolated input channel is shown in Figure 3-1. Figure 3-1: Photo Coupler The digital input is routed first through a photo-coupler (PC3H4) so that the connection are not polarly sensitive whether using positive or negative voltage.

  • Page 40: Change Of State (Cos) Interrupt

    3.2 Change of State (COS) interrupt Overview The COS (Change of State) means either the input state (logic level) changes from low to high, or from high to low. The COS detection circuit will detect the edge of level change. In the PCI- 7442/7443 card, the COS detection circuit is applied to all the input channels.

  • Page 41: Cos Detection Architecture

    HIGH to LOW or from LOW to HIGH. The COS interrupt system can generate an interrupt request signal and the software can service this request with ISR. Note that PCI-7442 has two banks (bank 0 from DI0 to DI31 and bank 1 from DI32 to 63) while PCI-7443 has four banks (bank 0 from DI0 to DI31 and bank 1 from DI32 to 63;...

  • Page 42: Isolated Digital Output Channels

    First, the PCI-7442/PCI-7444 could automatically con- figure the 64-/128-CH DO initial statuses when powering up. Sec- ond, you can direct the PCI-7442/PCI-7444 to hold the DO statuses and avoid its power-up initial configuration state after a hot system reset. Third, you can direct the PCI-7442/PCI-7444 to automatically configure the 64-/128-CH DO safety statuses when a WDT interruption asserts.

  • Page 43: Watchdog Timer (Wdt)

    In safety-critical applications, you can enable the watchdog timer (WDT) function to automatically generate an interrupt signal, in case the operating system or the PCI-7442/PCI-7444 card crashes. To access this function, you must first configure the watchdog timer overflow counter by windows API. Generally, the trigger source would come from the onboard 32-bit watchdog timer.
  • Page 44 Operation theory...

  • Page 45: Pci-7442 I/O Registers

    4.1 PCI-7442 I/O Registers Isolated Digital Input Register There are 64 isolated inputs on a PCI-7442 card. The statuses of the 64 lines can be read from the four isolated input registers. Each bit corresponds to each channel. The bit value 1 means that the input is ON and 0 means that the input is OFF.

  • Page 46: Cos Interrupt Control Registers

    COS Interrupt Control Registers There are two different interrupt modes in PCI-7442. Both interrupt modes are disabled by default. You can write the registers listed below to enable the interrupt. In the first mode, users enable the COS (Change of State) interrupt function to monitor the status of enabled input channels and whenever the status change from 0 to 1 or 1 to 0.
  • Page 47 Address: BASE+0x46h Reset Value: 0x0000h Read/Write: W CLR1 Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 Bit15 Bit14 Bit13 Bit12 Bit11 Bit10 Bit9 Bit8 Bit15 - 9 Not used Bit7 - 1 Not used Bit0 CLR1: COS 1 interrupt clear 1: Clear;...

  • Page 48: Interrupt Status, Cos Int Control Read Back Registers

    Interrupt Status, COS INT Control Read Back Registers When any COS interrupts occur, these registers provide informa- tion for you to recognize the interrupt status and the interrupt setup condition read back. Address: BASE+0x06h Reset Value: 0x0000h Read/Write: R CIS1 CIS0 Bit7 Bit6...

  • Page 49: Cos Setup/Latch Registers

    COS Setup/Latch Registers The PCI-7442 provides a Change of State (COS) interrupt function on any one of digital input channel. This function allows you to monitor the status of digital input channels by setting these regis- ters. By enabling the COS Setup registers, it will generate an interrupt when the corresponding channel changes its state.

  • Page 50: Ttl Io Setup, Status, Do And Di Registers

    TTL IO Setup, Status, DO and DI Registers The PCI-7442 provides an extra 32-channel TTL I/O function for optional applications. These TTL I/O channels are divided among two 16-bits banks and are divided between two connectors: JP3 and JP4. You may choose the direction of each TTL channel any time by setting up the two-bank TTL IO setup register.
  • Page 51 When the I/O direction setting is input, you can read data through the TTL I/O input channel. Address Value Mapping (MSB----LSB) BASE+0x0Eh TTL_IO_DI[15…0] BASE+0x4Eh TTL_IO_DI[31...16] Bit value: 0: Input is low. 1: Input is high. (Initial value) Register Format...

  • Page 52: Isolated Digital Output And Read Back Registers

    Isolated Digital Output and Read Back Registers There are 64 isolated digital outputs on each PCI-7442 board. These lines are divided between two output connectors: CN2A and CN2B. These are controlled by four 16-bit registers in bank2. Each digital output line is controlled by each bit of the four control registers.
  • Page 53 The isolated DO statuses can be read back from the registers. When you want to read the 64-bit DO statuses, you must first send the Read Back Start command (BASE+0x80h). You can in turn read the isolated DO when DO read back procedure is ready. DO ReadBack Start does not need any register value.

  • Page 54: Power-Up Do Setup/Read Register

    Power-up DO Setup/Read Register When the system enters the power up status, PCI-7442 can enter the initial procedure which sends out the default initial value to 64- CH digital outputs. You can configure the power-up default DO val- ues and store them in the flash memory. With this, the DO goes to a definite status when the system turns on.

  • Page 55: Watchdog Timer Load, Safety Do Setup/Read Back Regis Ters

    Watchdog Timer Load, Safety DO Setup/Read Back Registers The PCI-7442 provides a 32-bit watch dog timer (WDT) with 10 MHz clock. The WDT counter loads the 32-bit value of two 16-bit WDT_LOAD_CONFIG Registers in turn. The corresponding hexa- decimal value you set determines the overflow time of WDT coun- ter.
  • Page 56 You can read the configured the Safety DO values which are stored in the flash memory by sending out the WDTSafety DO ReadBack command (BASE+0x96h). The flash memory read pro- cedure starts in 50 ms. The finished flag can be checked by nAction_Ready flag.

  • Page 57: Wdt Int Control, Hot-Reset, And Hold Control Register

    WDT INT Control, Hot-Reset, and Hold Control Register There are two different interrupt modes in PCI-7442: the COS INT function and the watch dog timer (WDT). You may enable the WDT counter and let it count down as a mode of intrrupt. The interrupt asserts when the watch dog timer counter counts to zero.
  • Page 58 1: Clear WDT interrupt 0: No effect Bit3 WSOE: WDT Safety DO Send Out Enable 1: Enabled 0: Disabled Address: BASE+0x8Ah Reset Value: 0x0000h Read/Write: R ARDYS SRDYS RBRDYS SOES WDTES HRHES Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 Bit15 Bit14 Bit13...

  • Page 59: Pci-7443 I/O Registers

    4.2 PCI-7443 I/O Registers Isolated Digital Input Registers There are 128 isolated digital inputs on the PCI-7443 card. The statuses of the 128 lines can be read from the registers listed below. Each bit corresponds to each channel. Address Value Mapping (MSB----LSB) BASE+0x02h IDI[15...0] BASE+0x04h...

  • Page 60: Cos Interrupt Control Registers

    COS Interrupt Control Registers The interrupt mode in the PCI-7443 is disabled by default. You can write the registers listed below to enable the interrupt function. In interrupt mode, you may enable the COS (Change of State) inter- rupt function to monitor the statuses of enabled input channels whenever the statuses change from 0 to 1 or from 1 to 0.
  • Page 61 Bit8 EA0: COS 0 Interrupt enable/disable 1: Enabled; 0: Disabled Address: BASE+0x46h Reset Value: 0x0000h Read/Write: W CLR1 Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 Bit15 Bit14 Bit13 Bit12 Bit11 Bit10 Bit9 Bit8 Bit15 - 9 Not used Bit7 - 1 Not used Bit0 CLR1: COS 1 interrupt clear...
  • Page 62 Address: BASE+0xC6h Reset Value: 0x0000h Read/Write: W CLR3 Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 Bit15 Bit14 Bit13 Bit12 Bit11 Bit10 Bit9 Bit8 Bit15 - 9 Not used Bit7 - 1 Not used Bit0 CLR3: COS 3 interrupt clear 1: Clear;...

  • Page 63: Interrupt Status, Cos Int Control Read Back Registers

    Interrupt Status, COS INT Control Read Back Registers When any COS interrupt occurs, these registers provide informa- tion to recognize the interrupt status and the interrupt setup condi- tion read back. Address: BASE+0x06h Reset Value: 0x0000h Read/Write: R C3IS C2IS C1IS C0IS Bit7...
  • Page 64 Address: BASE+0x46h Reset Value: 0x0000h Read/Write: R Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 COS1E Bit15 Bit14 Bit13 Bit12 Bit11 Bit10 Bit9 Bit8 Bit14 - 0 Not used Bit15 COS1E: COS 1 Interrupt enable status 1: Enabled 0: Disabled Address: BASE+0x86h Reset Value: 0x0000h Read/Write: R...

  • Page 65: Cos Setup/Latch Registers

    COS Setup/Latch Registers The PCI-7443 provides the Change-of-State (COS) interrupt func- tion in each digital input channel. This function allows you to moni- tor the status of input channels by setting these registers. By enabling the COS Setup registers, the card generates an interrupt when the corresponding channel changes its state.
  • Page 66 When COS occurs, the COS Latch registers also latch the DI[31..0], DI[63..32],DI[95..64], and DI[127..96] data, respectively. Once you clear the interrupt request, the COS Latch register clears automatically. Since you can read these registers to know the statuses after interrupts, these registers free the CPU from constantly polling all inputs and enable the system to handle more tasks.

  • Page 67: Address Base+0X0Ch Base+0X4Ch Bit Value

    TTL IO Setup, Status, DO and DI Register The PCI-7443 provides an extra 32-CH TTL I/O function for optional applications. These TTL I/O channels are divided into two 16-bits banks. These channels are divided between two connec- tors: JP3 and JP4. You can choose the direction of each TTL channel any time by setting up the two-bank TTL IO setup register.

  • Page 68: Through The Ttl I/O Output Channel

    When the I/O direction setting is input , users can read data through the TTL I/O input channel. Address Value Mapping (MSB----LSB) BASE+0x0Eh TTL_IO_DI[15...] BASE+0x4Eh TTL_IO_DI[31...16] Bit value: 0: Input in low logic. 1: Input in high logic. (Default) Register Format...

  • Page 69: Pci-7444 I/O Registers

    4.3 PCI-7444 I/O Registers Isolated Digital Output/Read Back Registers The PCI-7444 has 128 isolated digital outputs. These lines are divided between four output connectors, CN1A, CN1B, CN2A, and CN2B. They are controlled by eight 16-bit registers. Each digital output line is controlled by each bit of the eight control registers. You must send out the corresponding DO output data and send out the start command in the end.
  • Page 70 Port0: Isolated digital output channel range from bit0 to bit63 Port1: Isolated digital output channel range from bit64 to bit127 All Ch.: Isolated digital output channel range from bit0 to bit127 You may read the isolated DO statuses from the registers. To read the 128-bit DO statuses, you must first send the Read Back Start (All Ch., Port0, Port1) command.

  • Page 71: Power-Up Do Setup/Read Back Register

    Power-up DO Setup/Read Back Register After the system powers up, the PCI-7444 can enter the initial pro- cedure which sends out the default initial value to 128-CH digital outputs. You can configure the default power-up DO values and store them in the flash memory to prevent the DO from entering an unknown status when the system turns on.
  • Page 72 Address Value Mapping (MSB----LSB) BASE+0x16h Read Back Start BASE+0x18h IDO[15...0] BASE+0x1Ah IDO[31...16] BASE+0x1Ch IDO[47...32] BASE+0x1Eh IDO[63...48] BASE+0x20h IDO[79...64] BASE+0x22h IDO[95...80] BASE+0x24h IDO[111...96] BASE+0x26h IDO[127...112] Bit value: 0: Output PowerMOSFET is OFF. (Initial value) 1: Output PowerMOSFET is ON. You need not assign a register value for the Power-Up Initial DO All Ch.

  • Page 73: Wdt Load Config, Safety Do Setup/Read Back Registers

    WDT Load Config, Safety DO Setup/Read Back Registers The PCI-7444 provides a 32-bit watch dog timer (WDT) with 10 MHz clock. The WDT counter loads the 32-bit value of two 16-bit WDT_LOAD_CONFIG Registers in turn. The corresponding hexa- decimal value you set determines the overflow time of WDT coun- ter.
  • Page 74 Address Value Mapping (MSB----LSB) BASE + 0x26h IDO[15…..0] BASE + 0x28h IDO[31…..16] BASE + 0x2Ah IDO[47…..32] BASE + 0x2Ch IDO[63…..48] BASE + 0x2Eh IDO[79…..64] BASE + 0x30h IDO[95…..80] BASE + 0x32h IDO[111….96] BASE + 0x34h IDO[127..112] Bit value: 0: Output PowerMOSFET is OFF (Initial value). 1: Output PowerMOSFET is ON.

  • Page 75: Wdt Int Control / Hot-Reset Hold Control Register

    WDT INT Control / Hot-Reset Hold Control Register The PCI-7444 has the watchdog timer as interrupt mode. The WDT interrupt mode is disabled by default. In this mode, you can enable the WDT to count down. The interrupt asserts when the WDT Counter reaches to zero.
  • Page 76 1: Function is enabled 0: Function is disabled Address: BASE+0x3Ah Reset Value: 0x0000h Read/Write: R ARDYS SRDYS RBRDYS SOES WDTES HRHES Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 Bit15 Bit14 Bit13 Bit12 Bit11 Bit10 Bit9 Bit8 Bit15 - 7 Not used Bit6 ARDYS: Flash Data Read/Write Finished Status...

  • Page 77: 0: I/O Direction Is Input. (Default) 1: I/O Direction Is Output

    TTL IO Setup, Status, DO and DI Registers The PCI-7444 provides an extra 32-CH TTL I/O function for optional applications. These TTL I/O channels are divided into two 16-bit banks. These channels are divided between two connec- tors: JP3 and JP4. You can choose the direction of each TTL channel any time by setting up the two-bank TTL IO setup register.
  • Page 78 When the I/O direction setting is input, you can read data through the TTL I/O input channel. Address Value Mapping (MSB----LSB) BASE+0x40 TTL_IO_DI[15…0] BASE+0x42 TTL_IO_DI[31...16] Bit value: 0: Input in low logic. 1: Input in high logic. (Default) Register Format...

  • Page 79: Handling Pci Controller Registers

    PCI bus. When you want to develop your own interrupt function driver, both interrupt registers in PCI- 9030 and in the PCI-7442/7443/7444 card have to work together. For detailed information about the interrupt control register in PCI- 9030, refer to the PCI-9030 databook.
  • Page 80 Register Format...

  • Page 81: Warranty Policy

    Warranty Policy Thank you for choosing ADLINK. To understand your rights and enjoy all the after-sales services we offer, please read the follow- ing carefully. 1. Before using ADLINK’s products please read the user man- ual and follow the instructions exactly. When sending in damaged products for repair, please attach an RMA appli- cation form which can be downloaded from: http:// rma.adlinktech.com/policy/.
  • Page 82 3. Our repair service is not covered by ADLINK's guarantee in the following situations: Damage caused by not following instructions in the User's Manual. Damage caused by carelessness on the user's part dur- ing product transportation. Damage caused by fire, earthquakes, floods, lightening, pollution, other acts of God, and/or incorrect usage of voltage transformers.

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