Super Io - ADLINK Technology Express-SL User Manual

Feature
VOC Error Target
Generate BDAT PEG Margin Data
PCIe Rx CEM Test Mode
PCIe Spread Spectrum Clocking
7.3.8

Super IO

Feature
Super IO Chip
W83627DHG Super IO Configuration
Serial Port 1 Configuration
Serial Port
Device Settings
Change Settings
Serial Port 2 Configuration
Serial Port
Device Settings
Change Settings
Device Mode
Options
2
Disabled
Generate Port Jitter Data
Disabled
Enabled
Enabled
Disable
Options
Info only
Info only
Enabled
Disabled
IO=3F8h; IRQ=4
Auto
IO=3F8h; IRQ=4
IO=3F8h; IRQ=3,4,5,6,7,9,10,11,12
IO=2F8h; IRQ=3,4,5,6,7,9,10,11,12
IO=3E8h; IRQ=3,4,5,6,7,9,10,11,12
IO=2E8h; IRQ=3,4,5,6,7,9,10,11,12
Enabled
Disabled
IO=2F8h; IRQ=3
Auto
IO=2F8h; IRQ=3
IO=3F8h; IRQ=3,4,5,6,7,9,10,11,12
IO=2F8h; IRQ=3,4,5,6,7,9,10,11,12
IO=3E8h; IRQ=3,4,5,6,7,9,10,11,12
IO=2E8h; IRQ=3,4,5,6,7,9,10,11,12
Standard Serial Port Mode
IrDA Active pulse 1.6 uS
IrDA Active pulse 3/16 bit time
ASKIR Mode
71
Description
The VOC margin search error target value [1..65535]
Enable to generate BDAT PCIe margin tables
Enable/Disable PEG Rx CEM Loopback Mode
Allows disabling of Spread Spectrum Clocking for compliance
testing
Description
Enable/Disable Serial Port (COM).
Fixed configuration of serial port.
Select an optimal setting for Super IO device.
Enable/Disable Serial Port (COM).
Fixed configuration of serial port.
Select an optimal setting for Super IO device.
Express-SL/SLE