Appendix D. Post Code Errors - Intel M20NTP1UR System Integration And Serive Manual

Intel® Server System M20NTP1UR - System Integration and Service Guide
Most error conditions encountered during POST are reported using POST error codes. These codes
represent specific failures, warnings, or information. POST error codes may be displayed in the error
manager display screen and are always logged to the System Event Log (SEL). Logged events are available to
system management applications, including remote and Out of Band (OOB) management.
Checkpoint Ranges
Status Code
Range
0x01 – 0x0B
0x0C – 0x0F
0x10 – 0x2F
0x30 – 0x4F
0x50 – 0x5F
0x60 – 0x8F
0x90 – 0xCF
0xD0 – 0xDF
0xE0 – 0xE8
0xE9 – 0xEF
0xF0 – 0xF8
0xF9 – 0xFF
Standard Checkpoints
Security (SEC) Phase
Status Code
0x00
0x01
0x02
0x03
0x04
0x05
0x06
0x07
0x08
0x09
0x0A
0x0B
90

Appendix D. POST Code Errors

SEC execution
SEC errors
PEI execution up to and including memory detection
PEI execution after memory detection
PEI errors
DXE execution up to BDS
BDS execution
DXE errors
S3 Resume (PEI)
S3 Resume errors (PEI)
Recovery (PEI)
Recovery errors (PEI)
Not used
Progress Codes
Power on. Reset type detection (soft/hard).
AP initialization before microcode loading
North Bridge initialization before microcode loading
South Bridge initialization before microcode loading
OEM initialization before microcode loading
Microcode loading
AP initialization after microcode loading
North Bridge initialization after microcode loading
South Bridge initialization after microcode loading
OEM initialization after microcode loading
Cache initialization
Description
Description