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AT8402
3.1.4.5
Flash ROM
The CPU uses a 64 Mbyte Flash Memory device. The sectors containing the bootloader code
are write protected, which can be disabled by setting jumper FWPD.
3.1.5
Synchronous Clock Distribution
The Clock CPLD is the global Clock distribution device on the carrier board. In conjunction with
the Zarlink ZL30410 protection switch, the CPLD distributes all necessary Telecom clocks to or
from the AMCs and the backplane.
TCLKA and TCLKC of any AMC can be driven by any backplane clock (CLK1A/B, CLK2A/B or
CLK3A/B). TCLKB and TCLKD of any AMC can drive any backplane clock. Any ATCA back-
plane clock can be used as the Zarlink reference clock input.
For more information on how to configure the clock distribution, refer to the AT8402 CLI Refer-
ence Manual.
3.1.6
AMC Bays
Up to four mid-size and single width or up to two mid-size and double width AMC bays for stan-
dard or custom AMCs are implemented with B+ AMC connectors, depending on the board op-
tion.
Table 3-8:
AMC Slot Types
Board
B1
option
Single width
A
AMC.1 Type 4E2S2
B
-
C
-
Single width
D
AMC.1 Type 4E2S2
Both Telecom clocks and PCI Express clock are supported on each AMC Bay.
Because of the AMC slot storage interconnects (see section 3.1.3.3) and for thermal reasons,
the preferred Processor AMC slots are B1 and B2 and the preferred HDD-AMC slots are B3
and B4. The PCI Express root complex is attached to port B2 by default. This configuration can
be changed using the CLI, refer to the AT8402 CLI Reference Manual.
B2
Single width
Single width
AMC.1 Type 8E2S2
AMC.1 Type 4E2S1
Double width
AMC.1 Type 8E2S2
Double width
Single width
AMC.1 Type 8E2S2
AMC.1 Type 4E2S1
Single width
AMC.1 Type 8E2S2
Page 3 - 9
Hardware Description
B3
Single width
AMC.1 Type 8E2S1
Double width
-
AMC.1 Type 8E2S1
Single width
AMC.1 Type 8E2S1
Double width
-
AMC.1 Type 8E2S1
AT8402 User Guide
B4
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