Spectrum Digital XDS560R Installation Manual page 30

Distributor of Spectrum Digital Inc: Excellent Integrated System Limited
Datasheet of 702570 - TARGET ADAPTER CBL 20P CTI JTAG
Contact us: sales@integrated-circuit.com Website: www.integrated-circuit.com
Importance of Good Design Practices
CAUTION
The target board designer should use good design practices to
minimize signal crosstalk and signal skew. The designer must also
take into account any propagation delays of these signals and the
effect that they will have on the timing of the emulation.
Vcc I/O
5
TVD
4
GND
6
GND
8
GND
10
GND
12
GND
GND
❏
The EMU0 and EMU1 signals must have pull-up resistors connected to V
provide a signal rise time of less than 10 us. A 4.7 kW resistor is suggested for most
applications.
❏
The input buffers for TMS and TDI should have pull-up resistors connected to V
hold these signals at a known value when the emulator is not connected. A resistor
value of 4.7 kW or greater is suggested.
❏
To have high-quality signals (especially the processor TCK and the emulator
TCK_RET signals), you may have to employ special care when routing the PWB
trace. You also may have to use termination scheme, which is appropriate for your
design to match the trace impedance. The emulator pod provides optional internal
parallel terminators on the TCK_RET and TDO. TMS and TDI provide fixed series
termination.
❏
Since TRST is an asynchronous signal, it should be buffered as needed to insure
sufficient current to all target devices.
❏
Additional considerations should be taken into account when designing a target
board. Such considerations include signal loading of vias and the like.
Emulation Header
13
EMU0
14
EMU1
2
TRST
1
TMS
3
TDI
7
TDO
11
TCK
9
TCK_RET
Greater than 6 Inches
Figure 3-6, Buffered Signal Connections
Spectrum Digital, Inc
Vcc I/O
Target Device
EMU0
EMU1
TRST
TMS
TDI
TDO
TCK
to
CC
to
CC
3-11