Spectrum Digital XDS560R Installation Manual page 26

Distributor of Spectrum Digital Inc: Excellent Integrated System Limited
Datasheet of 702570 - TARGET ADAPTER CBL 20P CTI JTAG
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3.4 XDS560R Emulator Cable Pod Signal Timing
Figure 3-4 shows the default timing waveforms for the XDS560R emulator cable pod.
The table below defines the timing parameters. These timing parameters are calculated
from values specified in the standard data sheets for the emulator and cable pod and
are for reference only.
The presented timing parameters are calculated for the end of the 14-pin target cable
header. Texas Instruments does not test or guarantee these timings.
The XDS560 emulator cable pod uses TCK_RET as its clock source for internal
synchronization. TCK is provided as an optional target system test-clock source.
TCK_RET
TMS/TDI
Table 2: Emulator Pod Timing Parameters
No Reference
1 t
c (T C K )
2 t
w( T CKH )
3 t
w( T CKL )
4 t
pd( T M S - T DI )
5 T
s u ( T D O )
6 T
hd (TD O )
Note: The delay timing for TMS/TDI valid is calculated for the default rising edge
TCK_RET. The delay time for TMS/TDI valid for a falling edge TCK_RET
configuration is vary similar.
2
4
TDO
Figure 3-4, Emulator Pod Timings
Description
Cycle time, TCK_RET
Pulse duration, TCK_RET high
Pulse duration, TCK_RET low
Delay time, TMS/TDI valid from TCK_RET high
Setup time, TDO valid before TCK_RET high
Hold time, TDO valid after TCK_RET high
Spectrum Digital, Inc
1
3
6
5
Min
20
10
10
2.5
Max Units
ns
ns
ns
18 31 ns
ns
0 ns
3-7