Clock Source - Texas Instruments ADS1271EVM-PDK User Manual

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CLKXMODE
0 (Low)
1 (High)
5.6.1.3 OBCLKSEL Routing
OBCLKSEL selects between one of two master clock sources. When OBCLKSEL is high, the onboard
clock is active and used for the master clock. When OBCLKSEL is low, the master clock is taken from
EXTCLK on J2, and the onboard oscillator is disabled.
A pull-down resistor is installed on OBCLKSEL, making connection to an external clock the default setting.
OBCLKSEL
0 (Low)
1 (High)
5.6.2 ADS1271 Communication Modes
The ADS1271EVM supports both interface modes for the ADS1271. The interface mode is chosen using
switch S7, located near the top-right corner of the EVM.
Depending of the communication mode, J2 pin 9 (FSR on the bottom connector and FSOUT on the top
connector) connect to different signals (see
In SPI mode, FSR is connected to DRDY output signal from the first ADC (U8), while the second ADC
(U7) DRDY line is not connected. FSOUT is not connected.
In FSYNC mode, the FSYNC pins of both ADCs are tied together, and the signal on FSR is copied to the
top connector on pin FSOUT.
J2 Pin 9
FSOUT (Top side)
FSR (Bottom side)
These configurations provide th capability of stacking ADS1271EVMs in either mode. To stack EVMs,
each EVM is required to operating in the same mode.
The MMB0 has the ability to determine the configuration of S7 by monitoring the FSDIR pin on J2. This
pin is high when FSOUT is active and FSR is an input, and low when FSOUT is disconnected and FSR is
an output.
5.7

Clock Source

The ADS1271 requires a clock signal for proper operation. Several options are available to source this
clock signal to the ADC.
5.7.1 Onboard Oscillator
A 27MHz clock oscillator is included on the EVM and is selected as the clock source for the device when
OBCLKSEL (J2.19) is high.
SBAU107C – November 2004 – Revised November 2014
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Table 14. CLKX Routing
CLKX Direction
Output
Table 15. OBCLKSEL
Table 16).
Table 16. J2 Pin 9 Routing
Communications Mode
SPI Mode
FSYNC Mode
SPI Mode
FSYNC Mode
Copyright © 2004–2014, Texas Instruments Incorporated
Input
Master Clock is connected to:
EXTCLK (J2.17)
On-board clock (U13)
ADC1 (U8)
Not connected
FSYNC
DRDY
FSYNC
ADS1271EVM and ADS1271EVM-PDK User's Guide
ADS1271EVM Hardware Details
CLX Connected to:
not connected
CLK
ADC2 (U7)
Not connected
FSYNC
Not connected
FSYNC
13