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2.7.3
Cortex Debug+ ETM Connector (20-pin)
The CPU_42A-V1 board supports Serial Wire Debug operation, Serial Wire viewer operation (via SWO
connection when Serial Wire Debug mode is used) through the 20-pin Cortex Debug+ ETM Connector. The
board does not support the Instruction Trace operation.
JTAG Debug operation additionally would require the TDI (P0.7) signal. By default the TDI signal is
disconnected from the Cortex Debug Connectors by a not assembled resistor R410, because the port pin P0.7
is used by the Actuator boards connected to the ACT satellite connector.
GND/TgtPwr+Cap
GND/TgtPwr+Cap
Figure 15
Cortex Debug+ETM Connector (20-pin)
Table 6
Cortex Debug+ ETM Connector (20 Pin)
Pin No.
Signal Name
1
VCC
2
SWDIO / TMS
3
GND
4
SWDCLK / TCK
5
GND
6
SWO / TDO
7
KEY
8
NC / TDI
9
GNDDetect
10
nRESET
11
GND/TgtPwr+Cap
12
TRACECLK
13
GND/TgtPwr+Cap
14
TRACEDATA[0]*
15
GND
Board User's Manual
Cortex Debug+ETM
Connector (20-pin)
VCC
1
GND
3
5
GND
KEY
7
GNDDetect
9
11
13
15
GND
GND
17
GND
19
Serial Wire Debug
+3.3 V
Serial Wire Data I/O
Ground
Serial Wire Clock
Ground
Trace Data OUT
KEY
Not connected
Ground Detect
Reset (Active Low)
Ground
TRACECLK
Ground
TRACEDATA[0]
Ground
CPU Board XMC4200 Actuator
2
SWDIO / TMS
4
SWDCLK / TCK
6
SWO / TDO / EXTa / TRACECTL
8
NC/EXTb/TDI
10
nRESET
12
TRACECLK(NC)
14
TRACEDATA[0] (NC)
16
TRACEDATA[1] (NC)
18
TRACEDATA[2] (NC)
20
TRACEDATA[3] (NC)
cortex_20pin.emf
18
CPU_42A-V1
Hardware Description
JTAG Debug
+3.3 V
Test Mode Select
Ground
Test Clock
Ground
Test Data OUT
KEY
Test Data IN
Ground Detect
Reset (Active Low)
Ground
TRACECLK
Ground
TRACEDATA[0]
Ground
Revision 1.0, 2013-02-19
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