Infineon iMOTION IRDM983-025MB Reference Manual
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Infineon iMOTION IRDM983-025MB Reference Manual

Infineon iMOTION IRDM983-025MB Reference Manual

Motion controller module for pm ac fan
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IRDM983-025 / -035MB
Reference Manual
iMOTION™ Motion Controller Module for PM AC Fan
Quality Requirement Category: Industry
Features
Complete 250V - 500V 3-phase inverter system in one chip
Permanent Magnet Sinusoidal Motors Control by Hall sensors
Only two low cost Hall elements required
High efficiency control by quadratic phase advance curve
Internal clock based on external RC
15V single power supply
3.3V Integrated Voltage Regulator
Integrated protection features:
Dynamic overcurrent , Overtemperature ,
Overspeed, Rotor lock, Undervoltage lockout
Full Three Phase Gate Driver
Integrated Bootstrap Diodes
No heatsink required
12x12 mm² PQFN package
Applications
PM fan motor control
Description
IRDM983-025MB, IRDM983-035MB are the complete PM motor controller including six power MOSFET, high voltage
integrated circuit, high precision analog circuit and integrated digital control algorithm. The controller implements
a Hall sensor based control algorithm for 3-phase sinusoidal permanent magnet motor fan applications.
Other than the IRDM982 the IRDM983 only requires two hall sensors.
The integrated digital controller does not require any programming.
Instead there are 16 load curves stored in the internal ROM that can be selected via two resistor pairs.
The IRDM983 is packaged in the 12 x 12 PQFN package and designed to dissipate the power loss through a PCB
without the use of an external heatsink.
There are two products available depending on the power rating of the internal high voltage MOSFETs:
1) IRDM983-025MB – employs six MOSFETs 500V 2A and 600V high voltage IC
2) IRDM983-035MB – employs six MOSFETs 500V 3A and 600V high voltage IC
Reference Manual
www.infineon.com/iMOTION
Please read the Important Notice and Warnings at the end of this document
Revision 2.0
2015-03-22

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  • Page 1 1) IRDM983-025MB – employs six MOSFETs 500V 2A and 600V high voltage IC 2) IRDM983-035MB – employs six MOSFETs 500V 3A and 600V high voltage IC Reference Manual Please read the Important Notice and Warnings at the end of this document Revision 2.0 www.infineon.com/iMOTION 2015-03-22...
  • Page 2 IRDM983-025/035MB Reference Manual Complete Motion Controller Module for PM AC fan Features Product Summary  Complete 500V 3-phase inverter system in one Topology 3 Phase AC chip  No heat-sink required ≤ 500 V OFFSET  Permanent Magnet Sinusoidal Motors Control by Current phase &...
  • Page 3 IRDM983-025/035MB Revision History 1) IRDM983 DATASHEET REVISION 1 (MAY 5, 2015) 2) INITIAL RELEASE – AUGUST 8, 2015 3) IRDM983 REFERENCE MANUAL REVISION 2 (MARCH 22, 2015) This document is the property of International Rectifier and may not be copied or distributed without expressed consent.

  • Page 4: Table Of Contents

    IRDM983-025/035MB Table of Contents 1.0 INTRODUCTION ......................... 4 2.0 LEAD DEFINITIONS ......................7 3.0 PERIPHERALS AND INPUTS/OUTPUTS ................9 4.0 POWER UP SEQUENCE AND FAULTS ................47 APPENDIX A REGISTER FILE ....................52 APPENDIX B. TEST MODE AND UART COMMUNICATION PROTOCOL ......57 APPENDIX C .

  • Page 5: Introduction

    IRDM983-025/035MB 1.0 Introduction IRDM983-025MB, IRDM983-035MB are the complete PM motor controller including six power MOSFET, high voltage integrated circuit, high precision analog circuit and digital control algorithm. There are two products depending on power rating of internal high voltage MOSFET listed below: 1) IRDM983-025MB –...
  • Page 6 IRDM983-025/035MB Simplified Block Diagram VBUS 15VDC Dynamic UNDERVOLTAGE 3.3VDC (Analog) Overcurrent & VOLTAGE Limit STANDBY REGULATOR AADV 3.3VDC (Digital) TEMP Internal HIGH VOLTAGE Temp sensing REGISTER FILE U DRIVER (H) ALGORITHM & CONTROL POWER-ON BLOCK PSEL RESET U DRIVER (H) HALL1+ HALL1- OVERCURRENT...
  • Page 7 IRDM983-025/035MB Control Block Diagram 20kHz PWM Carrier Frequency Internal Parameter Generation External Parameter VMOD 100% Carrier VMOD 9bit Filter 6 PWM Signals 2.1V 5.4V Current Deadtime Limit Frequency 45rpm Modulator Standby Mode Block commutation to Sinusoidal Enable High side (<10mW) Sinusoidal switch over Low On...

  • Page 8: Lead Definitions

    IRDM983-025/035MB 2.0 Lead Definitions Pin # Symbol Description Voltage Set Point analog input. Provides the value of the PWM modulation index to the controller. Provides speed feedback to through pulsed per revolution. It is an open drain output 15V tolerant. Motor Direction Input (internally pulled up high = UVW) VoltageCurveGain Parameter Input XTAL...
  • Page 9 IRDM983-025/035MB Lead Assignments Back Side View XTAL This document is the property of International Rectifier and may not be copied or distributed without expressed consent.

  • Page 10: Peripherals And Inputs/Outputs

    IRDM983-025/035MB 3.0 Peripherals and Inputs/Outputs The IRDM983-025MB, IRDM983-035MB have several on-chip peripherals including: A/D Converter (for conversion of the analog inputs: VSP, internal temperature and EFF. This section provides the description of the main features and each pin functions. 3.1 VSP Analog Input pin The VSP input has a triple purpose.
  • Page 11 IRDM983-025/035MB VMOD 100% (ADC=511) (ADC=199) 1.9V 5.0V Figure 3.2 VSP Range and Thresholds VSP standby description When VSP becomes less than 1.15V, the system goes into the standby mode and all circuit except a few analog circuits are powered off. Basically it disengages internal and external 3.3V power supply and wait for the system to become active.
  • Page 12 IRDM983-025/035MB 1.4V 1.15V Active greater than 5sec Less than 5sec Mode Change Standby Figure 3.4 VSP stand by to active mode example Once the system goes into a standby mode, all digital power and 3.3V analog power are shut off and only comparator circuit to monitor VSP analog input voltage is activated.
  • Page 13 IRDM983-025/035MB These following numbers have been put to the metal option area (described in the appendix) so they could be changed by changing one metal layer only: a. threshold (454) b. timing thresholds (1376 and 551) c. possibility to disable completely this function Figure 3.5 Trap test mode modulation The modulation in trap test mode is shown in figure 3.5 where DIR = 1.
  • Page 14 IRDM983-025/035MB Figure 3.6 Duty in trap test mode depends on forward speed VSP signal path to PWM The detailed signal path of VSP is shown in Figure below. VSP starts with analog input to ADC block followed by filtering and averaging process, and final PWM block. The data range and each function units are described in this Figure.
  • Page 15 IRDM983-025/035MB update, synchronization to ADC section takes place with two filtering blocks, namely 4 times averaging and 10msec filter block, by 20 kHz clock domain. The start and stop internal command is issue at the output of 10msec digital filter based on the certain digital value. Start/Stop logic: Synchronization If >= 796 START...
  • Page 16 IRDM983-025/035MB TargetVMod11bit [0 1686] TimeCalculator Compare Generator It calculates the time HalfTa, Based on sector, it generates Angle60 [0 682] One multiplexed Sin(angle60) the time HalfTb and the time HalfTa the compare value for each cmpul Sector Finder Cordic rotator [0 4095] HalfT0 PWM command signal.
  • Page 17 IRDM983-025/035MB 3.2 Temperature Sensing The IRDM983-025MB, IRDM983-035MB have an internal temperature sensor. It updates at every 363,3usec and selects appropriate overcurrent threshold value which goes into the hardware over-current limit comparator (see below Figure). This logic described below is the over-temperature limit control at a temperature below 100C degree.
  • Page 18 IRDM983-025/035MB Over-temperature processing Over-temperature fault turns off PWM completely so long as the sensed temperature exceeds 100C Celsius degrees. When over-temperature is engaged, there is a hysteresis to disengage over-temperature at 80C degree. Temperature acquisition to ADC is updated every 363,3 usec at 20MHz as a part of six channel ADC conversion.
  • Page 19 IRDM983-025/035MB 3.3 Hall sensor interface pins, Commutation and PWM The IRDM983-025MB, IRDM983-035MB has direct interface pins for two Hall sensors. The Hall sensors are non-buffered type and have a differential output. The IRDM983-025MB, IRDM983- 035MB are designed to work with particularly HW-101A by Asahi Kasei Microdevices. Each differential Hall signals are buffered by high gain operational amplifier with a preceding 1.5usec analog filter shown in Figure below.
  • Page 20 IRDM983-025/035MB HALL U’ HALL V’ HALL W’ HALL U” Figure 3.16 Hall sensor input qualification filter 3.4 Block commutation within +/-45rpm At starting a motor, up to 45rpm toward the same direction of DIR pin state, the IRDM983-025MB, IRDM983-035MB operates by a block commutation mode based on the Hall signal U’, V’, and W’. When motor rotates reverse and opposite direction of DIR pin state, then regardless of the motor speed, the PWM operation is based on a block commutation.
  • Page 21 IRDM983-025/035MB Transition to/from Block commutation When the speed, measured by hall sensor V (H2) falling edge to falling edge, reaches above 45rpm, a transition occurs and it switches to a two phase SVPWM. This transition is based on the speed measurement by the Hall V” falling edge to falling edge (one electrical revolution) and occurs if speed measurement becomes above 45 rpm by one speed measurement.
  • Page 22 IRDM983-025/035MB CW Direction = 0 Hall U (1) Hall V (2) Virtual Hall W U phase High side gate drive U Phase Low side gate drive 30 degree V Phase High side gate drive V Phase Low side gate drive 30 degree W Phase High side gate drive...
  • Page 23 IRDM983-025/035MB 3.5 Sinusoidal two phase SVPWM Above 45rpm, PWM modulation becomes a sinusoidal two phase SVPWM. In the two phase SVPWM modulation, commutation update occurs every 60 degree quadrant based on the Hall signal input, more specifically Hall signal filtered by a qualification filter described in the section 5.3.
  • Page 24 IRDM983-025/035MB (t2>t1) (t2<t1) U’’ U’’ V’’ V’’ W’’ W’’ Hold Duty update at Hall U Phase U applied voltage Phase U applied voltage edge (not wait till t1 (duty) (duty) period) Duty on hold till Hall U falling edge Figure 3.21 60 degree commutation update The RPM speed measurement is done by the phase V Hall (2) sensor falling edge to falling edge based on the qualified filtered Hall V (2) signal (V”).
  • Page 25 IRDM983-025/035MB V’’’, W’’’ edges. For example, if it persists H and H twice in row, then RDM = H, or if it persists L and L twice in row, then RDM = L. Otherwise it holds the previous state. The meaning of RDM logic states are “L”= Rotate same direction of command / “H”=Rotate opposite direction of command.
  • Page 26 IRDM983-025/035MB Hall W’’’ HALL1’’’ RDM-W edge DIR=H DIR=L Rise Fall Table 3.3 RDM W signal generation Rotation detect (DIR=“H”, command = U-V-W) Rotation = W-V-U (Rewind) , opposite direction of command Rotation = U-V-W, same direction of command Hall-U filtered (50usx3) Hall-V filtered (50usx3)
  • Page 27 IRDM983-025/035MB Rotation detect (DIR=“H”, command = U-V-W) Rotation = U-V-W, same direction of command Rotation = W-V-U (Rewind) , opposite direction of Rotation = U-V-W, same direction of command command Hall-U filtered (50usx3) Hall-V filtered (50usx3) Hall-W filtered (50usx3) Hall-U qualified Hall-V qualified...
  • Page 28 IRDM983-025/035MB Rotation detect (DIR=“L”, command = W-V-U) Rotation = W-V-U, same direction of command Rotation = U-V-W (Rewind) , opposite direction of Rotation = W-V-U, same direction of command command Hall-U filtered (50usx3) Hall-V filtered (50usx3) Hall-W filtered (50usx3) Hall-U qualified Hall-V qualified...
  • Page 29 IRDM983-025/035MB Dynamic DIR change and Rotation detection A motor needs to stop when changing DIR input. In Figure 3.24 it is shown how physically the signal RDMS is represented inside the digital logic. The RDMS signal is split into 2 digital signals that represent 2 distinct type of information: ...
  • Page 30 IRDM983-025/035MB As per figure 3.29 in the event of DIR change while motor is running at sinusoidal operation, there will be some delay in RDMS to reflect a change in DIR which causes generation of distorted sinusoidal waveform for a short period of time. This is due to the method that has been used to generate the detecteddirection signal that was designed not considering dynamic DIR changes.
  • Page 31 IRDM983-025/035MB Figure 3.31 Dynamic DIR change This behavior is known and it is mainly due to the rotation detection logic shown in the next Figure. Latched DIR Detected Figure 3.32 Detected DIR This document is the property of International Rectifier and may not be copied or distributed without expressed consent.
  • Page 32 IRDM983-025/035MB In the event of dynamic change of DIR input, with subsequent new DIR latch due to motor stop and start events, in the moment where detecteddirection is not reflecting the real direction, some distorted sinusoidal modulation waveform may appear (see Figure below). So as a result, to change the direction, the motor must be stopped and then re-started so that the new direction command is latched.
  • Page 33 IRDM983-025/035MB 3.7 COM/VSS pin and Overcurrent limit circuit COM pin is provided for an external shunt resistor for sensing a motor current on the DC bus. An internal analog filter has 1usec time constant in order to eliminate spike noise appearing on the DC bus current associated with diode recovery of main switches at commutation.
  • Page 34 IRDM983-025/035MB VBUS U DRIVER (H) IC PAD IRS6202D (NBC9604 NBC9606) IRS6205D (NBC9605) NBC960X QFN V DRIVER (H) package pin W DRIVER (H) LOW SIDE DRIVERS High Side Overcurrent Limit PWM Off Comparator PWM all off Figure 3.35 COM/VSS connection between IC and QFN package pins COM/VSS pins and the IC pads inside of IRDM983-025MB, IRDM983-035MB are connected by the bonding wires and shown in Figure 3.35.
  • Page 35 IRDM983-025/035MB 3.8 EFF – Phase angle advancement parameter input pin There is one motor parameter called EFF in the system. This pin defines the phase angle advancement between the applied voltage and the BEMF (or Hall sensor). The curve is a quadratic function and 16 (sixteen) selection with a different gain.
  • Page 36 IRDM983-025/035MB Figure 3.36b Phase Gain Parameters (EFF) Selection Scheme – 6 poles motor Figure 3.36c Phase Gain Parameters (EFF) Selection Scheme – 4 poles motor This document is the property of International Rectifier and may not be copied or distributed without expressed consent.
  • Page 37 IRDM983-025/035MB The above curves depend on effective value of the PWM frequency, given the RC network on CLKIN and XTAL pins, since the values in the table below are calculated at nominal PWM frequency of 20 kHz. The following table shows the parameters selections and defaults. Table 3.4a –...
  • Page 38 IRDM983-025/035MB 3.10 Motor Speed Feedback (PG pin) and Feedback Select (PGSEL) The PG pin is an output that indicates the mechanical speed of motor. The speed is expressed in the form of pulses/mechanical rotation. This output pin is an open drain with an on-resistance of 50 ohm.
  • Page 39 IRDM983-025/035MB The IRDM983-025MB, IRDM983-035MB has a common ground for the analog and digital circuitry (VSS) and for the MOSFET’s gate drivers return (COM) which also interconnects to the current sensing input. 3.13 Analog to Digital Converter The IRDM983-025MB, IRDM983-035MB integrate a 9-bit dual-slope A/D Converter to acquire Ground connection voltage for offset compensation of all the other 5 channels, VSP, internal Temperature sensor, EFF, internal voltage reference and Vsp input for 6 step special test mode which totals of six channels.
  • Page 40 IRDM983-025/035MB The dual-slope A/D Converter is independent of both capacitance and the clock frequency, because they affect both the integration and de-integration in the same ratio. Channel Select De-Integration Time (∆t) Fixed Integration Time (T) Zero-ing Phase Integrator Output Zero-ing Phase Conversion Value Counter Total Conversion Time = 1211 System Clock Cycles...
  • Page 41 IRDM983-025/035MB the first channel is clamped to be in the range of [-30 to +30]. The other 5 channels (Vsp, Temperature, EFF, dummy ref. low and Vsp for test mode are then automatically compensated by the measured offset in the first channel. Ground Temp Dummy...
  • Page 42 IRDM983-025/035MB cycle de-integration time for the channel 1 ground. As a net result it is a conversion 10 cycles shorter. The offset in this case is computed as Offset=512-502=10 This means that all other channels would experience a shorter de-integration time of 10 counts thus giving uncompensated result 10 counts bigger (note: remember that ADC result is 512 complement of de-integration time).
  • Page 43 IRDM983-025/035MB 3.14 Clock Generation (XTAL, CLKIN) The IRDM983-025B and IRDM983-035MB have an on-chip PLL (Phase-Locked Loop) to generate the internal system clock. The PLL relies on an internal DCO (Digital Controlled Oscillator) and on and external low-frequency reference input clock of 32.768kHz (32768Hz) to synthesize the internal main clock.
  • Page 44 IRDM983-025/035MB Typical Typical Connections Connections Using Crystal or Using R-C Resonator 47pF XTAL XTAL CLKIN CLKIN 47pF 270pF Note: 1) Typical Value To Match Required Time-Constant Figure 3.47 Typical Required External Circuitry for Clock Generation       ...
  • Page 45 IRDM983-025/035MB 3.15 PLL control algorithm The IRDM983-025MB and RIDM983-035MB have a special PLL control algorithm that is optimized and has the following features:  PLL is updated only during the dummy channel scan so clock variation does not affect the ADC channel conversion ...
  • Page 46 IRDM983-025/035MB In figure 3.48 the signal indicated with ‘Fref rise’ is a pulse that is generated every time the external reference frequency signal exhibits a rising edge. The ‘UPDATE’ signal is a pulse generated when the following condition is met: ADC is in dummy channel conversion (that lasts 1211 fast clock cycles) AND a rising edge of PWM clock occurred.
  • Page 47 IRDM983-025/035MB In Figure 3.49 it is shown the ADC sequence made of 6 channels scan. The channel sequence of the ADC in IRDM983-025MB, IRDM983-035MB is composed of 6 channels, as per previous paragraph description. One of these 6 channels in each sequence is called ‘dummy’ channel and its conversion is discarded and not used in normal operating mode function.

  • Page 48: Power Up Sequence And Faults

    IRDM983-025/035MB 4.0 Power up sequence and Faults 4.1 Power up sequence and standby state The IRDM983-025MB and IRMD983-035MB can be forced into RESET State by the on-chip power-on reset block (POR), by the on-chip supply monitor block (following a 15VDC or 3.3VDC supplies under-voltage).
  • Page 49 IRDM983-025/035MB 4.1.1 VDD voltage in standby In standby state, VDD pin may still exhibit some voltage (usually <100mV). This is normal because the internal digital circuits may not be able to discharge VDD pin to 0V. Ileak1 33VCAP All internal External Parasitic Ileak2...
  • Page 50 IRDM983-025/035MB 4.2.1 Over-Current Limit The over current limit function never causes a trip or reset. It sustains motor running operation PWM cycle by PWM cycle while only engages its functionality. The comparator to determine whether overcurrent or not has a dynamic/variable threshold (four values including rotor lock) depending on the temperature.
  • Page 51 IRDM983-025/035MB The deadtime within the overcurrent limit block is inserted under the following condition. If low side command in input is zero (e.g. ulin=0) then the deadtime is inserted and during deadtime low side command is kept to 0 (ulout=0) and only after deadtime the low side command is raised to one (ulout=1 after dead time).
  • Page 52 IRDM983-025/035MB 4.2.5 Over-speed protection When the speed exceeds 3000rpm (on a 8 poles motor), all PWM becomes off. There is no hysteresis on over-speed. 3000 rpm is based on 20 kHz PWM nominal frequency. If different PWM frequency is used the threshold becomes; over-speed = 3000 RPM x PWMfreq [kHz] / 20kHz.

  • Page 53: Appendix A Register File

    IRDM983-025/035MB Appendix A. Register File Registers Map The IRDM983-025MB, IRDM983-035MB have a set of register that are loaded at power-on or reset with default values stored in the internal ROM. In test mode, a Personal Computer or host processor can modify the value of the registers to control the IRDM983-025MB, IRDM983-035MB device using a standard RS-232 port in test mode.
  • Page 54 IRDM983-025/035MB Address Address Name Width Type (L) decimal (H) decimal raw unfiltered Vsp from ADC raw unfiltered temperature from ADC mechanical speed vsp11bit used in the algorithm modulation ground connection ADC readback EFF ADC readback filtered vsp11bit from ADC Filtered temperature from ADC dbg_temp_ranges* dbg_wires* motorrunacknowledged...
  • Page 55 IRDM983-025/035MB reset_control – address 6 – default 00 force_reset disable_reset_counters force_reset – active high: set to 1 to initiate internal reset disable_reset_counters – active high: set to 1 to disable all counters (e.g. 5 seconds before stand by). uart_controls - address 7 – default 000000 motorstartstop direction pgsel...
  • Page 56 IRDM983-025/035MB Following table shows the possible values for dir_source register dir_source value DIR pad 0 default - input 1 – output 2 – output 3 – output adctimedvalue 4 – output sysclkdiv4 5 – output ncurrentlimit 6 – output HALL1 7 –...
  • Page 57 IRDM983-025/035MB directangladvance – this register is used to feed directly the angle advance in the modulator if enabledirectangleadvance =1 . Range is from [0 to 682] that is [0deg to 60deg]. enabledirectangleadvance - if set to 1 the modulator angle advance is fed directly from directangleadvance register.

  • Page 58: Appendix B. Test Mode And Uart Communication Protocol

    IRDM983-025/035MB adcconvregvspout – this is the 11 bit Vsp input value from ADC after 4 samples sum and 10 ms filter. This is used for PWM modulation if not bypassed by UART. adcconvregvbe - this is the 9 bit ADC conversion of the internal temperature analog input channel after 4 samples average and 10 ms filter.
  • Page 59 IRDM983-025/035MB B.1 Test mode entering mechanism The test mode can be activated only at IC startup. So, if test mode entry is needed, the IC needs to be power cycled. To ensure successful enter in test mode, these steps must be followed: 1- Start with VCC=0V and VSP=0V 2- Do not apply any signal to the IC when it is switched off otherwise a biasing condition with ESD structure may cause interference...
  • Page 60 IRDM983-025/035MB CLKIN XTAL nPOReset testi @ posedge nPLLReset: nPLLReset If (testi == 1) then activate_pad = 1 activate_pad @ (testcounter==2000): Counter starts here If (testi == 1) then activate_pad = 1 and enable_testcounter and counts up to testo =1 2000 and then stops else activate_pad = 0 and testo = 0 testo @20 MHz...
  • Page 61 IRDM983-025/035MB H2+ = 1 MOS VH ON H2+ = 0 MOS VH OFF H2- = 1 MOS VL ON H2- = 0 MOS VL OFF TST2 = 1 MOS WH ON TST2 = 0 MOS WH OFF TST1 = 1 MOS WL ON TST1 = 0 MOS WL OFF...
  • Page 62 IRDM983-025/035MB CLKIN frequency 20MHz Baud rate 19200 Parity None Start bit Stop bit Delimiters None Table B-5 UART setting for Test Mode Byte to be transmitted bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 Start bit = 0 Least bit1 bit2 bit3 bit4...
  • Page 63 IRDM983-025/035MB B.3 RS-232 Register Write Access A Register write operation consists of a command/address byte, byte count, register data and checksum. When the IRDM983-025MB, IRDM983-035MB receives the register data, it validates the checksum, writes the register data, and transmits and acknowledgement to the host. From Host PC or Processor Command Data...
  • Page 64 IRDM983-025/035MB B.5 RS-232 Register Read Access A register read operation consists of a command/address byte, byte count and checksum. When the IRDM983-025MB, IRDM983-035MB receives the command, it validates the checksum and transmits the register data to the host. From Host PC or Processor Command &...

  • Page 65: Appendix C. Package Outline

    IRDM983-025/035MB Appendix C. Package Outline This document is the property of International Rectifier and may not be copied or distributed without expressed consent.
  • Page 66 IRDM983-025/035MB This document is the property of International Rectifier and may not be copied or distributed without expressed consent.

  • Page 67: Appendix D. Package Marking

    IRDM983-025/035MB Appendix D. Package Marking INTERNATIONAL RECTIFIER Logo DEVICE Part Number ASSEMBLY SITE CODE: H: Hana MARKING CODE C: Carsem Y: Engineering IRDM983-025 Q: Qual builds S: Pre production P: Lead Free released W: Lead free samples ?YWW? DATE CODE XXYY PIN 1 IDENTIFIER Year (5 = 2015)

  • Page 68: Appendix E. Soldering Temperature Profile

    IRDM983-025/035MB Appendix E. Soldering temperature profile The following soldering temperature profile is recommended. Any temperature which may exceed those indicated below is not recommended and may cause a permanent damage to the physical component such as deformation. 260C 221C 200C 60-150second 150C 60-80second...
  • Page 69 Technologies, Infineon Technologies’ products may standards concerning customer’s products and any not be used in any applications where a failure of use of the product of Infineon Technologies in the product or any consequences of the use thereof Document reference customer’s applications.

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