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DG_201701_PL21_004
Design guide IDP2303(A)
Design guide for TV power supply with digital multi -mode PFC + LLC
combo IC IDP2303(A)
About this document
Scope and purpose
This design guide is to help customers design a TV power supply using an Infineon digital controller. It provides
guidelines on power stage design, control parameters and protection settings as well as PCB layout and
dpVision GUI usage.
Intended audience
This document is intended for design engineers that want to design a high performance TV power supply using
Infineon's digital multi-mode PFC + LLC combo IC.
Table of contents
About this document .............................................................................................................................................1
Table of contents ...................................................................................................................................................1
1
Abstract ..............................................................................................................................................3
2
Introduction .......................................................................................................................................4
2.1
IC Introduction ........................................................................................................................................ 4
2.2
Pin configuration and description .......................................................................................................... 4
2.3
Product highlights ................................................................................................................................... 5
2.4
Application .............................................................................................................................................. 6
3
PFC design ..........................................................................................................................................7
3.1
Target specifications ............................................................................................................................... 7
3.2
Power stage ............................................................................................................................................. 7
3.2.1
Bridge rectifier .................................................................................................................................... 7
3.2.2
Selection of power MOSFET ............................................................................................................... 8
3.2.3
MOSFET gate driving .......................................................................................................................... 9
3.2.3.1
3.2.3.2
3.2.3.3
3.2.4
Boost diode ...................................................................................................................................... 10
3.2.5
Boost inductor .................................................................................................................................. 10
3.3
Control parameters and protections .................................................................................................... 12
3.3.1
Output voltage sense and protections ............................................................................................ 12
3.3.2
Redundant OVP (ROVP) .................................................................................................................... 13
3.3.3
PFC ZCD divider design .................................................................................................................... 15
3.3.4
Current sense and Over Current Protection (OCP) ......................................................................... 15
3.3.4.1
3.3.4.2
3.3.5
Frequency law for multi-mode PFC ................................................................................................. 19
3.3.5.1
3.3.5.2
3.3.5.3
Application Note
www.infineon.com
Unique gate drive concept ........................................................................................................... 9
Gate drive stability ........................................................................................................................ 9
Other design tips for the gate driving circuit ............................................................................. 10
Over Current Protection(OCP) tolerance & selection of current sense resistor ....................... 16
Verification of PFC inductance with OCP tolerance .................................................................. 19
Multimode PFC ............................................................................................................................ 19
Frequency law ............................................................................................................................. 20
Revision 2.0
2017-05-03
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Table of Contents
Related Manuals for Infineon IDP2303
Summary of Contents for Infineon IDP2303
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Page 1: Table Of Contents
About this document Scope and purpose This design guide is to help customers design a TV power supply using an Infineon digital controller. It provides guidelines on power stage design, control parameters and protection settings as well as PCB layout and dpVision GUI usage. - Page 2 Design guide IDP2303(A) Abstract 3.3.6 AC brown-in & out ..........................22 LLC design ............................23 Target specifications ..........................23 Power stage ............................23 4.2.1 System parameter calculation ......................23 4.2.2 Main transformer and resonant network ..................24 4.2.2.1 Transformer turns ratio ......................24 4.2.2.2...
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Page 3: Abstract
Abstract Abstract Infineon's digital platform controller IC (IDP2303(A)) combines the PFC and LLC controls for a high efficiency power supply. This design guide provides detailed calculation examples for major power stage component values as well as the settings for parameters associated with general functions and protection features. -
Page 4: Introduction
Introduction IC Introduction The IDP2303(A) is a multi-mode PFC and LLC controller combined with a floating high side driver and a startup cell. A digital engine provides advanced algorithms for multi-mode operation to support the highest efficiency over the whole load range. A comprehensive and configurable protection feature set is implemented. -
Page 5: Product Highlights
Design guide IDP2303(A) Introduction Symbol Type Function Voltage sensing Pin VS is connected to a high ohmic resistor divider for directly sensing the bus voltage. N.C. — Creepage distance High voltage input Pin HV is connected to the AC input via an external resistor and 2 diodes. There is a 600 V HV startup-cell internally connected that is used for initial VCC charge. -
Page 6: Application
Introduction Application IDP2303 HSGD Vout_2 HSVCC HSGND Vout_1 HBFB MFIO Configuration STANDBY Typical application circuit for a power supply with IDP2303 Figure 2 IDP2303A HSGD HSVCC 85 ... 265 VAC HSGND Gate1 Gate2 PGND HBFB UART Typical application circuit for a power supply with IDP2303A... -
Page 7: Pfc Design
Design guide IDP2303(A) PFC design PFC design Target specifications Table 2 shows the major specifications for the target PFC design. System specification Table 2 Parameter Symbol Value Unit Input voltage minimum in_min Input voltage maximum in_max Nominal bus voltage PFC output power... -
Page 8: Selection Of Power Mosfet
With the CE in 500 V, E6 and P6 family in 600 V, Infineon offers various series with extremely low conduction and switching losses that can make switching applications more efficient, more compact, lighter and cooler. -
Page 9: Mosfet Gate Driving
Design guide IDP2303(A) PFC design 3.2.3 MOSFET gate driving 3.2.3.1 Unique gate drive concept The IDP230x gate drive offers unique features including configurable charge current and output voltage, which offer many advantages (Figure 5): turn-on slope optimization for EMI by configurable current with dpVision ... -
Page 10: Other Design Tips For The Gate Driving Circuit
Design guide IDP2303(A) PFC design 3.2.3.3 Other design tips for the gate driving circuit For some high power SMPS applications, two MOSFETs are often connected in parallel for the PFC converter. In this case, it is recommended to enhance the PFC driving capability by adding an additional circuit close to the PFC MOSFET, as shown in the example in Figure 6. - Page 11 Design guide IDP2303(A) PFC design Current and timing in QR1 operation Figure 7 With the IDP230x, the minimum switching frequency of 25 kHz is guaranteed by the “maximum switching period time-out” approach, which turns the MOSFET on when 40 us of switching period is reached.
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Page 12: Control Parameters And Protections
Design guide IDP2303(A) PFC design �� ∗ (�� − �� ) ∗ �� (265 ∗ √ 2) ∗ (390 − 265 ∗ √ 2) ∗ 0.96 265_���� ������ 265_���� ������_265 �� < = 202 ���� ������ �� ∗ �� ∗ 8��... -
Page 13: Redundant Ovp (Rovp)
Design guide IDP2303(A) PFC design To meet the low standby power consumption requirement, P should be optimized. For example, the Rs_loss expected maximum power loss across these resistors, which occurs at 264Vac, is designed to be less than 15mW under standby operation, ( √... - Page 14 LLC switch continuously so the voltage divider is always in-circuit. However, the conduction loss is only a very small portion of the total loss. With the IDP2303, the MFIO pin is used for PFC output ROVP. As the MCOM pin is a multifunction pin, that is not dedicated for high impedance bus voltage sensing, it must not be connect to the bus voltage divider at start up.
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Page 15: Pfc Zcd Divider Design
Design guide IDP2303(A) PFC design 3.3.3 PFC ZCD divider design To ensure apporiate operation of PFC ZCD detection, the value of R_zcd_h and R_zcd_l, as well as the PFC inductor turn ratio, should be optimized. For PFCZCD pin, there are an internal negative clamping (V... -
Page 16: Over Current Protection(Ocp) Tolerance & Selection Of Current Sense Resistor
Design guide IDP2303(A) PFC design The triggering of OCP protects the PFC inductor from saturation and other components from over current stress. The triggering of OCP does not occur during normal operation. 3.3.4.1 Over Current Protection(OCP) tolerance & selection of current sense... - Page 17 Design guide IDP2303(A) PFC design A spradsheet-based calculation example for selecting the current sense resistor and the OCP tolerance is shown in Figure 12. Application Note Revision 2.0 2017-05-03...
- Page 18 Design guide IDP2303(A) PFC design Accurate calculation of OCP tolerance Figure 12 Application Note Revision 2.0 2017-05-03...
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Page 19: Verification Of Pfc Inductance With Ocp Tolerance
Design guide IDP2303(A) PFC design It can be seen from the calculation that the actual tolerance of current and power can be very high. Methods to reduce tolerances include: Reduce the tolerance of the shunt resistor Reduce the tolerance of the PFC choke ... -
Page 20: Frequency Law
Design guide IDP2303(A) PFC design L,pk L,ave L,pk L,sampled Current and timing in QR2 operation Figure 13 3.3.5.2 Frequency law A frequency law consisting of a maximum switching frequency �� and the minimum switching ���������� frequency �� is defined for the valley selection (QRN). In this way, the switching frequency is limited to ����������... -
Page 21: Setting Of �������� And ��������
Design guide IDP2303(A) PFC design Frequency … ... swmax swmin swDCM Low line swburst High line onDesir ed in,rms Frequency law for selecting operating modes Figure 14 The real-time operation of QRN is executed by the IDP230x hardware peripheral QR-timer. A new switching cycle of QRN operation starts with the N-th valley detection of the sensed inductor voltage or with the end of the maximum switching period, whichever occurs first. -
Page 22: Ac Brown-In & Out
Design guide IDP2303(A) PFC design 3.3.6 AC brown-in & out The PFC brown-in & out protections prevent the system from starting up or operating at very low input voltage outside the designed operating range. For a system without input brown-in & out protection, the boost converter may draw a higher current from the mains at a given output power which may lead to overheating of the MOSFET and boost diode. -
Page 23: Llc Design
Design guide IDP2303(A) LLC design LLC design Target specifications The LLC target specifications are summarized in Table 6. Design parameters for the LLC design Table 6 Parameter Symbol Value Unit Bus bulk capacitor 68 x 2 µF bulk Output voltage... -
Page 24: Main Transformer And Resonant Network
Design guide IDP2303(A) LLC design 4.2.2 Main transformer and resonant network 4.2.2.1 Transformer turns ratio In this design, an integrated transformer is considered, where the leakage inductance is used as a series inductor, while the magnetizing inductor is used a shunt inductor. The all-primary-referred model of the transformer is shown in Figure 17, where ��... -
Page 25: Equivalent Circuit And Resonant Network
Design guide IDP2303(A) LLC design The maximum voltage gain �� required is during conditions of full load operation at minimum input ������ voltage �� , which can be calculated as: ������_������ �� ������_������ �� �� 0.94 = 1.08 ������ ������... - Page 26 Design guide IDP2303(A) LLC design Voltage gain �� Vs normalized frequency �� Figure 19 The curve where ���� = 0.75 can achieve the required peak gain, �� , which is �� , �� = �� ∗ 1.05 = ���� ������...
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Page 27: Calculation Of Transformer Turn Ratio
Design guide IDP2303(A) LLC design 4.2.2.3 Calculation of transformer turn ratio In the above section, the actual minimum frequency �� has been calculated as 87 kHz. ������ Flux density swing Figure 20 According to the flux density swing illustrated in Figure 20, the voltage across the primary winding can be calculated as ��... -
Page 28: Selection Of Resonant Factor M
Design guide IDP2303(A) LLC design 4.2.2.4 Selection of resonant factor m Numerous factors come into play while considering the value of the resonant factor ��. In order to achieve the highest efficiency possible, the magnetizing inductance ��... -
Page 29: Power Mosfet Selection
With the CE in 500 V, E6 and P6 family in 600 V, Infineon offers series with extremely low conduction and switching losses and can make switching applications more efficient, more compact, lighter and cooler. -
Page 30: Control Parameters And Protections
Design guide IDP2303(A) LLC design �� �� �� �� ∗ 3 = 2.36 �� ��_������_12 �� �� �� �� �� ∗ 3.5 = 2.75 �� ��_������_24 �� Considering the voltage overshoot due to the stray inductance, 60 V/20 A and 100 V/30 A Schottky diodes are selected as the rectifier diodes for the 12 V and 24 V channels, repectively. -
Page 31: Xd835;�_������������ And ��_������������
Design guide IDP2303(A) LLC design (heavy load). Therefore, the VCO in the area II has a much better frequency resolution than in the area I and III. In this way, fine frequency resolution around the nominal operating point V is realized, while a wide... -
Page 32: Xd835;�_���������� ∶ ��_���������� (Light Load) : ��_���&#X
Design guide IDP2303(A) LLC design With some interpolation, the frequency value at 0 V is calculated to be around 170 kHz. 4.3.1.3 �� : �� (light load) : �� ∶ �� (heavy load) _���������� _���������� _���������� _���������� These two points define the mid-frequency range of VCO, which covers the normal operation ranges from very light load to full load at nominal bus voltage. -
Page 33: Dead Time
Design guide IDP2303(A) LLC design The current sense and OCP tolerance calculation of the LLC is similar to the PFC as described in section 3.3.2. Considering the parameters that affect OCP tolerance, a fast and simple way to obtain a value for the current sense resistor is: ��... -
Page 34: Llc Regulation Loop
Design guide IDP2303(A) LLC design Δ�� �� ���� = − Δ�� �� ℎ������ ���� Note: Similar to the LLC transfer function, the VCO transfer function depends on the VCO steady-state switching period, �� . Usually, the VCO transfer function has a very high gain in order to cover the whole ����... - Page 35 Design guide IDP2303(A) LLC design ( �� ) �� 1 + �� ( �� ) + �� �� �� + �� �� + �� �� �� �� �� �� ��1 �� = 1 + �� �� �� �� �� ��...
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Page 36: General Features And System Design Considerations
Design guide IDP2303(A) General features and system design considerations General features and system design considerations VCC supply and high voltage startup cell 5.1.1 Start up HV pin is connected to the AC input voltage via a resistor and two diodes. There are two main functions supported at HV pin: VCC startup and direct AC detection. -
Page 37: Selection Of Vcc Capacitor
Design guide IDP2303(A) General features and system design considerations 5.1.2 Selection of VCC capacitor According to the start-up procedure described above, when setting the value of the VCC capacitor, the following conditions must be considered: The requirement for the start-up time of the IC (��... -
Page 38: Llc High-Side Vcc (Hsvcc) Cap
Design guide IDP2303(A) General features and system design considerations LLC High-side VCC (HSVCC) cap To optimize LLC switching behaviour during start-up and burst mode operation, HSVCC cap is targeted to reach its turn-on threshold within the first low-side gate pulse. Thus, its capacitance can be calculated as: ��... - Page 39 Design guide IDP2303(A) General features and system design considerations If the UART (MCOM) voltage is at a high level, it is counted as “1”; if at a low level, “0”. The duration of each bit is 36 us. This may vary with different firmware settings.
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Page 40: Tips On Pcb Layout
Tips on PCB layout Tips on PCB layout Infineon's digital platform controller IC integrates the PFC and LLC converter controllers in one package. Therefore, it is a good idea to physically separate the PFC and LLC circuits on the PCB to avoid mutual interference. -
Page 41: Pfc Zcd Signal Detection Circuit
Design guide IDP2303(A) Tips on PCB layout (recommended value 1 nF) and HBFB pin (recommended value 4.7 nF) shall be mounted as close as possible to the controller IC, while their ground shall be connected to the IC ground directly. All these connection traces shall be as short as possible. -
Page 42: Minimum Current Flowing Loop Area
Design guide IDP2303(A) Tips on PCB layout For example, the PFC ZCD and HBFB pin related PCB tracks shall be far away from these high voltage and high dv/dt pins. Minimum current flowing loop area IDP2303 HSGD Vout_2 HSVCC HSGND... -
Page 43: Other Considerations
Design guide IDP2303(A) Tips on PCB layout Spark gaps for lightning surge test Figure 30 In addition, a ferrite bead (shown red in Figure 31) can be added between the bus track and the upper resistor in the bus voltage divider. -
Page 44: Usage Of Dpvision
2) Unzip the IDP2303_addon_generator.zip file and install add ons folders, by double clicking on IDP2303_addon_generator.msi file. 3) Step 2 above will copy and paste, documents, images & parameters to C:\Users\<Login>\Infineon Technologies AG\.dp vision 4) Connect the dpIFGen2 interface board using the USB cable provided to a laptop USB port and open the dpVision GUI by double clicking on “dpVision.exe”... - Page 45 Design guide IDP2303(A) Usage of dpVision dplFGen2 interface board (side view) Figure 34 7) Open“idp2303_configuration_dpVision2.0.8.0_dpIfGen2FW240_appFwV0322_Rev_0.8_embedded_hi sense.csv” using menu File Open browse to folder \..\.dpVision\Parameters 8) Press the “Power Device On/Off” button “Device status” should turn green Power device On/Off button and device status Figure 35 9) Press the “Test configuration set”...
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Page 46: Parameter Setting With Dpvision
Design guide IDP2303(A) Usage of dpVision 13) For the setting of parameters with dpVision, please press “Help” for the dpVision user manual. Help button Figure 38 Parameter setting with dpVision Table 8-10 list up all the configurable parameters by customers through dpVision. The setting of the major parameters has been explained in detail in this design guide. - Page 47 Design guide IDP2303(A) Usage of dpVision Parameter symbol Parameter description Default Range Unit PFC max on time 0.016 ~ 63.98 µs _OnMaxPFC Refer to 5.4.6 for limits LLC Parameters Table 10 Parameter symbol Parameter description Default Range Unit LLC GD1 drive voltage 10.5...
- Page 48 Design guide IDP2303(A) Usage of dpVision Parameter symbol Parameter description Default Range Unit Slope LLC initial slope during soft start 0.85 0.0157 ~ 3.984 µs/0.5 ms _TCO_init Slope LLC min slope during soft start 0.36 0.0157 ~ 3.984 µs/0.5 ms...
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Page 49: References
Design guide IDP2303(A) References References [1] Infineon technologies: IDP2303 Digital Multi-Mode PFC + LLC combo controller, Datasheet Rev. V1.0, 2016-11-21 [2] Infineon technologies: IDP2303A Digital Multi-Mode PFC + LLC combo controller, Datasheet Rev. V1.0, 2016-11-21 [3] Infineon Technologies: CrCM Boost PFC Converter Design, Design Note, DN 2013-10 V1.0 January 2013. - Page 50 Trademarks of Infineon Technologies AG AURIX™, C166™, CanPAK™, CIPOS™, CoolGaN™, CoolMOS™, CoolSET™, CoolSiC™, CORECONTROL™, CROSSAVE™, DAVE™, DI-POL™, DrBlade™, EasyPIM™, EconoBRIDGE™, EconoDUAL™, EconoPACK™, EconoPIM™, EiceDRIVER™, eupec™, FCOS™, HITFET™, HybridPACK™, Infineon™, ISOFACE™, IsoPACK™, i-Wafer™, MIPAQ™, ModSTACK™, my-d™, NovalithIC™, OmniTune™, OPTIGA™, OptiMOS™, ORIGA™, POWERCODE™, PRIMARION™, PrimePACK™, PrimeSTACK™, PROFET™, PRO-SIL™, RASIC™, REAL3™, ReverSave™, SatRIC™, SIEGET™, SIPMOS™, SmartLEWIS™, SOLID FLASH™, SPOC™, TEMPFET™,...