Applications ............................................................................................................................................. 7

1.2

Control registers and PMBus commands ............................................................................................... 7

1.3

Naming conventions ............................................................................................................................... 8

1.3.1

Loops and phases ............................................................................................................................... 8

1.3.2

Symbols and abbreviations ............................................................................................................... 8

1.3.3

Binary number format convention .................................................................................................. 11

1.4

Structure of this document ................................................................................................................... 12

Voltage sense ........................................................................................................................ 13

2.1

VS module configuration ...................................................................................................................... 14

2.2

Voltage sense analog-to-digital converter ........................................................................................... 17

2.2.1

Analog front end and front-end compensation .............................................................................. 18

2.2.2

Tracking ADC .................................................................................................................................... 18

2.3

Voltage sense processor ....................................................................................................................... 20

2.3.1

Output voltage processing .............................................................................................................. 20

2.3.2

Rectification voltage processing ..................................................................................................... 21

2.3.2.1

RECT

2.3.2.2

RECT

2.3.2.3

Deglitcher .................................................................................................................................... 23

2.3.2.4

RECT

2.3.2.5

2.3.2.6

RECT

2.3.2.7

Same cycle response................................................................................................................... 26

2.3.2.8

RECT

2.3.3

processing ................................................................................................................................... 28

User Manual

www.infineon.com/xdpp1100

timing for single PWM signal ............................................................................................... 22

watchdog timer ................................................................................................................... 23

timing for two PWM signals ................................................................................................ 24

transient response ................................................................................................................. 24

start-up programming ........................................................................................................ 25

delay counters ..................................................................................................................... 27

Please read the Important Notice and Warnings at the end of this document

page 1 of 562

V 1.0

2021-08-25

Table of Contents

Summary of Contents for Infineon XDPP1100

Page 1: Table Of Contents
About this document Scope and purpose This document focuses on the XDPP1100 hardware (HW) implementation, and it can be used as a reference document for firmware (FW) developers. The aim is to describe high-level functions and provide block diagram illustrations of the implemented HW. Furthermore, the purpose is to demonstrate how the XDPP1100 interacts with external components within applications, and show how the sensed information from the analog input pins is processed by the HW.
Page 2 XDPP1100 technical reference manual Digital power controller Table of contents VS registers ............................28 Current sense (IS) ........................37 Current sense module configuration ....................38 Current sense analog to digital converter .................... 40 3.2.1 Current sense analog front end ....................... 41 3.2.2...
Page 3 XDPP1100 technical reference manual Digital power controller Table of contents 6.2.1 Output voltage target computation ....................113 6.2.2 Input voltage source select and computation ................114 6.2.3 Override and adjustment options for FF ..................115 Control mode selection – peak current mode ................... 117 Open sense fault detection .........................
Page 4 XDPP1100 technical reference manual Digital power controller Table of contents 9.1.5 Power warnings ..........................238 9.1.6 Temperature faults ........................239 9.1.7 Current sharing fault ........................240 9.1.8 warning ......................... 240 OUT_MAX OUT_MIN 9.1.9 Sync fault ............................240 9.1.10 faults ........................240...
Page 5 XDPP1100 technical reference manual Digital power controller Table of contents 14.1 Multipurpose digital IO muxing ......................314 14.2 Digital input priority ..........................316 14.3 GPIO deglitch ............................316 14.4 Digital IO buffer programming ......................317 14.5 IO muxing registers ..........................317 Central processing unit subsystem ..................
Page 6 XDPP1100 technical reference manual Digital power controller Table of contents 15.10 PMBus module ............................. 499 15.10.1 PMBus clock scheme ........................501 15.10.2 Interrupt generation ........................501 15.10.3 PMBus operation ..........................501 15.10.3.1 Configuration ..........................502 15.10.3.2 Write transaction ........................503 15.10.3.3...
Page 7: Introduction
PMBus commands enable the end user to customize system applications. Access to the register map is supported by the XDPP1100 GUI. A full listing of the control registers and their descriptions can be found in the XDPP1100 register descriptions document. Registers associated with a HW function discussed in this document are also described at the end of the relevant chapter.
Page 8: Naming Conventions
With multi-config, the XDPP1100 controllers are capable of storing up to 16 configurations, and these 16 configurations may be reprogrammed once if needed. The controller identifies the proper configuration to load based on information stored in the configuration;...
Page 9 XDPP1100 technical reference manual Digital power controller Introduction High-pass filter Hardware IADC Current sense analog-to-digital converter IBAL Current balance Input output Integrated power stage IS AFE Current sense analog front end ISHARE Current sharing Current sense processor Leading edge Low-pass filter...
Page 10 BVREF_BVRREF XDPP1100 input pin BVSEN_BVRSEN XDPP1100 input pin Output voltage, Loop 1 BIREF XDPP1100 input pin for current sensing BISEN XDPP1100 input pin for current sensing Capacitor Output filter capacitor Frequency of the compensator zero Frequency of the compensator pole...
Page 11: Binary Number Format Convention
1.3.3 Binary number format convention Throughout this document in figures and text and in other XDPP1100-related documentation binary numbers are often referred to as having the form Ux.y for unsigned numbers or Sx.y for signed numbers. The definitions of these references are given below.
Page 12: Structure Of This Document
Introduction Structure of this document The remaining document is divided into 14 chapters, which describe the implemented HW of XDPP1100. Each chapter presents an independent part of the HW functionality. At the end of each chapter, relevant registers and PMBus commands related to the described functionality are summarized. Throughout every chapter, the recommended register programming as well as PMBus commands are provided.
Page 13: Voltage Sense
(VSP) in detail. In addition, the user-programmable settings for configuring the features of the sensed voltages are described and relevant registers provided. The XDPP1100 controller has three following analog input pin pairs for voltage sensing: VSEN/VREF, for V sensing •...
Page 14: Vs Module Configuration
Digital power controller Voltage sense VS module configuration The XDPP1100 controller contains three VS modules, VS0, VS1 and VS2. Each of them is connected to the above- mentioned analog input pin pairs as follows: Input pin pair VSEN/VREF is connected to VS0 •...
Page 15 XDPP1100 technical reference manual Digital power controller Voltage sense Loop 0 V telemetry, faults VSEN VSP0 PID0 VREF Loop 0 V VRSEN VSP1 telemetry, RECT VRREF faults Phase 1 (ISEN) current sense, flux balance Phase 2 BVRSEN (BISEN) VSP2 RECT...
Page 16 XDPP1100 technical reference manual Digital power controller Voltage sense Loop 0 V telemetry, faults VSEN VSP0 PID0 VREF Loop 0/1 V VRSEN or V VSP1 telemetry, RECT VRREF faults Phase 1/2 current sense BVSEN VSP2 PID1 BVREF Loop 1 V...
Page 17: Voltage Sense Analog-To-Digital Converter
XDPP1100 technical reference manual Digital power controller Voltage sense VSADC VSEN Tracking vout VREF vsadc Figure 5 VS module block diagram while processing V VSADC vrs_track vrs_hold V(R)SEN vout vsadc Tracking V(R)REF vrect vrs_comp vrs_comp_ref Figure 6 VS module block diagram while processing V...
Page 18: Analog Front End And Front-End Compensation
It compares the differential voltages at the input and output of the AFE and compensates for the difference at the reference path unity gain buffer via a 6-bit DAC. For the FEC module, it is strongly recommended to use the factory settings, selected automatically when programming via the XDPP1100 GUI (although the FEC module provides some programmability).
Page 19 1 is recommended. If automatic step size is programmed by setting vsX_step_en = 0, the XDPP1100 automatically selects the step size between 1 and 7 based on the perceived distance from the input voltage.
Page 20: Voltage Sense Processor
XDPP1100 technical reference manual Digital power controller Voltage sense Voltage sense processor The VSP receives the tracking ADC output (the digitized sensed voltage) as its input. Depending on the assignment of the specific module, it processes the incoming data in order to produce: Output and error voltages •...
Page 21: Rectification Voltage Processing
XDPP1100 technical reference manual Digital power controller Voltage sense It should be noted that the VCM output, V , has higher resolution than the V , thus resulting in an error control voltage with the resolution of 156.25 µV. Programmable clamp (register vsp_verrn_clamp_thresh) is applied to limit the maximum error seen by the compensation filter.
Page 22 The measurement cycle timing is initiated when the primary-side PWM signal goes high. At this point, a timer is started and the XDPP1100 waits for a high transition on the VRSEN or BVSEN_BVRSEN input pin. The rising edge of the rectified voltage is detected via a comparator, vrs_comp. It is clocked at 200 MHz and has a programmable threshold via register vrs_cmp_ref_sel.
Page 23: Deglitcher
XDPP1100 technical reference manual Digital power controller Voltage sense 2.3.2.2 watchdog timer RECT For correct V measurement, the input voltage needs to have certain minimum value in order to trip the RECT vrs_comp comparator. Therefore, a watchdog timer (WDT) is started on the PWM rising edge. This timer monitors the quality of the V signal.
Page 24: Vin
12), utilized RECT typically in the ACF converter topology. However, in the bridge topologies, two PWM signals operate on opposite cycles, referred to here as even and odd. The XDPP1100 measures and stores the PWM signals separately, as shown in Figure...
Page 25: Vrect
XDPP1100 technical reference manual Digital power controller Voltage sense VRSEN Hold Time Tracking Window Tracking ADC DAC Output Figure 14 sense transient RECT 2.3.2.6 start-up programming RECT At start-up, prior to the first PWM pulse, there is no V pulse on the secondary to be measured. Therefore, in...
Page 26: Same Cycle Response
XDPP1100 technical reference manual Digital power controller Voltage sense The terms utilized in the equations are defined as follows: Vin_init is the initial input voltage (i.e., 48 V for a 36 V to 72 V system), and it must be greater than the PMBus •...
Page 27: Vrect Delay Counters
XDPP1100 technical reference manual Digital power controller Voltage sense VRSEN Tracking Window Same Cycle Window vrect output same cycle disabled vrect output same cycle enabled Figure 16 Same cycle mode 2.3.2.8 delay counters RECT The V processing function includes a set of counters. They measure the delay between:...
Page 28: Vin
XDPP1100 technical reference manual Digital power controller Voltage sense VRSEN vrs_comp_ref vrs_comp vspX_cnt_srf2vrsr vspX_cnt_vrscomp_e vspX_cnt_vrsf2srr vspX_cnt_srf_avg vspX_cnt_vrscomp_o vspX_cnt_srr_avg Figure 17 Dead time counters If the counter detects the incoming waveform edges in the incorrect order, it will indicate this through the...
Page 29 XDPP1100 technical reference manual Digital power controller Voltage sense Peripheral Field name Access Address Bits Description 1: Use vs0_step[2:0] (recommended for VSEN) analog vs1_step 7000_0400h [6:4] VS1 (VRSEN) tracking loop step size when automatic step size disabled. Recommended setting is 1 for highest resolution.
Page 30 XDPP1100 technical reference manual Digital power controller Voltage sense Peripheral Field name Access Address Bits Description 7000_1000h (BVSEN) vsen vsp_mode_fe_1p25m 7000_0800h [17] (VSEN) Defines VS FEC DAC LSB weight. 7000_0C00h 0: 0.625 mV (VRSEN) 1: 1.250 mV 7000_1000h (BVSEN) vsen...
Page 31 XDPP1100 technical reference manual Digital power controller Voltage sense Peripheral Field name Access Address Bits Description on the rising edge of the PWMs indicated in ceX_on_mask0 and ceX_on_mask1 (where X = 0, 1). When the timer exceeds this threshold the V...
Page 32 XDPP1100 technical reference manual Digital power controller Voltage sense Peripheral Field name Access Address Bits Description 2: 16 samples 3: 32 samples common VRS comparator threshold select. vrs_cmp_ref_sel 7000_3018h [27] This threshold is shared by the VRSEN and BVRSEN sense paths.
Page 33 XDPP1100 technical reference manual Digital power controller Voltage sense Peripheral Field name Access Address Bits Description will begin vrs_meas_start_thr samples after entering tracking mode for faster FF response. Otherwise V is only updated on RECT the falling PWM edge. 0: Same cycle mode disabled...
Page 34 XDPP1100 technical reference manual Digital power controller Voltage sense Peripheral Field name Access Address Bits Description common vsp1_cnt_srf2vrsr 7000_3060h [23:16] Non-averaged VRSEN SR FET falling edge to VRS comp rising edge measurement result. LSB = 5 ns, range = 0 to 1275 ns...
Page 35 XDPP1100 technical reference manual Digital power controller Voltage sense Peripheral Field name Access Address Bits Description common vsp2_cnt_vrsf2srr 7000_3068h [31:24] Non-averaged BVRSEN VRS comp falling edge to SR FET rising edge measurement result. LSB = 5 ns, range = 0 to 1275 ns...
Page 36 XDPP1100 technical reference manual Digital power controller Voltage sense Peripheral Field name Access Address Bits Description when sharing Loop 0 V sense RECT 6: VRSEN: non-pulsed/primary V sense 7: BVSEN_BVRSEN, non- pulsed/primary V sense User Manual 36 of 562 V 1.0...
Page 37: Current Sense (Is)
This chapter describes the current sense module and its submodules in detail. In addition, the user- programmable settings for configuring different current sense features are described and relevant registers provided. Different applications require different current information. The XDPP1100 controller supports both primary and secondary-side current sensing in order to obtain information on I and I , respectively.
Page 38: Current Sense Module Configuration
PCMC FBFB rectifier with primary and secondary current sensing Current sense module configuration The XDPP1100 controller contains two current sense modules which are connected to the analog input pins ISEN/IREF and BISEN/BIREF. A simplified block diagram of these current sense modules is shown in...
Page 39 The current sense information is provided to ISEN/IREF and BISEN/BIREF input pins as a voltage that is proportional to the sensed current. There are different methods to obtain the current information, depending on the application requirements. For the XDPP1100 controller, the supported current sensing methods are: Shunt resistor •...
Page 40: Current Sense Analog To Digital Converter
The main requirement for using the integrated current sensing of IPS is to have 1.2 V reference voltage for current sense. An example of supported integrated power stage is Infineon’s IR3555A. Depending on the selected sensing method, the IADC resolution as well as the reference level need to be adjusted, as will be discussed in the following sections.
Page 41: Current Sense Analog Front End
XDPP1100 technical reference manual Digital power controller Current sense (IS) error tracking (B)ISEN DELAY pwm_state (B)IREF (from Dig PWM) quantizer Ltrace 9.25 bits compensation synth_i Analog front end (to ISP, Dig PWM) slope estimation vrect vout Current estimator Figure 20 Simplified block diagram of the IADC 3.2.1...
Page 42: Current Estimator
XDPP1100 technical reference manual Digital power controller Current sense (IS) based gain stage or IPS. All other applications require the reference level to be ground, except IPS. High-gain mode refers to smaller LSB size and finer resolution. This implies higher noise susceptibility, whereas low-gain mode means higher LSB size and lower noise sensitivity.
Page 43: Pwm State
3.2.2.1 PWM state The XDPP1100 controller continuously predicts the current phase and ripple based on the state of the PWM pulse. Therefore, the PWM state is critical to both slope estimation and error tracking, because it is used to determine the equation for voltage across the inductor in order to estimate the inductor current slope.
Page 44 The PWM state programming is described below in more detail through various topology examples. The XDPP1100 GUI can be used to automatically program the on-/off-states, based on topology selection and PWM mapping.
Page 45 XDPP1100 technical reference manual Digital power controller Current sense (IS) Figure 22 Buck topology FET naming Table 7 Buck topology PWM state programming example FET PWM Register programming Register value output PWM1 Set bit field values corresponding PWM1 to 1 and other bit...
Page 46 XDPP1100 technical reference manual Digital power controller Current sense (IS) Figure 24 HBCT topology FET naming Table 9 HBCT PWM state programming example Register programming Register value output PWM1 Set bit field values corresponding PWM1 to 1 and other bit fields...
Page 47 XDPP1100 technical reference manual Digital power controller Current sense (IS) Table 10 HBCD PWM state programming example Register programming Register value output PWM1 Set bit field values corresponding PWM1 to 1 and other bit fields ceX_on_mask0 = to 0 in ceX_on_mask0...
Page 48: Slope Estimator
, depending on RECT the topology and the PWM state. The XDPP1100 controller supports inductor voltage equations for buck- derived, as well as boost and buck-boost topologies. The topology is selected via register ceX_topology. The supported topologies and their corresponding inductor voltage equations for different PWM states are shown...
Page 49 In addition to the inductance tolerance, the inductor value may vary with the respect to the current. This variation is typically non-linear, and the XDPP1100 provides a linear correction as illustrated in Figure Register ceX_dt_l_slope defines the L slope dependence on the current. As illustrated in the figure, the...
Page 50 XDPP1100 technical reference manual Digital power controller Current sense (IS) Therefore, assuming L is the inductance at zero current, the parameter ceX_dt_l_slope is computed according to Equation (3.5). �� (3.5) ��_��_��_�� = �� (2 ∗ (( ) − 1) ∗...
Page 51: Error Tracking
XDPP1100 technical reference manual Digital power controller Current sense (IS) SECONDARY PRIMARY Figure 28 Primary-side and secondary-side current waveforms While determining the slope for the slope estimator, besides L the magnetizing inductance must also be considered. Therefore, Equation (3.3) is modified to consider the transformer turns ratio by computing the parameter kslope_real according to Equation (3.6).
Page 52: Trace Inductance Of The Pcb Current Sensing
XDPP1100 technical reference manual Digital power controller Current sense (IS) ceX_ktrack_on, for on-state • ceX_ktrack_off, for off-state • ceX_ktrack_hiz, for high impedance state • In addition, register ceX_iterm defines an integral coefficient which is applied across all states if set to a non- zero value.
Page 53: Adc Codes To Amps
XDPP1100 technical reference manual Digital power controller Current sense (IS) Tracking isp_track_fault_en fault isp_err_ratio_sel is_track_fault (To fault block) ierr (from AFE quantizer) Peak ce_current_limit pcl_fault current limit (To digital PWM) Short circuit isp_scp_thresh scp_fault fault (To fault block) Negative isp_ncl_thresh...
Page 54: Peak Current Limiting
XDPP1100 technical reference manual Digital power controller Current sense (IS) The selection over which switching cycle the current is averaged is done via register isp_fsw_sync_sel. The user can decide whether the switching cycle is averaged over Loop 0 or Loop 1. The averaged current is further processed downstream in the telemetry and fault blocks.
Page 55: Error Tracking Fault Detection
XDPP1100 technical reference manual Digital power controller Current sense (IS) 3.3.5 Error tracking fault detection Error tracking fault detects the inability of the IADC tracking mechanism to track the input. This fault typically indicates a board-level problem, for instance one of the ISEN/IREF inputs is not connected properly. The tracking fault detection is enabled by setting ispX_track_fault_en to 1.
Page 56: Current Sense Registers
XDPP1100 technical reference manual Digital power controller Current sense (IS) Lower-valued settings of ispX_err_ratio_sel are very sensitive and may cause false fault declaration, particularly in noisy current sense environments. Therefore, it is recommended to use only the higher-valued ispX_err_ratio_sel settings of 6 or 7.
Page 57 XDPP1100 technical reference manual Digital power controller Current sense (IS) Peripheral Field name Access Address Bits Description current sense and for the boost topology. LSB = 1/16 V/V, range = 0 to 15/16 V/V ce_ktrack_on 7000_2400h [11:8] Current sense tracking gain in the...
Page 58 XDPP1100 technical reference manual Digital power controller Current sense (IS) Peripheral Field name Access Address Bits Description (e.g., primary FETs in a bridge topology). In bridge topologies there are two on-states per switching cycle. ce_on_mask0 defines the first (even) on-state and ce_on_mask1 defines the second (odd) on-state.
Page 59 XDPP1100 technical reference manual Digital power controller Current sense (IS) Peripheral Field name Access Address Bits Description Q2, Q4 Buck HSFET isen ce_dt_l_slope 7000_2404h [31:24] Defines the slope of the output (ISEN) inductance dependence on current. 7000_2804h Although actual inductor variation...
Page 60 XDPP1100 technical reference manual Digital power controller Current sense (IS) Peripheral Field name Access Address Bits Description && !ON where [0] corresponds to PWM1, [11] corresponds to PWM12 and on is defined by ce_on_mask0 and ce_on_mask1 Secondary topology set: ce_off_mask0 bits corresponding...
Page 61 XDPP1100 technical reference manual Digital power controller Current sense (IS) Peripheral Field name Access Address Bits Description 7000_2808h Computed as follows: (BISEN) ce_ltrace = L / (R * dt) trace trace where = parasitic trace inductance trace being compensated = current sense trace...
Page 62 XDPP1100 technical reference manual Digital power controller Current sense (IS) Peripheral Field name Access Address Bits Description ADC feedback if the falling PWM edge causes noise on the current sense signal. LSB = 40 ns, range = 0 to 280 ns...
Page 63 XDPP1100 technical reference manual Digital power controller Current sense (IS) Peripheral Field name Access Address Bits Description 4: V (VRSEN/VRREF) RECT 5: BV (BVRSEN/BVRREF) RECT 6: pid_ff_vrect_override 7: PRISEN CE1 (BISEN): 0: V (VRSEN/VRREF) RECT 1: BV (BVRSEN/BVRREF) RECT 2: pid_ff_vrect_override...
Page 64: Current Sense Pmbus Commands
XDPP1100 technical reference manual Digital power controller Current sense (IS) Peripheral Field name Access Address Bits Description isp_err_ratio_sel 7000_2414h [3:1] Current sense tracking fault error isen (ISEN) ratio select. 7000_2814h 0: 4 (11.1 percent threshold) (BISEN) 1: 8 (20.0 percent threshold) 2: 12 (27.3 percent threshold)
Page 65 XDPP1100 technical reference manual Digital power controller Current sense (IS) Command name Access Length Address Bits Description [15:0] Current sense APC. MFR_IOUT_APC Word Linear11 format with suggested exponent -8 or -9 depending on magnitude. Unit = amps User Manual 65 of 562 V 1.0...
Page 66: Telemetry Sense
32. The input signals are assigned to the following XDPP1100 input pins: PRISEN, IMON, TSEN, BTSEN, XADDR1 and XADDR2. If a pin is not used for the associated named function, the input is available to be used as a general-purpose ADC input.
Page 67 XDPP1100 technical reference manual Digital power controller Telemetry sense mux2_sel 0.6 V PRISEN IMON 2 MHz LPF (A)TSEN 2 MHz LPF MUX2 TSADC Input BTSEN 2 MHz LPF XADDR1 XADDR2 mux1_sel Int. Temp 60k Res 2 MHz LPF MUX1 Figure 32...
Page 68 XDPP1100 technical reference manual Digital power controller Telemetry sense Table 20 MUX2 selection ts_muxctrl2 MUX2 output 0.6 V reference (test only) PRISEN IMON ATSEN BTSEN XADDR1 XADDR2 MUX1 output In addition to ts_muxmode, ts_muxctrl1 and ts_muxctrl2, the following registers are required to enable an...
Page 69: Telemetry Sense Current Dac
XDPP1100 technical reference manual Digital power controller Telemetry sense ts_muxctrl1 0 (ITSEN) ts_muxctrl2 1 (PRISEN) 7 (MUX1) 6 (XADDR2) clk_25mhz clk_tsadc sample sample sample PRISEN ITSEN convert PRISEN ts_adc[9:0] ATSEN ADC output (mux_mode=7) PRISEN ADC output prisen_adc[13:0] Previous PRISEN ADC output...
Page 70: Sequencer
XDPP1100 technical reference manual Digital power controller Telemetry sense clk_25mhz clk_tsadc ts_mux1_sel[1:0] mux1_sel[1:0] ts_mux2_sel[2:0] mux2_sel[2:0] ts_muxmode[2:0] prisen_update Sequencer imon_update atsen_update btsen_update itsen_update xaddr1_update xaddr2_update demux_sel[2:0] prisen_adc[13:0] imon_adc[13:0] atsen_adc[13:0] Gain and offset btsen_adc[13:0] ts_adc[9:0] correction itsen_adc[13:0] xaddr1_adc[13:0] xaddr2_adc[13:0] vin[11:0] compute Int. temp...
Page 71: Internal Temperature (Itsen) Computation
U8.4 S9.4 U8.4 U10.2 Figure 35 computation 4.4.4 Internal temperature (ITSEN) computation The XDPP1100 internal temperature is computed from ADC codes based on the following registers and according to Equation 4.2: ptat_0c_code • ptat_pwl_slope • ptat_temp_trim • ��. �� = ( �� − ��_0��_�� ) * ��_��_�� + ��_��_��...
Page 72: X-Valent Measurement
XDPP1100 technical reference manual Digital power controller Telemetry sense ptat_temp_trim = 0 • A register, temp_min, is provided to clamp the minimum computed internal temperature. The default setting for this parameter is -128°C. After the clamp, the internal temperature is low-pass filtered at a fixed BW of 0.48 kHz.
Page 73: Telemetry Sense Registers
XDPP1100 technical reference manual Digital power controller Telemetry sense XADDR resistance (Ω) 16-value XADDR decode 4700 6070 8000 10200 13200 17200 22470 29200 39000 56000 The decoded results are available on read-only registers tlm_xaddr1_pinset and tlm_xaddr2_pinset. Alternatively, a user-defined FW patch may be used to measure the XADDR1, two-resistor programming. The...
Page 74 XDPP1100 technical reference manual Digital power controller Telemetry sense Peripheral Field name Access Address Bits Description IMON measurement will occur, even if selected by ts_muxmode and ts_muxctrl2. 0: Disabled 1: Enabled tsen atsen_meas_en 7000_4C00h TSADC ATSEN input measurement enable. When enabled, the TSADC...
Page 75 XDPP1100 technical reference manual Digital power controller Telemetry sense Peripheral Field name Access Address Bits Description temperature sense element. The current source may be disabled to use the BTSEN input as a general- purpose ADC input. 0: Disabled 1: Enabled...
Page 76 XDPP1100 technical reference manual Digital power controller Telemetry sense Peripheral Field name Access Address Bits Description measure the internal temperature of the controller. 0: ITSEN 1: 60 K resistor (test only) 2: XADDR1 filtered 3: XADDR2 filtered tsen ts_muxctrl2 7000_4C00h [19:17] TSADC MUX2 input source select.
Page 77 XDPP1100 technical reference manual Digital power controller Telemetry sense Peripheral Field name Access Address Bits Description tsen ptat_0c_code 7000_4C08h [10:0] ITSEN 0°C code. Internal temperature computed as: Int. temp. = (ADC - 0C_code) * pwl_slope + temp_trim LSB = 0.25 ADC codes, range = 0.0 to 511.75 ADC codes...
Page 78 XDPP1100 technical reference manual Digital power controller Telemetry sense Peripheral Field name Access Address Bits Description LSB = 0.0625 ADC code, range = 0.0 to 1023.9375 ADC codes tsen ts_btsen_adc 7000_4C20h [13:0] Gain and offset corrected BTSEN TSADC output. LSB = 0.0625 ADC code, range = 0.0 to 1023.9375 ADC codes...
Page 79 XDPP1100 technical reference manual Digital power controller Telemetry sense Peripheral Field name Access Address Bits Description output 1: Use idac_fw_frc User Manual 79 of 562 V 1.0 2021-08-25...
Page 80: Voltage Control
XDPP1100 technical reference manual Digital power controller Voltage control Voltage control This chapter introduces the voltage control module and its submodules, as well as describing the relevant registers and PMBus commands. The purpose of the voltage control module is to set the control or reference voltage with respect to which the output voltage is regulated.
Page 81: Pmbus Commands To Hw Parameters
XDPP1100 technical reference manual Digital power controller Voltage control PMBus commands to HW parameters The voltage control module implements the PMBus reference voltage generation model from a high-level perspective, as described in the PMBus Specification, Part II, Revision 1.3.1, section 9.2 and shown in...
Page 82 XDPP1100 technical reference manual Digital power controller Voltage control A simplified block diagram of the ramp generator is shown in Figure 40, where the target output voltage consists of the sum of the following registers: vc_vramp_target, which is the VSEN referenced target voltage computed by FW from PMBus commands •...
Page 83: Interrupts
XDPP1100 technical reference manual Digital power controller Voltage control Care should be taken if using this feature during active regulation, because the power stage may not be capable of tracking large steps in the target voltage without significant overshoot/undershoot. The ramp generator also provides the following read-only status registers: vc_vcontrol_at_target indicates vcontrol_ramp is at the target voltage and is no longer slewing •...
Page 84: Droop Voltage Computation
XDPP1100 technical reference manual Digital power controller Voltage control VOUT_MAX MFR_RDROOP_RLL_NEG VOUT_DROOP (SEG1) VOUT_COMMAND MFR_RDROOP_RLL_SEG2 MFR_RDROOP_RLL_SEG3 VOUT_MIN Figure 42 Multi-segment droop: V vs. I The first positive segment (SEG1) is the standard operating droop, which is programmed through the PMBus command VOUT_DROOP.
Page 85 In order to determine in which current segment the XDPP1100 is operating, the current itot_mux is compared to the segment current thresholds. The computed droop voltages in each of the four segments are described in Table 24.
Page 86: Droop Voltage Filtering
XDPP1100 technical reference manual Digital power controller Voltage control Table 24 Computed droop voltage by segment at high BW and low BW LPF inputs Segment Current range vdroop_hibw vdroop_lobw I < 0 I * rll_neg seg1 0 < I < ithr_seg2...
Page 87: Output Summation And Clamping
XDPP1100 technical reference manual Digital power controller Voltage control vc_vavp_kfp kfp kfp_real F3db (kHz) vc_vavp_kfp kfp kfp_real F3db (kHz) 0.0001 0.43 0.0017 6.81 0.0001 0.49 0.0020 7.79 0.0002 0.61 0.0024 9.74 0.0002 0.73 0.0029 11.69 0.0002 0.85 0.0034 13.65 0.0002 0.97...
Page 88: Voltage Control Registers
XDPP1100 technical reference manual Digital power controller Voltage control ��_��∗��_��_��∗50 (5.15) ��_��_��_�� = (24) Read-only registers vc_over_vout_max and vc_under_vout_min indicate when these clamp voltages are exceeded at the summation output and the clamp is applied. Additionally, they go to the fault module for reporting on STATUS_VOUT.
Page 89 XDPP1100 technical reference manual Digital power controller Voltage control Peripheral Field name Access Address Bits Description F3db(MHz) = [kfp/(1-kfp)] * 25 MHz / 2 * pi vcontrol vc_vramp_target 7000_1404h [14:0] Ramp target value referenced to (vcontrol0) VSEN input (i.e., after scaling by 7000_1804h VOUT_SCALE_LOOP).
Page 90 XDPP1100 technical reference manual Digital power controller Voltage control Peripheral Field name Access Address Bits Description vcontrol vc_vramp_on 7000_1404h [24] When high, indicates the ramp (vcontrol0) should respond to target changes 7000_1804h and that that loop is actively (vcontrol1) regulating.
Page 91 XDPP1100 technical reference manual Digital power controller Voltage control Peripheral Field name Access Address Bits Description LSB = 20 ns, range = 0.0 to 1.3107 ms vcontrol vc_vavp_itot_delta 7000_140Ch [12:0] Total current offset term applied to (vcontrol0) droop computations only. Allows...
Page 92 XDPP1100 technical reference manual Digital power controller Voltage control Peripheral Field name Access Address Bits Description vcontrol vc_vcontrol_vout_min 7000_1418h [15:8] min. limit referenced to VSEN (vcontrol0) input (i.e., after scaling by 7000_1818h VOUT_SCALE_LOOP. Target (vcontrol1) voltages (including droop) below this limit will be clamped to this level.
Page 93 XDPP1100 technical reference manual Digital power controller Voltage control Peripheral Field name Access Address Bits Description vcontrol vc_vcontrol_at_target 7000_1424h Status flag indicating the V control (vcontrol0) ramp is at the target voltage. 7000_1824h 0: Ramp not at target voltage (vcontrol1)
Page 94 XDPP1100 technical reference manual Digital power controller Voltage control Peripheral Field name Access Address Bits Description commands as follows: vc_vavp_rll_seg3(U9.1) = MFR_RDROOP_RLL_SEG3(Ux.y) * VOUT_SCALE_LOOP(U0.16) / (2^y * 2^(16-1)) where y = -1 * LINEAR11 exponent of MFR_RDROOP_RLL_SEG3 LSB = 0.5 mΩ, range = 0.0 to 511.5 mΩ...
Page 95: Voltage Control Pmbus Commands
XDPP1100 technical reference manual Digital power controller Voltage control Peripheral Field name Access Address Bits Description +vc_vavp_itot_delta 1: vc_vavp_otpt_uc_sel Voltage control PMBus commands The relevant voltage control-related PMBus commands are given in Table Table 28 Voltage control-related PMBus commands Command name...
Page 96 XDPP1100 technical reference manual Digital power controller Voltage control Command name Access Length Address Bits Description VOUT_MARGIN_LOW Word [15:0] Defines the output voltage when selected by the OPERATION command. Format is ULINEAR16 with the exponent defined by VOUT_MODE[4:0]. VOUT_TRANSITION_RATE Word...
Page 97 XDPP1100 technical reference manual Digital power controller Voltage control Command name Access Length Address Bits Description [63:48] MFR_RDROOP_RLL_SEG3: Sets the V droop rate in mV/A when I exceeds MFR_RDROOP_ITHR_SEG3. Format is LINEAR11. [79:64] MFR_RDROOP_RLL_NEG: Sets the V droop rate in mV/A when I is negative.
Page 98: Compensator
Compensator Compensator This chapter describes in more detail the XDPP1100 compensator implementation and main functionality. The relevant user-programmable parameters and corresponding registers are discussed as well as the input FF term and its relevant settings. Most of this chapter assumes that compensator output is directly the duty cycle as in VMC, and in section 6.3...
Page 99: Pre-Filter
XDPP1100 technical reference manual Digital power controller Compensator pid_kp_index_1ph for K • pid_ki_index_1ph for K • pid_kd_index_1ph for K • The PID provides a pole in the origin and two mid-band zeros while the LPFs present two high-frequency poles. This corresponds to the Type III compensation response which can provide up to 180 degrees of phase boost. A...
Page 100 XDPP1100 technical reference manual Digital power controller Compensator The filter coefficient parameters use an exponent mantissa format to provide an extended range utilizing fewer total bits. The upper three bits of kfp1_index represent the exponent and the lower three bits represent the mantissa.
Page 101 XDPP1100 technical reference manual Digital power controller Compensator kfp_index kfp_real 0.0063 0.0068 0.0073 0.0078 0.0088 0.0098 0.0107 0.0117 0.0127 0.0137 0.0146 0.0156 0.0176 0.0195 0.0215 0.0234 0.0254 0.0273 0.0293 0.0313 0.0352 0.0391 0.0430 0.0469 0.0508 0.0547 0.0586 0.0625 0.0703 0.0781 0.0859...
Page 102: Pid Term Computation
XDPP1100 technical reference manual Digital power controller Compensator Compensator pre- and post-filter bandwidth (kHz) 1000.00 100.00 10.00 1.00 kfp_index Figure 48 Pre- and post-filter BW as a function of kfp_index 6.1.2 PID term computation The PID coefficients are computed based on the pre-filter output signals: Proportional (P_term) and integral (I_term) terms are obtained from the filtered error signal verrn_filt •...
Page 103 XDPP1100 technical reference manual Digital power controller Compensator U-5.16 Clamp verrn_filt S4.16 S9.3 p_term pd_term U1.11 S8.16 d_term Clamp verrn_slope S7.16 S8.6 S15.12 U-15.26 S1.16 S1.16 Clamp S-6.29 i_term accum S1.16 Figure 49 PID computation block diagram Similarly to the pre-filter, the PID parameters use an exponent mantissa format to provide an extended range...
Page 104 XDPP1100 technical reference manual Digital power controller Compensator _index _real 0.0002 0.0002 0.0003 0.0003 0.0003 0.0004 0.0004 0.0004 0.0005 0.0005 0.0005 0.0006 0.0007 0.0007 0.0008 0.0009 0.0009 0.0010 0.0011 0.0012 0.0013 0.0015 0.0016 0.0017 0.0018 0.0020 0.0022 0.0024 0.0027 0.0029 0.0032...
Page 105 XDPP1100 technical reference manual Digital power controller Compensator _index _real 0.0073 0.0078 0.0088 0.0098 0.0107 0.0117 0.0127 0.0137 0.0146 1024 0.0156 1152 0.0176 1280 0.0195 1408 0.0215 1536 0.0234 1664 0.0254 1792 0.0273 1920 0.0293 Correspondingly, the integer and real number representations of K are computed as given in Equations (6.11)
Page 106 XDPP1100 technical reference manual Digital power controller Compensator _index _real 2.98E-07 3.28E-07 3.58E-07 3.87E-07 4.17E-07 4.47E-07 4.77E-07 5.36E-07 5.96E-07 6.56E-07 7.15E-07 7.75E-07 8.34E-07 8.94E-07 9.54E-07 1.07E-06 1.19E-06 1.31E-06 1.43E-06 1.55E-06 1.67E-06 1.79E-06 1.91E-06 2.15E-06 2.38E-06 2.62E-06 2.86E-06 3.10E-06 3.34E-06 3.58E-06 3.81E-06...
Page 107 XDPP1100 technical reference manual Digital power controller Compensator _index _real 9.54E-06 1.05E-05 1.14E-05 1.24E-05 1.34E-05 1.43E-05 1024 1.53E-05 1152 1.72E-05 1280 1.91E-05 1408 2.10E-05 1536 2.29E-05 1664 2.48E-05 1792 2.67E-05 1920 2.86E-05 The integer and real number representations of K are computed as provided in Equations (6.15) to (6.18).
Page 108 XDPP1100 technical reference manual Digital power controller Compensator _index _real 0.0137 0.0146 0.0156 0.0176 0.0195 0.0215 0.0234 0.0254 0.0273 0.0293 0.0313 0.0352 0.0391 0.0430 0.0469 0.0508 0.0547 0.0586 0.0625 0.0703 0.0781 0.0859 0.0938 0.1016 0.1094 0.1172 0.1250 0.1406 0.1563 0.1719 0.1875...
Page 109 XDPP1100 technical reference manual Digital power controller Compensator _index _real 0.4375 0.4688 1024 0.5000 1152 0.5625 1280 0.6250 1408 0.6875 1536 0.7500 1664 0.8125 1792 0.8750 1920 0.9375 2048 1.000 2304 1.125 2560 1.250 2816 1.375 3072 1.500 3328 1.625 3584 1.750...
Page 110: Post-Filter And Summation
XDPP1100 technical reference manual Digital power controller Compensator _index _real 28672 14.000 30720 15.000 32768 16.0 36864 18.0 40960 20.0 45056 22.0 49152 24.0 53248 26.0 57344 28.0 61440 30.0 65536 32.0 73728 36.0 81920 40.0 90112 44.0 98304 48.0 106496 52.0...
Page 111: Input/Output Clamping Of The Compensation Filter
XDPP1100 technical reference manual Digital power controller Compensator Integral term output, I_term • Voltage FF term, ff_duty • The implementation of the post-filter is illustrated in Figure U-3.13 U-3.13 S3.20 pd_term Clamp S8.16 S5.29 S1.20 S1.20 S1.20 S2.53 pid_force_duty duty cycle i_term U0.16...
Page 112: Output Override - Forced Duty Cycle
XDPP1100 technical reference manual Digital power controller Compensator The compensation filter output, duty_cycle, is clamped to a fixed 16-bit width. In the case of VMC it refers a value between 0.0 and 1.0. The PCMC behavior and the corresponding compensator output value is discussed section 6.3.
Page 113: Input Voltage Feed-Forward
• errn Under these conditions, the XDPP1100 HW freezes the integrator term accumulator. In addition to the HW freeze conditions, it is possible to freeze the integrator accumulator through register pid_freeze_accum. Another register, pid_reset_accum, allows the FW to reset the integrator accumulator to 0.
Page 114: Input Voltage Source Select And Computation
XDPP1100 technical reference manual Digital power controller Compensator �� (6.28) �� ,�� _��_�� Where: is the internal reference voltage • control VOUT_SCALE_LOOP is a PMBus command for external resistive divider • In the actual HW implementation, as shown in...
Page 115: Override And Adjustment Options For Ff
XDPP1100 technical reference manual Digital power controller Compensator An example of a special case for the FF calculation is when the ACF converter (Loop 0) is followed by post-buck topology (Loop 1). Thus, the Loop 1 input 1 is the output of Loop 0, and the following settings should be...
Page 116 XDPP1100 technical reference manual Digital power controller Compensator (6.31) �� _�� −9 �� = �� _�� ∗ 2 ∗ 2 �� 50 �� (6.32) �� 3�� ( �� ) = [ ] ∗ 1−�� 2�� Table 33...
Page 117: Control Mode Selection - Peak Current Mode
XDPP1100 technical reference manual Digital power controller Compensator Control mode selection – peak current mode This section describes the selection of control mode in more detail, focusing on the compensator-related register settings for PCMC. However, most PCMC-related circuitry and detailed functionality is discussed in the PWM chapter that follows.
Page 118: Compensation Filter Registers
XDPP1100 technical reference manual Digital power controller Compensator Both the duty cycle and FF must be above their corresponding thresholds, pid_osp_duty_thr and pid_osp_ff_thr, in order to prevent false fault detection at low voltages during start-up, when duty cycle is much larger than the FF (e.g., at V = 0 V).
Page 119 XDPP1100 technical reference manual Digital power controller Compensator Peripheral Field name Access Address Bits Description VOUT_COMMAND*VOUT_SCALE_LO OP - V(VSEN) 0: Clamp range = -40 to 40 mV 1: Clamp range = -80 to 80 mV 2: Clamp range = -120 to 120 mV...
Page 120 XDPP1100 technical reference manual Digital power controller Compensator Peripheral Field name Access Address Bits Description parameters pid_ff_override_sel and pid_ff_override (e.g., to override the HW-computed FF with a FW computation appropriate for boost or buck-boost derived topologies). 0: VS1 (VRSEN) V...
Page 121 XDPP1100 technical reference manual Digital power controller Compensator Peripheral Field name Access Address Bits Description 7000_2004h ki_man = 8 + pid_ki_index_1ph[2:0] (pid1) ki = ki_man * 2^ki_exp * 2^-25 pid_kd_index_1ph 7000_1C04h [30:24] PID derivative coefficient index. (pid0) Note that index settings greater 7000_2004h than 119 are clamped to 119.
Page 122 XDPP1100 technical reference manual Digital power controller Compensator Peripheral Field name Access Address Bits Description 7000_201Ch BVRSEN). Used only when selected by pid_ff_vrect_sel. If computing (pid1) from V pid_ff_vrect_override(U12.0) = (V) * 800 * MFR_VRECT_SCALE(U0.12) * MFR_TRANSFORMER_SCALE(U0.12) / (2^12 * 2^12) LSB = 1.25 mV, range = 0.0 to...
Page 123 XDPP1100 technical reference manual Digital power controller Compensator Peripheral Field name Access Address Bits Description MFR_TRANSFORMER_SCALE[9:0] pid_ff_i82_div_trans_scale_loop(U- 4.23) = quot1(U5.7) * 82 (U-9.16) LSB = 2^-23, range = 0.0 to 0.0625 7000_1C28h [5:0] PID K coefficient value after V RECT (pid0) scaling.
Page 124 XDPP1100 technical reference manual Digital power controller Compensator Peripheral Field name Access Address Bits Description 1: PCMC on secondary 2: PCMC on primary 3: Reserved ramp0_force_duty 7000_2C34 [7:0] Forced duty-cycle value overrides ramp0 input when selected by ramp0_force_duty_en. Because this force is applied at the ramp...
Page 125: Digital Pulse Width Modulator
At the end of the chapter, all relevant PWM-related registers and PMBus commands are given. The PWM converts the compensation filter output into one or more PWM pulses depending on the application. The XDPP1100 has up to 12 PWM output pins. The PWM consists of: Two ramp generators •...
Page 126: Pwm Ramp Generator
XDPP1100 technical reference manual Digital power controller Digital pulse width modulator pwm_force_hi[0] pwm1_loop_map[1] pwm_force_lo[0] pwm1_rise_sel pwm1_dr pwm1_fall_sel pwm1_df additional control signals Pulse Gen 1 Interpolator 1 PWM1 ramp0_tswitch pidX_duty Ramp Gen 0 pidX_ftr_mode pidX_ovs_mode ce0_synth_i Pulse Gen 2 Interpolator 2...
Page 127 XDPP1100 technical reference manual Digital power controller Digital pulse width modulator Table 35 Typical settings of the register rampX_pid_sel Topology ramp0_pid_sel ramp1_pid_sel Single loop, single-phase Single loop, interleaved Dual loop In order to generate the PWM pulses, the ramp generator produces the timing information based on a timing ramp.
Page 128: Pwm Ramp Modulation Schemes
PWM pulses. The timing markers are discussed further in the pulse generator section 7.2. The XDPP1100 supports the following modulation schemes for placing t1 and t2: Trailing edge (TE) modulation • Leading edge (LE) modulation •...
Page 129 XDPP1100 technical reference manual Digital power controller Digital pulse width modulator ramp count = ramp_max Ramp Count ramp count = 0 t1 = 0 t1 = 0 t1 = 0 t1 = 0 a) t1, t2 placement using trailing edge modulation...
Page 130: Pwm Ramp Synchronization
XDPP1100 technical reference manual Digital power controller Digital pulse width modulator The pulse width, t2 – t1, for all modulation schemes is given in Equation (7.2): (7.2) �� − �� = �� ∗ ��_�� D is the duty-cycle output of the compensation filter in the case of VMC. It should be noted that the pulse generator is also capable of creating a pulse with LE at t2 and TE at t1.
Page 131 External sync phase programming for non-bridge and bridge topologies In order to synchronize to the external signal, various IO pins of the XDPP1100 can be used. These pins are BEN, BPWRGD, EN, FAULT1, FAULT2, IMON, PWRGD, SMBALERT, SYNC and PWM1 through PWM12. Each pin has a corresponding register <pin_name>_func (such as fault1_func, or smbalert_func) which needs to be set to a...
Page 132: Pwm Pulse Generator
Section 7.7 provides a further description of these registers. PWM pulse generator The XDPP1100 contains 12 pulse generators, as was shown in Figure 54. There is one dedicated pulse generator for each of the PWM outputs, PWM1 through PWM12. These pulse generators use the timing markers, t1 and t2,...
Page 133: Ramp Selection (Loop/Phase)
Loop 0, Phase 2 or Loop 1, Phase 1 • The XDPP1100 also supports potential non-standard uses of the register pwmY_loop_map. Nevertheless, it is critical that the loop assignment is correct, as this is used for the HW-based fault-induced shutdown. For example, if both ramp0 and ramp1 are used by Loop 0, Phase 1, the pwmY_loop_map assignment to select ramp1 should be 3 since that corresponds to Loop 0.
Page 134 The selection of the falling edge is the same as defined for the rising edge. The only exception is that the options VRSEN or BVRSEN are not available for the falling edge. The XDPP1100 GUI can be used to automatically program the registers pwmY_loop_map, pwmY_rise_sel and pwmY_fall_sel based on topology selection and PWM output mapping. Some example settings for these...
Page 135: Dead Time Programming
7.2.4 Dead time programming The XDPP1100 is capable of applying independent dead time (delay) to both the rising and the falling edges of each PWM output. The dead time programming for the edges is the following: Rising edge dead time, via register pwmY_dr (Y = 1 to 12) •...
Page 136 XDPP1100 technical reference manual Digital power controller Digital pulse width modulator ramp count = ramp_max Ramp ramp count = 0 PWMY pwmY_dr pwmY_df Figure 59 Dead time programming Table 40 PMBus command PWM_DEADTIME mapping to pwmY_dr and pwmY_df PWM_DEADTIME[7:0] pwm1_df[7:0]...
Page 137: Force High Force Low
Force high force low The XDPP1100 has two registers which allow the PWM output state to be forced. By setting appropriate bits in either of the following register values to 1, the corresponding PWM output can be forced either high or low: Register pwm_force_hi[11:0] forces the corresponding PWM output high •...
Page 138 XDPP1100 technical reference manual Digital power controller Digital pulse width modulator ramp_force_t1, ramp_force_t1_en ramp_force_t2, ramp_force_t2_en Ramp ramp_half_mode even_cycle ramp_max ramp ibal_duty_adj pulse ramp t1_val pw_even t1_crossing pid_duty width cross ramp_pw detect ramp_force_duty t1,t2 pw_odd t2_val t2_crossing ramp_force_duty_en Hold flux_duty_adj ramp_m_flavor...
Page 139: Peak Current Mode Control
1 for secondary-side PCMC or to 2 for primary-side PCMC. In the case of PCMC the compensator output represents the control current, whereas for VMC it was directly the duty cycle. Figure 61 shows the functional block diagram of the XDPP1100 internal configuration when PCMC is applied. Slope Compensation compensation_slope PCMC...
Page 140: Maximum And Minimum Pulse Width Enforcement
XDPP1100 technical reference manual Digital power controller Digital pulse width modulator determine the convergence rate of these two signals, the PCMC cross-detect function uses the slope information from both the slope compensation ramp and the CE. This convergence rate information is used to: predict the t2 crossing in the next clock cycle •...
Page 141: Forced Duty Cycle T1, T2
• required, this is the only method to override the duty cycle. These PID override parameters are stored in the OTP so they can be used to configure the XDPP1100 to • apply permanent fixed duty cycle in an open-loop control mode without applying a FW patch.
Page 142: Burst Mode
OFF time Figure 62 BM operation with pid_burst_reps = 1 Upon entering BM, the XDPP1100 disables the SR FETs and outputs a burst of PWM pulses on each half-cycle corresponding to a number programmed via register pid_burst_reps as defined in Table...
Page 143: Fast-Transient Response
The BW is typically 1/6 to 1/10 of the switching frequency. A slow response results in increased undershoot or overshoot. In order to improve the transient performance, the XDPP1100 supports two fast response modes for transient improvement. These are: Fast-transient response for load steps •...
Page 144 XDPP1100 technical reference manual Digital power controller Digital pulse width modulator PRIMARY LOAD LOAD verr_slope_entry_thrs verr_slope_exit_thrs verr_entry_thrs verr_exit_thrs Figure 63 Fast-transient response waveform Two registers control the entry into the fast-transient response mode. These are: pid_verr_entry_thrs, which defines the error voltage (V = target voltage –...
Page 145: Fast-Transient Response - Load Release
4 to 7 Filter bypassed Refer to “Application Guide – Digital power controller XDPP1100” for additional information regarding system tuning with respect to fast-transient response. 7.5.2 Fast-transient response – load release The controller minimizes the duty cycle when a negative load step is detected. This is performed by immediately reducing the PWM PW to the programmed minimum (which may be 0).
Page 146: Pwm Interrupts
LPF. The filter BW settings were summarized in Table Refer to “Application Guide – Digital power controller XDPP1100” for additional information regarding system tuning with respect to fast-overshoot response. PWM interrupts Both ramp generators (ramp0 and ramp1) are capable of setting two interrupts (IRQs). The following registers...
Page 147: Pwm Registers
XDPP1100 technical reference manual Digital power controller Digital pulse width modulator In addition to setting an interrupt on t1 and t2: Register rampX_t1_irq_sel may also select an arbitrary phase location within the ramp for an interrupt. The • phase location is defined by the register rampX_irq_phase. Its value is defined according to Equation (7.14).
Page 148 XDPP1100 technical reference manual Digital power controller Digital pulse width modulator Peripheral Field name Access Address Bits Description topologies and disabled otherwise. 0: Half-mode disabled (non-bridge topology) 1: Half-mode enabled (bridge topology) ramp0_min_pw_stat 7000_2C00h Selects pulse generator response when PW computed from PID duty cycle is less than ramp0_pw_min.
Page 149 XDPP1100 technical reference manual Digital power controller Digital pulse width modulator Peripheral Field name Access Address Bits Description half of T , otherwise it is equal to switch . Half-mode should be enabled switch for bridge type primary-side topologies and disabled otherwise.
Page 150 XDPP1100 technical reference manual Digital power controller Digital pulse width modulator Peripheral Field name Access Address Bits Description compensation_slope 7000_2C00h [19:18] Defines the compensation ramp slope when PCMC selected as modulation type by mode_control_loop0 or mode_control_loop1. This single register applies to both loops in the case of a dual-loop system.
Page 151 XDPP1100 technical reference manual Digital power controller Digital pulse width modulator Peripheral Field name Access Address Bits Description designations are for use with bridge topologies to distinguish between half-cycles. The VRSEN and BVRSEN options allow a PWM output to be set high...
Page 152 XDPP1100 technical reference manual Digital power controller Digital pulse width modulator Peripheral Field name Access Address Bits Description 0.5 * T and T for bridge switch switch topologies) and t1 is modulated. When using DE modulation, t1 and t2 are centered around 0.5 * T switch (or 0.25 * T...
Page 153 XDPP1100 technical reference manual Digital power controller Digital pulse width modulator Peripheral Field name Access Address Bits Description pwm3_rise_sel 7000_2C04h [20:17] Topology-driven PWM3 rising edge select. t1 and t2 refer to the modulated edges created by the ramp. When using TE modulation, t1 is fixed at time 0 and t2 is modulated.
Page 154 XDPP1100 technical reference manual Digital power controller Digital pulse width modulator Peripheral Field name Access Address Bits Description 1: t2 2: t1 even cycle 3: t2 even cycle 4: t1 odd cycle 5: t2 odd cycle 6: t1 delay 7: t2 delay...
Page 155 XDPP1100 technical reference manual Digital power controller Digital pulse width modulator Peripheral Field name Access Address Bits Description (or 0.25 * T and 0.75 * T switch switch bridge topologies) and both are modulated. Odd and even cycle designations are for use with bridge topologies to distinguish between half-cycles.
Page 156 XDPP1100 technical reference manual Digital power controller Digital pulse width modulator Peripheral Field name Access Address Bits Description t1 is fixed at time 0 and t2 is modulated. When using LE modulation, t2 is fixed at T switch 0.5 * T...
Page 157 XDPP1100 technical reference manual Digital power controller Digital pulse width modulator Peripheral Field name Access Address Bits Description 7: t2 delay 8: VRSEN neg. edge 9 to 15: BVRSEN neg. edge pwm7_fall_sel 7000_2C08h [16:14] Topology-driven PWM7 falling edge select. t1 and t2 refer to the modulated edges created by the ramp.
Page 158 XDPP1100 technical reference manual Digital power controller Digital pulse width modulator Peripheral Field name Access Address Bits Description 0: t1 1: t2 2: t1 even cycle 3: t2 even cycle 4: t1 odd cycle 5: t2 odd cycle 6: t1 delay 7: t2 delay 8: VRSEN neg.
Page 159 XDPP1100 technical reference manual Digital power controller Digital pulse width modulator Peripheral Field name Access Address Bits Description topologies to distinguish between half-cycles. The VRSEN and BVRSEN options allow a PWM output to be set high after detection of the falling transition of the rectification voltage.
Page 160 XDPP1100 technical reference manual Digital power controller Digital pulse width modulator Peripheral Field name Access Address Bits Description topologies) and t1 is modulated. When using DE modulation, t1 and t2 are centered around 0.5 * T switch (or 0.25 * T and 0.75 * T...
Page 161 XDPP1100 technical reference manual Digital power controller Digital pulse width modulator Peripheral Field name Access Address Bits Description pwm10_rise_sel 7000_2C0Ch [13:10] Topology-driven PWM10 rising edge select. t1 and t2 refer to the modulated edges created by the ramp. When using TE modulation, t1 is fixed at time 0 and t2 is modulated.
Page 162 XDPP1100 technical reference manual Digital power controller Digital pulse width modulator Peripheral Field name Access Address Bits Description 1: t2 2: t1 even cycle 3: t2 even cycle 4: t1 odd cycle 5: t2 odd cycle 6: t1 delay 7: t2 delay...
Page 163 XDPP1100 technical reference manual Digital power controller Digital pulse width modulator Peripheral Field name Access Address Bits Description (or 0.25 * T and 0.75 * T switch switch bridge topologies) and both are modulated. Odd and even cycle designations are for use with bridge topologies to distinguish between half-cycles.
Page 164 XDPP1100 technical reference manual Digital power controller Digital pulse width modulator Peripheral Field name Access Address Bits Description 2: Loop 1, phase 0 3: Loop 0, phase 1 pwm2_loop_map 7000_2C10h [3:2] Defines the loop and phase mapping of the PWM2 output.
Page 165 XDPP1100 technical reference manual Digital power controller Digital pulse width modulator Peripheral Field name Access Address Bits Description 2: Loop 1, phase 0 3: Loop 0, phase 1 pwm10_loop_map 7000_2C10h [19:18] Defines the loop and phase mapping of the PWM10 output.
Page 166 XDPP1100 technical reference manual Digital power controller Digital pulse width modulator Peripheral Field name Access Address Bits Description max. duty-cycle limit is scaled with respect to the V reference defined by parameter pid1.pid_vrect_ref as shown below. Max. duty = ramp1_dc_max_nom *...
Page 167 XDPP1100 technical reference manual Digital power controller Digital pulse width modulator Peripheral Field name Access Address Bits Description ramp1_phase 7000_2C20h [7:0] ramp1 phase alignment with respect to sync signal selected with ramp1_sync_sel. Computed by FW from PMBus command as follows: ramp1_phase = 2^8 * PAGE1.INTERLEAVE[3:0]/...
Page 168 XDPP1100 technical reference manual Digital power controller Digital pulse width modulator Peripheral Field name Access Address Bits Description determined by the setting of ramp0_pw_min_state. Computed by FW from PMBus as follows: ramp0_pw_min = MFR_MIN_PW LSB = 5 ns, range = 0 to 1275 ns...
Page 169 XDPP1100 technical reference manual Digital power controller Digital pulse width modulator Peripheral Field name Access Address Bits Description ramp0_force_t2_en 7000_2C3Ch [11] PWM ramp0 t2 force enable. 0: t2 determined by modulation scheme and duty cycle 1: t2 set by ramp0_force_t2...
Page 170 XDPP1100 technical reference manual Digital power controller Digital pulse width modulator Peripheral Field name Access Address Bits Description ramp1_force_duty_e 7000_2C48h PWM ramp1 forced duty-cycle select. 0: Use PID computed duty cycle 1: Use ramp1_force_duty ramp1_force_t1 7000_2C4Ch [10:0] PWM ramp1 forced t1 setting selected by ramp1_force_t1_en.
Page 171 XDPP1100 technical reference manual Digital power controller Digital pulse width modulator Peripheral Field name Access Address Bits Description LSB = 1.25 ns, range = 0.0 to 318.75 ns pwm1_df 7000_2C54h [15:8] PWM1 falling edge delay (dead) time from t1 or t2. Mapping of the falling edge to t1 or t2 defined by pwm1_fall_sel.
Page 172 XDPP1100 technical reference manual Digital power controller Digital pulse width modulator Peripheral Field name Access Address Bits Description LSB = 1.25 ns, range = 0.0 to 318.75 ns pwm3_dr 7000_2C5Ch [7:0] PWM3 rising edge delay (dead) time from t1 or t2. Mapping of the rising edge to t1 or t2 defined by pwm3_rise_sel.
Page 173 XDPP1100 technical reference manual Digital power controller Digital pulse width modulator Peripheral Field name Access Address Bits Description pwm4_df 7000_2C60h [15:8] PWM4 falling edge delay (dead) time from t1 or t2. Mapping of the falling edge to t1 or t2 defined by pwm4_fall_sel.
Page 174 XDPP1100 technical reference manual Digital power controller Digital pulse width modulator Peripheral Field name Access Address Bits Description pwm6_dr 7000_2C68h [7:0] PWM6 rising edge delay (dead) time from t1 or t2. Mapping of the rising edge to t1 or t2 defined by pwm6_rise_sel.
Page 175 XDPP1100 technical reference manual Digital power controller Digital pulse width modulator Peripheral Field name Access Address Bits Description pwm7_df 7000_2C6Ch [15:8] PWM7 falling edge delay (dead) time from t1 or t2. Mapping of the falling edge to t1 or t2 defined by pwm7_fall_sel.
Page 176 XDPP1100 technical reference manual Digital power controller Digital pulse width modulator Peripheral Field name Access Address Bits Description pwm9_dr 7000_2C74h [7:0] PWM9 rising edge delay (dead) time from t1 or t2. Mapping of the rising edge to t1 or t2 defined by pwm9_rise_sel.
Page 177 XDPP1100 technical reference manual Digital power controller Digital pulse width modulator Peripheral Field name Access Address Bits Description pwm10_df 7000_2C78h [15:8] PWM10 falling edge delay (dead) time from t1 or t2. Mapping of the falling edge to t1 or t2 defined by pwm10_fall_sel.
Page 178 XDPP1100 technical reference manual Digital power controller Digital pulse width modulator Peripheral Field name Access Address Bits Description pwm12_dr 7000_2C80h [7:0] PWM12 rising edge delay (dead) time from t1 or t2. Mapping of the rising edge to t1 or t2 defined by pwm12_rise_sel.
Page 179 XDPP1100 technical reference manual Digital power controller Digital pulse width modulator Peripheral Field name Access Address Bits Description ramp0_t2_irq_sel 7000_2C8Ch [5:3] PWM ramp0 t2 IRQ source select. 0: t2 IRQ disabled 1: t2 2: t2 even 3: t2 odd 4 to 7: V...
Page 180 XDPP1100 technical reference manual Digital power controller Digital pulse width modulator Peripheral Field name Access Address Bits Description 0: Every T switch 1: Every 2 T switch 2: Every 4 T switch 3: Every 8 T switch 4: Every 16 T...
Page 181 XDPP1100 technical reference manual Digital power controller Digital pulse width modulator Peripheral Field name Access Address Bits Description pid_verr_slope_exit_ 7000_1C0Ch [13:7] FTR mode error voltage (V ) slope thrs (pid0) exit threshold where the error 7000_200Ch voltage is defined as...
Page 182 XDPP1100 technical reference manual Digital power controller Digital pulse width modulator Peripheral Field name Access Address Bits Description undershoot. LSB = 1.25 mV/clk, range = 0.0 to 158.75 mV/clk at VSEN pid_ftr_lpf 7000_1C0Ch [30:28] FTR mode LPF BW applied to the...
Page 183 XDPP1100 technical reference manual Digital power controller Digital pulse width modulator Peripheral Field name Access Address Bits Description 7000_2010h (pid1) = (target voltage - sense voltage) When (V is less than pid_ovs_entry_thrs) AND (V slope is less than pid_ovs_slope_entry_thrs) the control loop enters OVS mode.
Page 184 XDPP1100 technical reference manual Digital power controller Digital pulse width modulator Peripheral Field name Access Address Bits Description voltage. LSB = 1.25 mV, range = 0.0 to 18.75 mV at VSEN pid_burst_mode_ith 7000_1C14h [9:4] BM entry current threshold. When (pid0)
Page 185: Pwm Pmbus Commands
This may be used to facilitate paralleling of multiple units or to reduce AC currents injected into the power bus. On the XDPP1100 it is also used to set the relative phase alignment of the two phases in a dual- phase topology.
Page 186 XDPP1100 technical reference manual Digital power controller Digital pulse width modulator Command name Access Length Address Bits Description PAGE1.INTERLEAVE[7:4] = 2d (two phases in group) PAGE1.INTERLEAVE[3:0] = 1d (position 1 in group 180 degrees) The FW_CONFIG_PWM command FW_CONFIG_PWM Block [31:0]...
Page 187 XDPP1100 technical reference manual Digital power controller Digital pulse width modulator Command name Access Length Address Bits Description pwm5_df [79:72]: PWM5 rising edge dead time, pwm5_dr [87:80]: PWM6 falling edge dead time, pwm6_df [95:88]: PWM6 rising edge dead time, pwm6_dr...
Page 188 XDPP1100 technical reference manual Digital power controller Digital pulse width modulator Command name Access Length Address Bits Description pwm4_df [63:56]: PWM4 rising edge dead time, pwm4_dr [71:64]: PWM5 falling edge dead time, pwm5_df [79:72]: PWM5 rising edge dead time, pwm5_dr...
Page 189 XDPP1100 technical reference manual Digital power controller Digital pulse width modulator Command name Access Length Address Bits Description ramp1 even in the case that both PWM ramps are used by Loop 0. User Manual 189 of 562 V 1.0 2021-08-25...
Page 190: Telemetry
XDPP1100 technical reference manual Digital power controller Telemetry Telemetry This chapter discusses the telemetry module and its submodules and their operation. The relevant register settings and PMBus commands are also provided. The main function of the telemetry module is to provide source selection and low-pass filtering of HW-sensed...
Page 191: Input Voltage
XDPP1100 technical reference manual Digital power controller Telemetry tlm_kfp_vout kfp kfp_real F3db (kHz) tlm_kfp_vout kfp kfp_real F3db (kHz) 0.0015 11.67 0.0234 190.99 0.0017 13.62 0.0273 223.71 The LPF output is subsampled to the F rate and it is available as read-only register tlmX_vout_fsw. This...
Page 192 XDPP1100 technical reference manual Digital power controller Telemetry tlm_vin_src_sel Source Comments VRSEN Non-pulsed/primary V sense via VSADC BVRSEN Non-pulsed/primary V sense via VSADC When Loop 0 V is selected as the V source for Loop 1, it is important to note that scaling by register tlm1_vin_convert_factor will apply.
Page 193: Output Current
XDPP1100 technical reference manual Digital power controller Telemetry If secondary-side sense is selected as the input source, several registers are provided to fine-tune the V to V RECT computation. There registers are: tlmX_vrect_voffset, which is a constant offset correction term added directly to V voltage coming from •...
Page 194 XDPP1100 technical reference manual Digital power controller Telemetry ISEN and BISEN, which can be selected individually to provide I , or input CE (section 8.5) is provided to • estimate I based on measured V and duty cycle if I...
Page 195: Output And Input Power Telemetry
XDPP1100 technical reference manual Digital power controller Telemetry one_div_vin[13:0] U0.14 tlmX_vout_div_vin[11:0] U0.12 tlmX_vout_fsw_1v[15:0] U6.10, 1v tlmX_duty_fsw[15:4] tlmX_iin_est[12:0] U0.12 U6.7 tlmX_transformer_scale_loop[11:0] tlmX_iin_est_alpha[5:0] tlmX_iout_fsw[12:0] RW parameters U0.12 U0.6 S9.4 RO parameters Figure 69 Input current estimation block diagram Output and input power telemetry Output and input power telemetry are computed in FW based on the HW-computed voltages and currents.
Page 196 XDPP1100 technical reference manual Digital power controller Telemetry tlm_kfp_tsen[5:0] ts_atsen_adc[13:0] tlm_atsen_lpf[9:0] U10.4 U10.0 ts_atsen_adc_update 25 MHz ts_btsen_adc[13:0] tlm_btsen_lpf[9:0] U10.4 U10.0 ts_btsen_adc_update 25 MHz ts_itsen_adc[13:0] tlm_itsen_lpf[9:0] U10.4 U10.0 ts_itsen_adc_update 25 MHz RW parameters RO parameters Figure 70 Temperature telemetry block diagram Table 55 Temperature and general-purpose ADC LPF BW programming, where LSB = 0.0001221 and...
Page 197: Duty-Cycle Telemetry
XDPP1100 technical reference manual Digital power controller Telemetry The conversion from ADC codes to temperature is performed in FW using a user-defined LUT. A default LUT is provided in ROM based on a 47 k NTC sense element. Both NTC and PTC LUTs are allowed.
Page 198: General-Purpose Adc Telemetry
XDPP1100 technical reference manual Digital power controller Telemetry Figure 72 Switching frequency telemetry block diagram 8.10 General-purpose ADC telemetry The general-purpose TSADC outputs are low-pass filtered as illustrated in the block diagram in Figure 73. The IMON and XADDR BWs are programmed via registers tlm_kfp_imon and tlm_kfp_xaddr according to the...
Page 199 XDPP1100 technical reference manual Digital power controller Telemetry Table 57 PRISEN ADC LPF BW programming, where LSB = 0.0001221 and F = 0.25 MHz. Applicable sample to PRISEN when ts_muxmode = 6, 7 and IMON when ts_muxmode = 4, 6.
Page 200: Telemetry Interrupts
61.894 8.11 Telemetry interrupts The XDPP1100 provides 16 independently programmable telemetry IRQs. Figure 74 shows a block diagram of one IRQ along with the ORing of the other IRQs to generate signal tlm_irq, which is sent to the CPU. Register...
Page 201: Telemetry High/Low Watermark Detect
The telemetry IRQ status is available on read-only register tlm_irq_stat. 8.12 Telemetry high/low watermark detect The XDPP1100 contains two watermark detectors per loop, designated as A and B. Figure 75 shows a block diagram of a single detector. Each watermark detector is capable of detecting and capturing the high and low input value since the last clear.
Page 202: Telemetry Registers
XDPP1100 technical reference manual Digital power controller Telemetry tlm_hilo_mark_sel Source Register tlmX_hilo_mark_Y_clr is used to clear current high and low stored values. Upon a clear: The high register is reset to its minimum setting based on the format of the selected input; 0000h for •...
Page 203 XDPP1100 technical reference manual Digital power controller Telemetry Peripheral Field name Access Address Bits Description 7000_3800h to 9. Set to 63 to bypass filter. kfp_exp = tlm_kfp_iin[5:2]" (Loop 1) kfp_man = 4 + tlm_kfp_iin[1:0] kfp = kfp_man * 2^kfp_exp * 2^-13...
Page 204 XDPP1100 technical reference manual Digital power controller Telemetry Peripheral Field name Access Address Bits Description LINEAR11 format for correct scaling of V telemetry. telem tlm_kfp_vin 7000_3404h [5:0] Input voltage telemetry LPF (Loop 0) coefficient index. Note that exp. 7000_3804h settings greater than 9 are clamped (Loop 1) to 9.
Page 205 XDPP1100 technical reference manual Digital power controller Telemetry Peripheral Field name Access Address Bits Description 5: 1280 mV 6: 1600 mV 7: 1920 mV telem tlm_duty_fsw 7000_3408h [15:0] Low-pass filtered duty-cycle (Loop 0) telemetry updated at F rate. switch 7000_3808h...
Page 206 XDPP1100 technical reference manual Digital power controller Telemetry Peripheral Field name Access Address Bits Description 7000_3818h LSB = 2^-12 V/V, range = 0.0 to (Loop 1) 0.9998 V/V telem tlm_iout_fs 7000_341Ch [12:0] Unfiltered, cycle-averaged output (Loop 0) current updated at F rate.
Page 207 XDPP1100 technical reference manual Digital power controller Telemetry Peripheral Field name Access Address Bits Description 7000_382Ch FW as follows: READ_VIN(U7.2) = tlm_vin_lpf[10:2] (Loop 1) LSB = 62.5 mV, range = 0.0 to 127.9375 V telem tlm_vout_convert_facto 7000_3430h [20:0] Conversion factor for computing...
Page 208 XDPP1100 technical reference manual Digital power controller Telemetry Peripheral Field name Access Address Bits Description LSB = 0.15625 mV, range = 0.0 to 5.11875 V telem tlm_transformer_scale_l 7000_343Ch [11:0] Ratio of V to V . For HB equal to RECT...
Page 209 XDPP1100 technical reference manual Digital power controller Telemetry Peripheral Field name Access Address Bits Description telem tlm_hilo_mark_A_sel 7000_3448h [1:0] Input select for high/low (Loop 0) watermark detector A. 7000_3848h 0: V (Loop 1) 1: V 2: I 3: I telem...
Page 210 XDPP1100 technical reference manual Digital power controller Telemetry Peripheral Field name Access Address Bits Description : Unsigned, LSB = 7.8125 mA, range = 0.0 to 63.9922 A : Signed, LSB = 62.5 mA, range = -256 to +255.9375 A telem...
Page 211 XDPP1100 technical reference manual Digital power controller Telemetry Peripheral Field name Access Address Bits Description when used as a general-purpose ADC. Note that exp. settings greater than 9 are clamped to 9. Set to 63 to bypass filter. kfp_exp = tlm_kfp_xaddr[5:2]...
Page 212 XDPP1100 technical reference manual Digital power controller Telemetry Peripheral Field name Access Address Bits Description 14: Internal temp. 15: IMON 16: PRISEN 17: XADDR1 18: XADDR2 19 to 31: Unused tlmcom tlm_irq_gereric_thr_1 7000_5008h [15:0] Telemetry IRQ 1 threshold. Compared against signal selected by tlm_irq_thr_src_sel_1.
Page 213 XDPP1100 technical reference manual Digital power controller Telemetry Peripheral Field name Access Address Bits Description 17: XADDR1 18: XADDR2 19 to 31: Unused tlmcom tlm_irq_gereric_thr_2 7000_500Ch [15:0] Telemetry IRQ 2 threshold. Compared against signal selected by tlm_irq_thr_src_sel_2. Format based on selected source.
Page 214 XDPP1100 technical reference manual Digital power controller Telemetry Peripheral Field name Access Address Bits Description tlmcom tlm_irq_gereric_thr_3 7000_5010h [15:0] Telemetry IRQ 3 threshold. Compared against signal selected by tlm_irq_thr_src_sel_3. Format based on selected source. : S9.4, LSB = 62.5 mA, range = -256 to +255.9375 A...
Page 215 XDPP1100 technical reference manual Digital power controller Telemetry Peripheral Field name Access Address Bits Description based on selected source. : S9.4, LSB = 62.5 mA, range = -256 to +255.9375 A : U12.3, LSB = 156.25 µV, range = 0.0 to 5.11984375 V : U6.7, LSB = 7.8125 mA, range =...
Page 216 XDPP1100 technical reference manual Digital power controller Telemetry Peripheral Field name Access Address Bits Description : U12.3, LSB = 156.25 µV, range = 0.0 to 5.11984375 V : U6.7, LSB = 7.8125 mA, range = 0.0 to 63.9922 A : U7.4, LSB = 62.5 mV, range = 0.0 to 127.9375 V...
Page 217 XDPP1100 technical reference manual Digital power controller Telemetry Peripheral Field name Access Address Bits Description 0.0 to 63.9922 A : U7.4, LSB = 62.5 mV, range = 0.0 to 127.9375 V Duty: U0.16, LSB = 2^-16, range = 0.0 to 0.99998 : U11.0, LSB = 1 kHz, range = 0...
Page 218 XDPP1100 technical reference manual Digital power controller Telemetry Peripheral Field name Access Address Bits Description Duty: U0.16, LSB = 2^-16, range = 0.0 to 0.99998 : U11.0, LSB = 1 kHz, range = 0 switch to 2047 kHz ATSEN, BTSEN, ITSEN: U10.0, LSB =...
Page 219 XDPP1100 technical reference manual Digital power controller Telemetry Peripheral Field name Access Address Bits Description to 2047 kHz ATSEN, BTSEN, ITSEN: U10.0, LSB = 1 ADC code, range = 0 to 1023 ADC codes IMON, PRISEN, XADDR1, XADDR2: U10.4, LSB = 0.0625 ADC code, range = 0.0 to 1023.9375 ADC codes...
Page 220 XDPP1100 technical reference manual Digital power controller Telemetry Peripheral Field name Access Address Bits Description codes IMON, PRISEN, XADDR1, XADDR2: U10.4, LSB = 0.0625 ADC code, range = 0.0 to 1023.9375 ADC codes tlmcom tlm_irq_thr_src_sel_9 7000_5028h [20:16] Telemetry IRQ 9 source select.
Page 221 XDPP1100 technical reference manual Digital power controller Telemetry Peripheral Field name Access Address Bits Description U10.4, LSB = 0.0625 ADC code, range = 0.0 to 1023.9375 ADC codes tlmcom tlm_irq_thr_src_sel_10 7000_502Ch [20:16] Telemetry IRQ 10 source select. Selects signal to compare against tlm_irq_gereric_thr_10 for IRQ generation.
Page 222 XDPP1100 technical reference manual Digital power controller Telemetry Peripheral Field name Access Address Bits Description tlmcom tlm_irq_thr_src_sel_11 7000_5030h [20:16] Telemetry IRQ 11 source select. Selects signal to compare against tlm_irq_gereric_thr_11 for IRQ generation. 0: Loop 0 I 1: Loop 1 I...
Page 223 XDPP1100 technical reference manual Digital power controller Telemetry Peripheral Field name Access Address Bits Description generation. 0: Loop 0 I 1: Loop 1 I 2: Loop 0 V 3: Loop 1 V 4: Loop 0 I 5: Loop 1 I...
Page 224 XDPP1100 technical reference manual Digital power controller Telemetry Peripheral Field name Access Address Bits Description 3: Loop 1 V 4: Loop 0 I 5: Loop 1 I 6: Loop 0 V 7: Loop 1 V 8: Loop 0 duty 9: Loop 1 duty...
Page 225 XDPP1100 technical reference manual Digital power controller Telemetry Peripheral Field name Access Address Bits Description 7: Loop 1 V 8: Loop 0 duty 9: Loop 1 duty 10: Loop 0 F switch 11: Loop 1 F switch 12: ATSEN 13: BTSEN 14: Internal temp.
Page 226 XDPP1100 technical reference manual Digital power controller Telemetry Peripheral Field name Access Address Bits Description 11: Loop 1 F switch 12: ATSEN 13: BTSEN 14: Internal temp. 15: IMON 16: PRISEN 17: XADDR1 18: XADDR2 19 to 31: Unused tlmcom...
Page 227 XDPP1100 technical reference manual Digital power controller Telemetry Peripheral Field name Access Address Bits Description LSB = 0.25 ADC code, range = 0 to 1023.75 ADC codes tlmcom tlm_irq_polarity 7000_505Ch [15:0] Telemetry IRQ comparison polarity select where bit [X] corresponds to IRQX.
Page 228: Pmbus
XDPP1100 technical reference manual Digital power controller Telemetry 8.14 PMBus The relevant PMBus commands for telemetry are given in Table Table 62 PWM-related PMBus commands Command name Access Length Address Bits Description VOUT_SCALE_LOOP Word [15:0] Scales VOUT_COMMAND and other -related commands for the external resistor divider between V and VSEN.
Page 229 XDPP1100 technical reference manual Digital power controller Telemetry Command name Access Length Address Bits Description FW_CONFIG_TELEMETRY.READ_DUTY_ EXP. READ_FREQUENCY Word [15:0] Returns the switching frequency in kHz in the LINEAR11 format. If the device is configured as a SYNC slave, this...
Page 230 XDPP1100 technical reference manual Digital power controller Telemetry Command name Access Length Address Bits Description MFR_TRANSFORMER_SCA Word [15:0] Defines the transformer turns ratio, . The format is turn_sec turn_prim LINEAR11 with recommended exponents -10, -11, -12 if (N is greater than 0.5)
Page 231 XDPP1100 technical reference manual Digital power controller Telemetry Command name Access Length Address Bits Description READ_TEMPERATURE_2 = ITSEN 4: READ_TEMPERATURE_1 = ITSEN, READ_TEMPERATURE_2 = ATSEN 5: READ_TEMPERATURE_1 = ITSEN, READ_TEMPERATURE_2 = BTSEN 6, 7: READ_TEMPERATURE_1 = ATSEN, READ_TEMPERATURE_2 = BTSEN...
Page 232: Fault Handler
XDPP1100 technical reference manual Digital power controller Fault handler Fault handler This chapter discusses the fault handler module and its main functionalities and relevant registers programming. All the PMBus commands mentioned within the chapter are described in section 9.8. The fault module is responsible for detecting faults and reporting them to the FW as well as initiating fault- based shutdown.
Page 233: Output Voltage Faults
XDPP1100 technical reference manual Digital power controller Fault handler vspX_vout_fs vout_ov_fault faultX_vout_ov_fault_thresh faultX_vout_ov_fault_cnt vout_ov_warn faultX_vout_ov_warn_thresh faultX_vout_ov_warn_cnt faults vout_uv_fault faultX_vout_uv_fault_thresh faultX_vout_uv_fault_cnt vout_uv_warn faultX_vout_uv_warn_thresh faultX_reg_loop[31:0] faultX_vout_uv_warn_cnt fault_loop_bus[31:0] Fault latching faultX_vout_fault_hyst Note: Bus connections faultX_status_loop[31:0] tlmX_vin_lpf not shown tied to logic 0. vin_ov_fault...
Page 234 • STATUS_VOUT • It should be noted that VOUT_OV_FAULT and VOUT_UV_FAULT remain asserted in the PMBus STATUS command until VOUT_OV_WARNING and VOUT_UV_WARNING are deasserted. The XDPP1100 response to the output voltage faults is programmed through the PMBus commands: VOUT_OV_FAULT_RESPONSE •...
Page 235: Input Voltage Faults
XDPP1100 technical reference manual Digital power controller Fault handler The time unit for the delay portion of the output voltage RESPONSE commands is defined by PMBus command FW_CONFIG_FAULTS bits [7:6]. All of these PMBus commands are described in section 9.8.
Page 236: Output Current Faults
• STATUS_INPUT • It should be noted that VIN_OV_FAULT and VIN_UV_FAULT remain asserted in the PMBus STATUS command until VIN_OV_WARNING and VIN_UV_WARNING are deasserted. The XDPP1100 response to the input voltage faults is programmed through the PMBus commands: VIN_OV_FAULT_RESPONSE •...
Page 237 • MFR_IOUT_OC_FAST_FAULT • In this mode, the XDPP1100 attempts to continue operation while maintaining the output current at IOUT_OC_FAULT_LIMIT by reducing the output voltage. If the output voltage drops below the threshold defined by register fault_iout_oc_lv_fault_thresh, IOUT_OC_LV_FAULT is declared. User Manual 237 of 562 V 1.0...
Page 238: Input Current Faults
9.8. 9.1.5 Power warnings The XDPP1100 supports output and input power warnings. Since the power computation itself is implemented in FW, the warning detection is also performed in FW. The following PMBus commands are used for the power warnings: POUT_OP_WARN_LIMIT defines the threshold for the output power warning •...
Page 239: Temperature Faults
XDPP1100 technical reference manual Digital power controller Fault handler All of these PMBus commands and their programming are described in section 9.8. 9.1.6 Temperature faults The temperature fault submodule is responsible for the detection of: Overtemperature fault and warning •...
Page 240: Current Sharing Fault
VOUT_MAX_MIN warning is reported on PMBus command STATUS_VOUT bit [3]. 9.1.9 Sync fault The XDPP1100 asserts the sync fault when the external SYNC input is out of range as described in section 7.1.2. The sync fault is reported on PMBus command STATUS_MFR_SPECIFIC bit [7].
Page 241: Loop Fault Latching
XDPP1100 technical reference manual Digital power controller Fault handler 9.1.11 Loop fault latching The loop fault latching submodule is responsible for registering and holding the occurrence of loop faults for use by the shutdown submodule and reporting to the FW. As was shown in...
Page 242: Common Faults
Common fault submodule block diagram 9.2.1 Current sense tracking fault The XDPP1100 supports a current sense error tracking fault as described in section 3.2.2.3. The error tracking fault is bitwise ORed with all common faults and reported on STATUS_MFR_SPECIFIC bit [4]. The individual fault can be determined by reading the register fault_status_com.
Page 243: Scp Fault
The XDPP1100 is capable of detecting open or missing sense resistors on the VSEN/VREF, VRSEN/VRREF and BVSEN_BVRSEN/BVREF_BVRREF input pairs. The sense configuration consists of an upper and lower sense resistor pair, dividing the sensed voltage into a range suitable for the XDPP1100 inputs, as was shown in Figure 2.
Page 244 XDPP1100 technical reference manual Digital power controller Fault handler fault_block_on_shut block_fault_update fault_shut_irq fault_reg_com[31:0] fault_com_bus[31:0] fault_com_in[31:0] fault_status_com[31:0] [31:0] [31:0] fault_force_com[31:0] 50MHz 2MHz fault_enable_com[31:0] [31:0] [31:0] fault_clear_com[31:0] Note: Set has priority over Reset on SR Flip-Flops Note: Set has priority over reset on SR flip-flops...
Page 245: Fault Interrupts (Irq)
XDPP1100 technical reference manual Digital power controller Fault handler Fault interrupts (IRQ) The fault interrupt generation is shown in Figure 81. From the figure it can be observed that three fault status registers: fault0_status_loop • fault1_status_loop • fault_status_com • are individually bitwise ORed to produce three interrupt signals: fault0_irq •...
Page 246: Fault Shutdown
[31:0] faultcm_shut fault_reg_com[31:0] fault_shut_clr_com fault_shut_clr_all Figure 83 Fault shutdown block diagram The XDPP1100 supports two different fault-based shutdown timings: Aligned to the PWM ramp t2 time • Immediate (non-t2 aligned) • User Manual 246 of 562 V 1.0 2021-08-25...
Page 247: Fault Pin Mapping
Loop 1 shutdown event • fault_shut_clr_com clears the common shutdown event • fault_shut_clr_all clears all shutdown events • Fault pin mapping The 40-pin version of the XDPP1100 provides two GPIO-based fault pins: FAULT1 • FAULT2 • User Manual 247 of 562 V 1.0...
Page 248: Fault Registers
XDPP1100 technical reference manual Digital power controller Fault handler By default GPIO0[2] is assigned to FAULT1 and it outputs Loop 0 faults as selected through PMBus page 0 FW_CONFIG_FAULTS[71:8]. Correspondingly, the GPIO1[2] is assigned to FAULT2 and it outputs Loop 1 faults as selected through PMBus Page 1 FW_CONFIG_FAULTS[71:8].
Page 249 XDPP1100 technical reference manual Digital power controller Fault handler Peripheral Field name Access Address Bits Description 2: 4 samples 3: 8 samples fault fault_iout_oc_fault_cnt 7000_3C00h [12:8] Output overcurrent fault count. (Loop 0) Defines the number of consecutive 7000_4000h switching cycles (T...
Page 250 XDPP1100 technical reference manual Digital power controller Fault handler Peripheral Field name Access Address Bits Description 1: 2 T switch 2: 4 T switch 3: 8 T switch fault fault_vin_uv_fault_cnt 7000_3C04h [5:4] Input undervoltage fault count. (Loop 0) Defines the number of consecutive...
Page 251 XDPP1100 technical reference manual Digital power controller Fault handler Peripheral Field name Access Address Bits Description fault_vin_fault_hyst) will reset the count. For the typical case this parameter should be set to a positive voltage. This hysteresis parameter applies to all V faults and warnings as shown below.
Page 252 XDPP1100 technical reference manual Digital power controller Fault handler Peripheral Field name Access Address Bits Description below (VOUT_OV_FAULT_LIMIT- fault_vout_fault_hyst) will reset the count. For the typical case this parameter should be set to a positive voltage. This hysteresis parameter applies...
Page 253 XDPP1100 technical reference manual Digital power controller Fault handler Peripheral Field name Access Address Bits Description should be set to a positive current. This hysteresis parameter applies to all I faults and warnings as shown below. IIN_OC_FAULT: Asserted when I...
Page 254 XDPP1100 technical reference manual Digital power controller Fault handler Peripheral Field name Access Address Bits Description Asserted when I is greater than MFR_IOUT_OC_FAST_FAULT_LIMIT Deasserted when I is less than or equal to (MFR_IOUT_OC_FAST_FAULT_LIMI T-fault_iout_oc_fault_hyst) LSB = 0.25 A, range = -8.0 to +7.75 A...
Page 255 XDPP1100 technical reference manual Digital power controller Fault handler Peripheral Field name Access Address Bits Description temperature faults and warnings, as shown below. PTC OT_FAULT: Asserted when temp. is greater than fault_ot_fault_thresh Deasserted when temp. is less than (fault_ot_fault_thresh +...
Page 256 XDPP1100 technical reference manual Digital power controller Fault handler Peripheral Field name Access Address Bits Description LSB = 1 TSADC code, range = -16 to +15 TSADC codes fault_shut_mask_loop 7000_3C0Ch [31:0] Shutdown mask for Loop faults. fault (Loop 0) Individual faults are enabled for...
Page 257 XDPP1100 technical reference manual Digital power controller Fault handler Peripheral Field name Access Address Bits Description 1, the immediate shutdown behavior of fault_shut_mask_loop is implemented. This register should not be written directly but rather through PMBus command FW_CONFIG_FAULTS bits [199:168], which have a 1 to 1 mapping with bits [31:0] of this register.
Page 258 XDPP1100 technical reference manual Digital power controller Fault handler Peripheral Field name Access Address Bits Description 7: VIN_UV_FAULT 8: VIN_UV_WARN 9: IOUT_OC_FAULT 10: IOUT_OC_LV_FAULT 11: IOUT_OC_WARN 12: IOUT_UC_FAULT 13: MFR_IOUT_OC_FAST 14: IIN_OC_FAULT 15: IIN_OC_WARN 16: OT_FAULT 17: OT_WARN 18: UT_FAULT...
Page 259 XDPP1100 technical reference manual Digital power controller Fault handler Peripheral Field name Access Address Bits Description sense resistor divider. Computed by FW from PMBus command as follows: fault_vout_uvp_fault_thresh = Int(VOUT_UV_FAULT_LIMIT(U16- X.X) * VOUT_SCALE_LOOP(U0.16) * 200 / (2^X * 2^16)) where X = negative of VOUT_MODE exponent LSB = 5 mV, range = 0.0 to 5.115 V...
Page 260 XDPP1100 technical reference manual Digital power controller Fault handler Peripheral Field name Access Address Bits Description LSB = 125 mV, range = 0.0 to 127.875 V fault fault_vin_uv_warn_thre 7000_3C34h [9:0] Input undervoltage warning (Loop 0) threshold. 7000_4034h Computed by FW from PMBus...
Page 261 XDPP1100 technical reference manual Digital power controller Fault handler Peripheral Field name Access Address Bits Description 2^(IOUT_UC_FAULT_LIMIT[15:11])) LSB = 1 A, range = -128 to +127 A fault fault_mfr_iout_oc_fast_ 7000_3C48h [7:0] Fast output overcurrent fault thresh (Loop 0) threshold. 7000_4048h...
Page 262 XDPP1100 technical reference manual Digital power controller Fault handler Peripheral Field name Access Address Bits Description fault fault_ut_fault_thresh 7000_3C5Ch [9:0] Undertemperature fault threshold (Loop 0) in TSADC codes. This threshold is 7000_405Ch computed by FW based on the (Loop 1)
Page 263 XDPP1100 technical reference manual Digital power controller Fault handler Peripheral Field name Access Address Bits Description 5: VIN_OV_FAULT 6: VIN_OV_WARN 7: VIN_UV_FAULT 8: VIN_UV_WARN 9: IOUT_OC_FAULT 10: IOUT_OC_LV_FAULT 11: IOUT_OC_WARN 12: IOUT_UC_FAULT 13: MFR_IOUT_OC_FAST 14: IIN_OC_FAULT 15: IIN_OC_WARN 16: OT_FAULT...
Page 264 XDPP1100 technical reference manual Digital power controller Fault handler Peripheral Field name Access Address Bits Description fault fault_clear_loop 7000_3C74h [31:0] Fault force clear register. When the (Loop 0) bit corresponding to a 7000_4074h fault/warning is set to 1, that (Loop 1)
Page 265 XDPP1100 technical reference manual Digital power controller Fault handler Peripheral Field name Access Address Bits Description 12: IOUT_UC_FAULT 13: MFR_IOUT_OC_FAST 14: IIN_OC_FAULT 15: IIN_OC_WARN 16: OT_FAULT 17: OT_WARN 18: UT_FAULT 19: UT_WARN 20: POWER_LIMIT_MODE 21: ISHARE_FAULT 22: VOUT_MAX_MIN_WARN 23: SYNC_FAULT...
Page 266 XDPP1100 technical reference manual Digital power controller Fault handler Peripheral Field name Access Address Bits Description fault fault_iout_cc_adj 7000_3C80h [14:1] Status register indicating (Loop 0) magnitude of constant current 7000_4080h mode output voltage adjustment (Loop 1) referenced to the VSEN pin (i.e.,...
Page 267 XDPP1100 technical reference manual Digital power controller Fault handler Peripheral Field name Access Address Bits Description faultcom fault_block_on_shut 7000_5404h Defines whether faults continued to be reported after an initial shutdown fault had occurred and triggered shutdown. 0: Fault reporting continues after shutdown fault.
Page 268 XDPP1100 technical reference manual Digital power controller Fault handler Peripheral Field name Access Address Bits Description faultcom fault_shut_clr_com 7000_5410h Clears shutdown faults in fault_reg_com when set high. This field should not be written until after FW has completed shutdown- related cleanup (e.g., V...
Page 269 XDPP1100 technical reference manual Digital power controller Fault handler Peripheral Field name Access Address Bits Description 1: Unused 2: IS1 (ISEN) tracking fault 3: IS2 (BISEN) tracking fault 4: Fbal1 fault 5: IS1 (ISEN) PCL fault 6: IS1 (ISEN) SCP fault...
Page 270 XDPP1100 technical reference manual Digital power controller Fault handler Peripheral Field name Access Address Bits Description the position of the first “1” searching from the LSB. Fault0_status_loop[31:0] reports in the range 0 to 31, fault1_status_loop[31:0] reports in the range 32 to 63 and fault_status_com[31:0] reports in the range 224 to 255.
Page 271: Fault Pmbus Commands
XDPP1100 technical reference manual Digital power controller Fault handler Fault PMBus commands Table 67 Fault-related PMBus command descriptions Command name Access Length Address Bits Description VOUT_SCALE_LOOP Word [15:0] Scales VOUT_COMMAND and other V related commands for the external resistor divider between V and VSEN.
Page 272 XDPP1100 technical reference manual Digital power controller Fault handler Command name Access Length Address Bits Description VOUT_UV_FAULT_LIMIT Word [15:0] Sets the value of the output voltage that causes an output undervoltage fault. The data bytes are formatted according to the setting of the VOUT_MODE command.
Page 273 XDPP1100 technical reference manual Digital power controller Fault handler Command name Access Length Address Bits Description specified by delay bits [2:0] then if still operating in current limiting, shut down and respond according to retry bits [5:3] 3: Shut down and respond according to...
Page 274 XDPP1100 technical reference manual Digital power controller Fault handler Command name Access Length Address Bits Description 3: Shut down SR until fault condition removed [5:3]: Retry setting 0: Remain disabled until fault cleared 1 to 6: Attempt to restart [5:3] times with...
Page 275 XDPP1100 technical reference manual Digital power controller Fault handler Command name Access Length Address Bits Description UT_FAULT_RESPONSE Byte [7:0] Instructs the device on what action to take in response to an overtemperature fault. [7:6]: Response 0: Continue operation without interruption...
Page 276 XDPP1100 technical reference manual Digital power controller Fault handler Command name Access Length Address Bits Description between restart attempts, unit defined by FW_CONFIG_FAULTS command VIN_OV_WARN_LIMIT Word [15:0] Sets the value of the input voltage that causes an input overvoltage warning.
Page 277 XDPP1100 technical reference manual Digital power controller Fault handler Command name Access Length Address Bits Description 0: Continue operation without interruption 1: Continue operation for time specified by delay bits [2:0] then if fault condition still present, shut down and respond...
Page 278 XDPP1100 technical reference manual Digital power controller Fault handler Command name Access Length Address Bits Description between restart attempts, unit defined by FW_CONFIG_FAULTS command TOFF_MAX_WARN_LIMIT Word [15:0] Sets an upper limit, in ms, on how long the unit can attempt to power down the output without reaching 12.5 percent of...
Page 279 XDPP1100 technical reference manual Digital power controller Fault handler Command name Access Length Address Bits Description [14] I : An output current or output power fault or warning has occurred. [13] INPUT: An input voltage, input current or input power fault of warning has occurred.
Page 280 XDPP1100 technical reference manual Digital power controller Fault handler Command name Access Length Address Bits Description STATUS_TEMPERATURE Byte [7:0] Returns one data byte with contents as follows: [7]: OT_FAULT [6]: OT_WARNING [5]: UT_WARNING [4]: UT_FAULT [3]: Reserved [2]: Reserved [1]: Reserved...
Page 281 XDPP1100 technical reference manual Digital power controller Fault handler Command name Access Length Address Bits Description [3:2] Iout_Delay_Unit: Time unit for retry responses. 0: 1 ms 1: 4 ms 2: 16 ms 3: 256 ms [5:4] Vin_Delay_Unit: Time unit for retry responses.
Page 282 XDPP1100 technical reference manual Digital power controller Fault handler Command name Access Length Address Bits Description 1: Common fault 2: TON_MAX_FAULT 3: TOFF_MAX_WARN 4: PIN_OP_WARN 5: POUT_OP_WARN 6: VIN_INSUFFICIENT 7 to 31: Unused [103:72] Fault_enable_mask_loop_hw[31:0]: Masking for loop hardware faults. Set a bit to 1 to disable PMBus reporting on the corresponding fault.
Page 283 XDPP1100 technical reference manual Digital power controller Fault handler Command name Access Length Address Bits Description corresponding fault. 0: Unused 1: Unused 2: IS1 (ISEN) tracking fault 3: IS2 (BISEN) tracking fault 4: Fbal1 fault 5: IS1 (ISEN) PCL fault...
Page 284 XDPP1100 technical reference manual Digital power controller Fault handler Command name Access Length Address Bits Description 18: UT_FAULT 19: UT_WARN 20: POWER_LIMIT_MODE 21: ISHARE_FAULT 22: VOUT_MAX_MIN_WARN 23: SYNC_FAULT 24 to 31: Unused MFR_IOUT_OC_FAST_FAU Byte [7:0] Instructs the device on what action to...
Page 285: Current Sharing (I )
10.1 Current sharing circuit For active current sharing, the XDPP1100 IMON pin is used to share the current information between power supplies. An example system with two XDPP1100-based power supplies connected in parallel is shown in Figure...
Page 286 XDPP1100 technical reference manual Digital power controller Current sharing (ISHARE) The IMON pin is connected to: Current DAC output; in the current sharing mode it outputs a current proportional to the load current share • of the individual supply TSADC input; in the current sharing mode it allows measurement of the voltage across the resistor •...
Page 287: Current Sharing Pi Filter
XDPP1100 technical reference manual Digital power controller Current sharing (ISHARE) supply current is given in amps. As an example, if an individual supply can handle 50 A, then the ishr_scale value is as given in Equation (10.4). (10.3) ��ℎ��_�� = �� (16 ∗...
Page 288: Current Sharing Fw Override
XDPP1100 technical reference manual Digital power controller Current sharing (ISHARE) Register values ishr_kp and ishr_ki larger than 55 are clamped to 55. Figure 87 shows an example magnitude response with the following values: ishr_kp = 24 • ishr_ki = 16 •...
Page 289: Current Sharing Pin, Dac And Adc Configuration
• ishare o IMON pin and PWM6 for XDPP1100-Q024 (Figure o IMON pin and PWM6 or PWM11 for XDPP1100-Q040 (Figure For the second R connection with module sequencing, a FW patch is available. It drives the R negative...
Page 290: Current Sharing Registers
XDPP1100 technical reference manual Digital power controller Current sharing (ISHARE) OUT1 Unit 1 XDPP1100 OUT1 Ishare IMON Load ishare PWM6 OUT2 Unit 2 XDPP1100 OUT2 Ishare IMON ishare PWM6 Figure 88 Active current sharing example with two units in parallel while start-up sequencing is applied 10.6...
Page 291 XDPP1100 technical reference manual Digital power controller Current sharing (ISHARE) Peripheral Field name Access Address Bits Description common ishr_scale 7000_3020h [4:0] Used for current sharing, this register defines a pre-scale gain applied to the internal current telemetry before sending to the current output DAC on the IMON pin.
Page 292 XDPP1100 technical reference manual Digital power controller Current sharing (ISHARE) Peripheral Field name Access Address Bits Description adjust 1: Use ishr_fw_adj common idac_fw_frc 7000_3088h [9:0] When idac_fw_en is high, this register overrides the HW current DAC output with a FW-controlled setting.
Page 293: Current Sharing Pmbus Commands
XDPP1100 technical reference manual Digital power controller Current sharing (ISHARE) Peripheral Field name Access Address Bits Description 0: 0.6 V reference (test only) 1: PRISEN 2: IMON 3: ATSEN 4: BTSEN 5: XADDR1 unfiltered 6: XADDR2 unfiltered 7: MUX1 (see ts_tsmuxctrl1)
Page 294: Current Balance
• Transient timing with respect to the phase timing • The XDPP1100 supports interleaved topologies of a single loop with up to two phases driving a common output voltage. Figure 89 shows an example of an interleaved HBCT topology, where the inductor currents in L OUT1 may become imbalanced.
Page 295: Current Balance Pi Filter
XDPP1100 technical reference manual Digital power controller Current balance (IBAL) isp2_iout_cavg BISEN, S8.4 PI Filter S9.4 ibal_duty_adj clk_fsw ibal_fw_adj S-1.9 S-1.9 To PWM Ramp 0 isp1_iout_cavg ISEN, S8.4 kp_ibal ibal_fw_en ki_ibal Figure 90 Simplified current balance block diagram The circuit receives as its input the cycle-averaged current outputs from ISP1 and ISP2, which correspond to the ISEN and BISEN sensed currents.
Page 296: Current Balance Fw Override
XDPP1100 technical reference manual Digital power controller Current balance (IBAL) set in register ibal_en_thresh) the accumulated current error is held at its last value rather than being reset to Figure 91 shows an example magnitude response with the following values: kp_ibal = 48 •...
Page 297: Current Balance Registers
XDPP1100 technical reference manual Digital power controller Current balance (IBAL) 11.4 Current balance registers The relevant current balance registers and their descriptions are provided in Table Table 73 Current balance register descriptions Peripheral Field name Access Address Bits Description common...
Page 298: Flux Balance
Each method has drawbacks, adding either BOM cost or board area, or reducing efficiency. To overcome these drawbacks while obtaining flux balance, the XDPP1100 contains two flux balance circuits to support interleaved designs. It is capable of maintaining volt-second balance between half-cycles by using measured even/odd...
Page 299 XDPP1100 technical reference manual Digital power controller Flux balance (FBAL) vbal_mode_sel fbal_max U-2.10 vsum vdt_plus_tdv vrs_vrect_even PI Filter Clamp U12.0 fbal_duty_adj S-1.11 fbal_fw_adj applied to odd vdiff vrs_vrect_odd kp_fbal half cycles only S-1.9 U12.0 ki_fbal fbal_fw_en tsum cnt_vrscomp_even U11.0 fbal_time_only...
Page 300: Flux Balance Pi Filter
XDPP1100 technical reference manual Digital power controller Flux balance (FBAL) o Loop 0 is operating (start-up or regulation) o interleave operation enabled via PMBus command PAGE0.FW_CONFIG_REGULATION.INTERLEAVE_ENABLE=1 If flux balance is not desired under the above conditions, the adjustment can be disabled by one of the...
Page 301: Flux Balance Fw Override
Therefore, due to the inability to accurately measure the primary-side pulse width in DCM operation it is recommended to disable flux balance in this mode. The XDPP1100 provides several registers to control the flux balance behavior in and around DCM operation. These registers are:...
Page 302: Flux Balance Fault Detection
XDPP1100 technical reference manual Digital power controller Flux balance (FBAL) fbal_dcm_thresh, which sets the current threshold at which the flux balance function is disabled due to the • DCM operation; a setting of 63 disables this feature (not recommended) fbal_dcm_dis_cnt, which defines the number of consecutive current samples (at F rate) below •...
Page 303: Flux Balance Registers
XDPP1100 technical reference manual Digital power controller Flux balance (FBAL) In the case of absolute error method, register fbal_delta_abs_en selects where the absolute value of the error is applied, either before or after the LPF. The LPF BW programming is performed via register fbal_lpf_kpshift...
Page 304 XDPP1100 technical reference manual Digital power controller Flux balance (FBAL) Peripheral Field name Access Address Bits Description settings greater than 55 are clamped to 55. Note also that flux balancing requires that duty-cycle locking is enabled by rampX_dutyc_lock. ki_exp = ki_fbal[5:3]...
Page 305 XDPP1100 technical reference manual Digital power controller Flux balance (FBAL) Peripheral Field name Access Address Bits Description Kp = 2^-Kpshift F3db = [kp/(1-kp)] * F / 2pi switch common fbal_delta_abs_en 7000_3030h [13] In flux balance computation, determines whether absolute value applied to the error before or after the LPF.
Page 306 XDPP1100 technical reference manual Digital power controller Flux balance (FBAL) Peripheral Field name Access Address Bits Description common fbal1_fw_en 7000_307Ch Enables FW-controlled flux/voltage balance loop via fbal1_fw_adj. 0: Use HW-computed flux/voltage balance adjust 1: Use fbal1_fw_adj common fbal2_fw_adj 7000_3080h [7:0]...
Page 307: Fan Support
FAN_CONFIG_1_2[7] enables/disables FAN1 • FAN_CONFIG_1_2[3] enables/disables FAN2 • 13.1 Fan PWM output The XDPP1100 provides HW support for up to two fan PWM outputs, identified as: FAN1_PWM • FAN2_PWM • The pin programming options for these fan PWM outputs are shown in Table 78.
Page 308: Duty-Cycle Mode
XDPP1100 technical reference manual Digital power controller Fan support Table 80 Fan PWM operating mode selection fan_mode Fan operating mode Duty-cycle mode Current mode 13.1.1 Duty-cycle mode In duty-cycle mode, the user directly programs the PWM duty cycle through one of the following methods: Register fan_duty programs the duty-cycle output in fractional duty cycle •...
Page 309: Fan Speed Input
Fan support Figure 97 Current mode duty cycle with fan_duty_min greater than (fan_imin/fan_imax) 13.2 Fan speed input The XDPP1100 provides HW support for up to two fan speed tachometer inputs, identified as: FAN1_TACH • FAN2_TACH • The pin programming options for these fan tachometer inputs are shown in...
Page 310: Fan Registers
XDPP1100 technical reference manual Digital power controller Fan support Fan speed is reported on: Register fan_speed with range 0 to 32K RPM and 8 RPM resolution • PMBus commands: • o READ_FAN_SPEED_1 o READ_FAN_SPEED_2 These PMBus commands are in LINEAR11 format with exponent defined by PMBus command FW_CONFIG_TELEMETRY.READ_FAN_EXP.
Page 311 XDPP1100 technical reference manual Digital power controller Fan support Peripheral Field name Access Address Bits Description fan_tach_ppr 7000_4400h [27:26] Tachometer pulses per revolution (Fan 1) (ppr). 7000_4800h 0: 1 ppr (Fan 2) 1: 2 ppr 2: 3 ppr 3: 4 ppr...
Page 312: Fan Pmbus Commands
XDPP1100 technical reference manual Digital power controller Fan support 13.4 Fan PMBus commands Table 84 Fan PMBus commands Peripheral Field name Access Address Bits Description FAN_CONFIG_1_2 Byte FAN1 enable. 0: FAN1 disabled 1: FAN1 enabled FAN1 control mode select. Not supported by default FW patch.
Page 313 XDPP1100 technical reference manual Digital power controller Fan support Peripheral Field name Access Address Bits Description register fan_mode. Format is LINEAR11 with exponent of -8 recommended. C000h = 0/256 = 0.0 percent C001h = 1/256 = 0.390625 percent C002h = 2/256 = 0.78125 percent …...
Page 314: Io Muxing
This chapter describes the programming of the multiple digital IO pins and describes the relevant register settings in more detail. The XDPP1100 contains several programmable multipurpose digital IO pins, and depending on the variant the pin numbers are: 21, for the Q040 variant •...
Page 315 XDPP1100 technical reference manual Digital power controller IO muxing Table 85 Multipurpose IO pin function programming <pin_name>_func[2:0] XDPP1100-Q040 XDPP1100-Q024 Pin name Pin number Pin number FAULT1 FAULT1/GPIO0[2] GPIO0[2] GPIO1[2] External sync FAN2_PWM SDA2 UART_RX FAULT2 FAULT2/GPIO1[2] GPIO0[2] GPIO1[2] External sync...
Page 316: Digital Input Priority
The GPIO deglitch function only applies to GPIO0[0] and GPIO1[0] assigned to EN and BEN by default ROM FW. This is due to an erratum affecting all currently available XDPP1100 versions. Therefore, it should be noted that this section describes the actual behavior rather than the intended behavior.
Page 317: Digital Io Buffer Programming
XDPP1100 technical reference manual Digital power controller IO muxing A deglitcher is provided on the GPIO0 and GPIO1 inputs. An individual GPIO input bit must be stable for the time defined by register gpio_dly in order for a transition to pass through the deglitcher. A setting of 0 on gpio_dly disables the deglitcher on all GPIO inputs.
Page 318 XDPP1100 technical reference manual Digital power controller IO muxing Peripheral Field name Access Address Bits Description common ben_pu_n 7000_3004h Pin BEN weak pull-up enable. 0: Pull-up enabled 1: Pull-up disabled common ben_ppen 7000_3004h Pin BEN output buffer CMOS/open drain select.
Page 319 XDPP1100 technical reference manual Digital power controller IO muxing Peripheral Field name Access Address Bits Description 3: SYNC, digital IO 4: FAN2_PWM, digital output 5: SDA2, digital IO 6: UARTRXD, digital input 7: Not used common fault1_pd 7000_3004h [21] Pin FAULT1 weak pull-down enable.
Page 320 XDPP1100 technical reference manual Digital power controller IO muxing Peripheral Field name Access Address Bits Description common imon_pu_n 7000_3008h Pin IMON weak pull-up enable. 0: Pull-up enabled 1: Pull-up disabled common imon_ppen 7000_3008h Pin IMON output buffer CMOS/open drain select.
Page 321 XDPP1100 technical reference manual Digital power controller IO muxing Peripheral Field name Access Address Bits Description 4: FAN1_PWM, digital output 5 to 7: Not used common sync_pd 7000_3008h [21] Pin SYNC weak pull-down enable. 0: Pull-down disabled 1: Pull-down enabled...
Page 322 XDPP1100 technical reference manual Digital power controller IO muxing Peripheral Field name Access Address Bits Description common pwm2_func 7000_300Ch [8:6] Pin PWM2 function definition. 0: PWM2, digital output 1: GPIO0[7], digital IO 2: GPIO1[7], digital IO 3: SYNC, digital IO...
Page 323 XDPP1100 technical reference manual Digital power controller IO muxing Peripheral Field name Access Address Bits Description 0: Open drain output 1: CMOS output common pwm5_func 7000_300Ch [26:24] Pin PWM5 function definition. 0: PWM5, digital output 1: GPIO0[3], digital IO 2: GPIO1[3], digital IO...
Page 324 XDPP1100 technical reference manual Digital power controller IO muxing Peripheral Field name Access Address Bits Description common pwm7_pu_n 7000_3010h [10] Pin PWM7 weak pull-up enable. 0: Pull-up enabled 1: Pull-up disabled common pwm7_ppen 7000_3010h [11] Pin PWM7 output buffer CMOS/open drain select.
Page 325 XDPP1100 technical reference manual Digital power controller IO muxing Peripheral Field name Access Address Bits Description common pwm10_pd 7000_3010h [27] Pin PWM10 weak pull-down enable. 0: Pull-down disabled 1: Pull-down enabled common pwm10_pu_n 7000_3010h [28] Pin PWM10 weak pull-up enable.
Page 326 XDPP1100 technical reference manual Digital power controller IO muxing Peripheral Field name Access Address Bits Description 3: SYNC, digital IO 4: FAN1_TACH, digital input 5 to 7: Not used common pwm12_pd 7000_3014h Pin PWM12 weak pull-down enable. 0: Pull-down disabled...
Page 327 XDPP1100 technical reference manual Digital power controller IO muxing Peripheral Field name Access Address Bits Description 01h: GPIO1[0] deglitch enabled 02-FFh: Not allowed User Manual 327 of 562 V 1.0 2021-08-25...
Page 328: Central Processing Unit Subsystem
Figure 98 CPUS block diagram The XDPP1100 CPUS is based on a multilayer Arm® AMBA® bus protocol, in which two AHB masters (Cortex®-M0 and DMA) access all peripherals through an Arm® bus matrix. The main features of the bus matrix are: It allows concurrent access when the target peripherals are different •...
Page 329: Cpus Bus Matrix
XDPP1100 technical reference manual Digital power controller Central processing unit subsystem A DMA is available to handle autonomous data transfers, and to avoid BW losses on the microcontroller in case of data movements. AHB to APB Arm® bridges handle the protocol conversion between the two AMBA® layers.
Page 330: Cpu Interrupt Sources
XDPP1100 technical reference manual Digital power controller Central processing unit subsystem Reference Manual (TRM). These documents are available from the Arm® website (www.arm.com). Please note that downloading the ARMv6-M Architecture Reference Manual requires a registration process. A simplified block diagram of the Cortex®-M0 is shown in...
Page 331 XDPP1100 technical reference manual Digital power controller Central processing unit subsystem Table 89 Cortex®-M0 interrupt table Interrupt Description External index CMSYS interrupt Memory address source number RESET Reset – 0000_0004h 0000_0008h HARDFAULT Hard fault 0000_000Ch SVCALL SV call 0000_002Ch PENDSV...
Page 332: Cortex®-M0 Memory Map
XDPP1100 technical reference manual Digital power controller Central processing unit subsystem INT31 UART 0000_00BCh Every interrupt INT31-INT0 can be programmed to be used as NMI, by configuring the NMI source-select register NMI_SRC_EN in SCU. 15.2.2 Cortex®-M0 memory map The memory map accessible by Cortex®-M0 is described in...
Page 333: Remapping Feature
Cortex®-M0 has the interrupt table hard-coded in the lowest address space (0000_0004h - 0000_00BCh) that is normally occupied by a non-volatile memory (NVM). In the case of XDPP1100 this is the 80 kB ROM. This means that all interrupt serving routines (ISRs) are hard-coded and fixed.
Page 334 XDPP1100 technical reference manual Digital power controller Central processing unit subsystem Table 91 Cortex®-M0 memory map (remap = 1) Address range Size Peripheral Bus matrix master 0000_0000h - 0000_3FFFh 16 kB RAM1 0000_4000h - 0000_7FFFh 16 kB RAM1 (replica) 0000_8000h - 0000_BFFFh...
Page 335: Clock And System Controller
XDPP1100 technical reference manual Digital power controller Central processing unit subsystem 6000_0000h - 600F_FFFFh WDT, DTIMER1/2/3, GPIO0/1 6010_0000h - 6FFF_FFFFh Reserved 7000_0000h - 7007_FFFFh BIF REGFILE (CONTROL) 7008_0000h - 700F_FFFFh PMBus/CRC/I 7010_0000h - DFFF_FFFFh Reserved E000_0000h - E00F_FFFFh Cortex®-M0 private peripherals...
Page 336 XDPP1100 technical reference manual Digital power controller Central processing unit subsystem Register name Field name Access Address Bits Description 0: CPUS external wakeup is disabled 1: CPUS external wakeup is enabled CPUS_CFG USR_CNFG0 4000_0000h Reserved CPUS_CFG USR_CNFG1 4000_0000h Reserved CPUS_CFG...
Page 337 XDPP1100 technical reference manual Digital power controller Central processing unit subsystem Register name Field name Access Address Bits Description 1: Invalid setting CPUS_CFG EN_AUX_EXTWKUP 4000_0000h [20] Enable auxiliary external wakeup source to wake up CPUS when in the power-down or hibernate state.
Page 338 XDPP1100 technical reference manual Digital power controller Central processing unit subsystem Register name Field name Access Address Bits Description CPUS_CFG_SE USR_CNFG1 4000_0004h Reserved CPUS_CFG_SE USR_CNFG2 4000_0004h Reserved CPUS_CFG_SE USR_CNFG3 4000_0004h Reserved CPUS_CFG_SE USR_CNFG4 4000_0004h Reserved CPUS_CFG_SE USR_CNFG5 4000_0004h Reserved CPUS_CFG_SE...
Page 339 XDPP1100 technical reference manual Digital power controller Central processing unit subsystem Register name Field name Access Address Bits Description CPUS_CFG_SE EN_AUX_EXTWKUP 4000_0004h [20] Enable auxiliary external wakeup source to wake up CPUS when in the power-down or hibernate state. 0: No change to existing value...
Page 340 XDPP1100 technical reference manual Digital power controller Central processing unit subsystem Register name Field name Access Address Bits Description CPUS_CFG_CL USR_CNFG3 4000_0008h Reserved CPUS_CFG_CL USR_CNFG4 4000_0008h Reserved CPUS_CFG_CL USR_CNFG5 4000_0008h Reserved CPUS_CFG_CL USR_CNFG6 4000_0008h [10] Reserved CPUS_CFG_CL OTP_KEEP_PWR_S 4000_0008h [11] Controls OTP APB peripheral register reset on a soft reset.
Page 341 XDPP1100 technical reference manual Digital power controller Central processing unit subsystem Register name Field name Access Address Bits Description CPUS_CFG_CL EN_PMBUS_WKUP 4000_0008h [21] Enable internal source PMBUS_IRQ to wake up CPUS when in the power-down or hibernate state. 0: No change to existing value...
Page 342 XDPP1100 technical reference manual Digital power controller Central processing unit subsystem Register name Field name Access Address Bits Description NMI_SRC_EN WDT_NMI_EN 4000_000Ch [12] WDT NMI control. 0: Disabled 1: Enabled NMI_SRC_EN DTIMER1_0_NMI_E 4000_000Ch [13] DTIMER_11 NMI control. 0: Disabled 1: Enabled...
Page 343: Clock Generator Unit
[31:0] Spare register 15.3.2 Clock generator unit The clock generation unit (CGU) generates and controls the clock signals of the CPUS section of the XDPP1100 device. It provides the following main system functions: Clock schemes and clock generation • Clock division and control •...
Page 344 XDPP1100 technical reference manual Digital power controller Central processing unit subsystem FCLK CPUS_EN & SCLK WKUPIN GATEHCLKs CortexM0IM & AUX_WKUPIN HCLK SLEEDPDEEP & Kill_me_hardly DCLK Ram1_clk HOSC_clk RAM1 & HOSC & Ram2_clk RAM2 & Kill_me_softly HOSC_clk_gated Rom_clk & CNFG Cnfg_clk...
Page 345: Clock Dividers
XDPP1100 technical reference manual Digital power controller Central processing unit subsystem CPUS clock typical and maximum frequencies and related modules are shown in Table Table 93 CPUS clock domains Clock name Module name Typ. freq. (MHz) Max. freq. (MHz) hosc_clk...
Page 346: Clock Gating
XDPP1100 technical reference manual Digital power controller Central processing unit subsystem The watchdog and timer clock dividers scale the counter clocks, keeping the interface on the AMBA® bus clock unchanged, and allowing the time constant of the counters to be extended to bigger time intervals. This is particularly effective for the watchdog, for example, where the timer interval is in the range of seconds.
Page 347: Primary-Source Clock Gating
XDPP1100 technical reference manual Digital power controller Central processing unit subsystem DeepSleep mask Sleep mask SLEEPDEEP Clock enable reg GATEHCLK EN_CLK CLK_IN CLK_OUT Figure 101 Clock gating structure 15.3.2.3 Primary-source clock gating The primary-source clock gating has the structure shown in...
Page 348: Cgu Registers
XDPP1100 technical reference manual Digital power controller Central processing unit subsystem DeepSleep mask Sleep mask (bit 0) (bit 0) SLEEPDEEP Clock enable reg (bit 0) GATEHCLK WKUPIN & Kill_me_softly Hosc SW clk gating control reg HRESETn Kill_me_hardly >=1 Hosc HW clk gating control reg...
Page 349 XDPP1100 technical reference manual Digital power controller Central processing unit subsystem Register name Field name Access Address Bits Description CPU_CLK_DIV_ cpuclk_div 4000_2004h [4:0] This register configures the divider CTRL of cpu_clk. The divide ratio is equal to cpuclk_div[4:0] + 1. For example,...
Page 350 XDPP1100 technical reference manual Digital power controller Central processing unit subsystem Register name Field name Access Address Bits Description generates a default clock frequency of pmbus_kernel_clk = alpha_clk/1. KRN_CLK_DIV_ otp_kernel_clk_div 4000_2008h [29:25] This register configures the divider CTRL of the OTP kernel clock. The divide ratio is equal to otp_kernel_clk_div[4:0] + 1.
Page 351 XDPP1100 technical reference manual Digital power controller Central processing unit subsystem Register name Field name Access Address Bits Description 1: Clock “dma_clk” is live CLK_EN_CTRL cnfg_otp1_w_clk_g 4000_2010h Enable bit for the clock cnfg_otp1_w_clk and cnfg_clk. 0: Clock “cnfg_otp1_w_clk” is off 1: Clock “cnfg_otp1_w_clk”...
Page 352 XDPP1100 technical reference manual Digital power controller Central processing unit subsystem Register name Field name Access Address Bits Description CLK_EN_CTRL dtimer2_clk_g 4000_2010h [18] Enable bit for the clock dtimer2_clk and apb_per_clk. 0: Clock “dtimer2_clk” is off 1: Clock “dtimer2_clk” and...
Page 353 XDPP1100 technical reference manual Digital power controller Central processing unit subsystem Register name Field name Access Address Bits Description CLK_EN_CTRL otp_kernel_clk_g 4000_2010h [27] Enable bit for the clock otp_kernel_clk. 0: Clock “otp_kernel_clk” is off 1: Clock “otp_kernel_clk” is live CLK_SLEEP_M...
Page 354 XDPP1100 technical reference manual Digital power controller Central processing unit subsystem Register name Field name Access Address Bits Description 1: Clock “dma_clk” is gated when CM0 is in sleep state CLK_SLEEP_M se_cnfg_otp1_w_cl 4000_2014h Enable cnfg_otp1_w_clk clock SK_CNFG gating when Cortex®-M0 enters sleep state.
Page 355 XDPP1100 technical reference manual Digital power controller Central processing unit subsystem Register name Field name Access Address Bits Description 0: Clock “bif_per_i2c_clk” is not gated by CM0 power state status 1: Clock “bif_per_i2c_clk” is gated when CM0 is in sleep state...
Page 356 XDPP1100 technical reference manual Digital power controller Central processing unit subsystem Register name Field name Access Address Bits Description CLK_SLEEP_M se_gpio1_clk_g 4000_2014h [22] Enable gpio1_clk clock gating when SK_CNFG Cortex®-M0 enters sleep state. 0: Clock “gpio1_clk” is not gated by CM0 power state status 1: Clock “gpio1_clk”...
Page 357 XDPP1100 technical reference manual Digital power controller Central processing unit subsystem Register name Field name Access Address Bits Description CLK_DEEP_SL dse_dma_clk_g 4000_2018h Enable dma_clk clock gating when EEP_MSK_CNF Cortex®-M0 enters deep sleep state. 0: Clock “dma_clk” is not gated by CM0 power state status 1: Clock “dma_clk”...
Page 358 XDPP1100 technical reference manual Digital power controller Central processing unit subsystem Register name Field name Access Address Bits Description CLK_DEEP_SL dse_bif_per_pmbus 4000_2018h [13] Enable bif_per_pmbus_clk clock EEP_MSK_CNF _clk_g gating when Cortex®-M0 enters deep sleep state. 0: Clock “bif_per_pmbus_clk” is not gated by CM0 power state status 1: Clock “bif_per_pmbus_clk”...
Page 359 XDPP1100 technical reference manual Digital power controller Central processing unit subsystem Register name Field name Access Address Bits Description 1: Clock “dtimer3_clk” is gated when CM0 is in deep sleep state CLK_DEEP_SL dse_wdt_clk_g 4000_2018h [20] Enable wdt_clk clock gating when EEP_MSK_CNF Cortex®-M0 enters deep sleep state.
Page 360 XDPP1100 technical reference manual Digital power controller Central processing unit subsystem Register name Field name Access Address Bits Description Note: The primary clock gating is performed if this bit is set. KILL_ME_SOFTLY bit of the HOSC_SW_CLK_GATING_CTRL register is also set. Be sure to...
Page 361 XDPP1100 technical reference manual Digital power controller Central processing unit subsystem Register name Field name Access Address Bits Description 1: Enable “bif_reg_clk” clock CLK_EN_CTRL bif_per_svid_clk_g 4000_2030h [12] Enable the bif_per_svid_clk clock. _SET Note: The CRC32 peripheral is using the SVID slot so this actually controls the CRC32 clock.
Page 362 XDPP1100 technical reference manual Digital power controller Central processing unit subsystem Register name Field name Access Address Bits Description CLK_EN_CTRL gpio1_clk_g 4000_2030h [22] Enable the gpio1_clk clock. _SET 0: Status of “gpio1_clk” clock is not affected 1: Enable “gpio1_clk” clock...
Page 363 XDPP1100 technical reference manual Digital power controller Central processing unit subsystem Register name Field name Access Address Bits Description 0: Status of “hosc_clk” clock is not affected 1: Disable “hosc_clk” clock CLK_EN_CTRL rom_clk_g 4000_2034h Disable the rom_clk clock. _CLR 0: Status of “rom_clk” clock is not affected 1: Disable “rom_clk”...
Page 364 XDPP1100 technical reference manual Digital power controller Central processing unit subsystem Register name Field name Access Address Bits Description 0: Status of “bif_per_pmbus_clk” clock is not affected 1: Disable “bif_per_pmbus_clk” clock CLK_EN_CTRL bif_per_ssp_clk_g 4000_2034h [14] Reserved _CLR CLK_EN_CTRL bif_per_i2c_clk_g 4000_2034h [15] Disable the bif_per_i2c_clk clock.
Page 365 XDPP1100 technical reference manual Digital power controller Central processing unit subsystem Register name Field name Access Address Bits Description CLK_EN_CTRL dtimer2_kernel_clk 4000_2034h [24] Disable the dtimer2_kernel_clk _CLR clock. 0: Status of “dtimer2_kernel_clk” clock is not affected 1: Disable “dtimer2_kernel_clk” clock...
Page 366 XDPP1100 technical reference manual Digital power controller Central processing unit subsystem Register name Field name Access Address Bits Description 1: Enable clock “ram1_clk” sleep state clock gating CLK_SLEEP_M se_ram2_clk_g 4000_2038h Enable ram2_clk clock gating when SK_CNFG_SET the Cortex®-M0 enters sleep state.
Page 367 XDPP1100 technical reference manual Digital power controller Central processing unit subsystem Register name Field name Access Address Bits Description peripheral is using the SVID slot so this actually controls the CRC32 clock. 0: Clock “bif_per_svid_clk” sleep state clock gating status unchanged 1: Enable clock “bif_per_svid_clk”...
Page 368 XDPP1100 technical reference manual Digital power controller Central processing unit subsystem Register name Field name Access Address Bits Description 0: Clock “dtimer2_clk” sleep state clock gating status unchanged 1: Enable clock “dtimer2_clk” sleep state clock gating CLK_SLEEP_M se_dtimer3_clk_g 4000_2038h [19]...
Page 369 XDPP1100 technical reference manual Digital power controller Central processing unit subsystem Register name Field name Access Address Bits Description 1: Disable clock “rom_clk” sleep state clock gating CLK_SLEEP_M se_ram1_clk_g 4000_203Ch [2] Disable ram1_clk clock gating when SK_CNFG_CLR the Cortex®-M0 enters sleep state.
Page 370 XDPP1100 technical reference manual Digital power controller Central processing unit subsystem Register name Field name Access Address Bits Description 0: Clock “bif_reg_clk” sleep state clock gating status unchanged 1: Disable clock “bif_reg_clk” sleep state clock gating CLK_SLEEP_M se_bif_per_svid_clk 4000_203Ch [12]...
Page 371 XDPP1100 technical reference manual Digital power controller Central processing unit subsystem Register name Field name Access Address Bits Description 0: Clock “dtimer1_clk” sleep state clock gating status unchanged 1: Disable clock “dtimer1_clk” sleep state clock gating CLK_SLEEP_M se_dtimer2_clk_g 4000_203Ch [18]...
Page 372 XDPP1100 technical reference manual Digital power controller Central processing unit subsystem Register name Field name Access Address Bits Description 0: Clock “hosc_clk” deep sleep state clock gating status unchanged 1: Enable clock “hosc_clk” deep sleep state gating if hosc_clk clock...
Page 373 XDPP1100 technical reference manual Digital power controller Central processing unit subsystem Register name Field name Access Address Bits Description CLK_DEEP_SL dse_cnfg_otp1_w_c 4000_2040h Enable cnfg_otp1_w_clk clock EEP_MSK_CNF lk_g gating when the Cortex®-M0 enters G_SET deep sleep state. 0: Clock “cnfg_otp1_w_clk” deep...
Page 374 XDPP1100 technical reference manual Digital power controller Central processing unit subsystem Register name Field name Access Address Bits Description CLK_DEEP_SL dse_bif_per_ssp_cl 4000_2040h [14] Reserved EEP_MSK_CNF G_SET CLK_DEEP_SL dse_bif_per_i2c_clk 4000_2040h [15] Enable bif_per_i2c_clk clock gating EEP_MSK_CNF when the Cortex®-M0 enters deep G_SET sleep state.
Page 375 XDPP1100 technical reference manual Digital power controller Central processing unit subsystem Register name Field name Access Address Bits Description 0: Clock “wdt_clk” deep sleep state clock gating status unchanged 1: Enable clock “wdt_clk” deep sleep state clock gating CLK_DEEP_SL dse_gpio0_clk_g...
Page 376 XDPP1100 technical reference manual Digital power controller Central processing unit subsystem Register name Field name Access Address Bits Description 1: Disable clock “ram1_clk” deep sleep state clock gating CLK_DEEP_SL dse_ram2_clk_g 4000_2044h Disable ram2_clk clock gating when EEP_MSK_CNF the Cortex®-M0 enters deep sleep G_CLR state.
Page 377 XDPP1100 technical reference manual Digital power controller Central processing unit subsystem Register name Field name Access Address Bits Description 0: Clock “bif_reg_clk” deep sleep state clock gating status unchanged 1: Disable clock “bif_reg_clk” deep sleep state clock gating CLK_DEEP_SL dse_bif_per_svid_cl...
Page 378 XDPP1100 technical reference manual Digital power controller Central processing unit subsystem Register name Field name Access Address Bits Description CLK_DEEP_SL dse_dtimer1_clk_g 4000_2044h [17] Disable dtimer1_clk clock gating EEP_MSK_CNF when the Cortex®-M0 enters deep G_CLR sleep state. 0: Clock “dtimer1_clk” deep sleep...
Page 379: Reset Generator Unit
XDPP1100 technical reference manual Digital power controller Central processing unit subsystem Register name Field name Access Address Bits Description 1: Disable clock “gpio1_clk” deep sleep state clock gating 15.3.3 Reset generator unit The reset generator unit (RGU) implements the reset scheme of the CPUS. The CPUS reset scheme is shown in Figure 103.
Page 380: Reset Sources
XDPP1100 technical reference manual Digital power controller Central processing unit subsystem 15.3.3.1 Reset sources The CPUS supports multiple reset sources: External reset • CPUS_EN reset • SW_PWDN reset • WDT reset • CPU system reset • Soft reset • Peripheral modules reset •...
Page 381: Software Power-Down
XDPP1100 technical reference manual Digital power controller Central processing unit subsystem An assertion of the SYSTRESETQ signal by Cortex®-M0 (debugger reset request) will cause the CPUS to be initialized, with the exception of the debugger section and WDT functionality. So the debugger will not be disconnected.
Page 382: Software Reset
XDPP1100 technical reference manual Digital power controller Central processing unit subsystem 15.3.3.3 Software reset The CPUS software reset is invoked by setting the SWRST bit in the RSTMODS register. To perform the reset, the EN_SWRES bit in SWRST_CTRL register must be set first (enabling CPUS software reset execution), then a...
Page 383 XDPP1100 technical reference manual Digital power controller Central processing unit subsystem Register name Field name Access Address Bits Description RSTSR SYSRST 4000_1000h [15] Cortex®-M0 SYSRESETQ flag. 0: The last reset was not generated by SYSRESETQ 1: The last reset was generated by...
Page 384 XDPP1100 technical reference manual Digital power controller Central processing unit subsystem Register name Field name Access Address Bits Description RSTMODS CNFGOTP1WRST 4000_1008h OTP wrapper reset bit. To exercise a module reset, FW has to set and to clear the proper bit accordingly.
Page 385 XDPP1100 technical reference manual Digital power controller Central processing unit subsystem Register name Field name Access Address Bits Description 1: Performs a reset of the D TIMER1 module RSTMODS DTIMER2RST 4000_1008h [12] module reset bit. To exercise TIMER2 a module reset, FW has to set and clear the proper bit accordingly.
Page 386 XDPP1100 technical reference manual Digital power controller Central processing unit subsystem Register name Field name Access Address Bits Description SWPWDN_CTRL register: only if the SW_PWDN_CTRL register has been configured does the SW_PWDN_REQ register have effect. 0: No request to enter power-down 1: Request CPUS to enter power- down.
Page 387 XDPP1100 technical reference manual Digital power controller Central processing unit subsystem Register name Field name Access Address Bits Description RSTMODS_SET CNFGOTP1WRST 4000_1020h OTP wrapper reset bit. To exercise a module reset, FW has to set and clear the proper bit accordingly.
Page 388 XDPP1100 technical reference manual Digital power controller Central processing unit subsystem Register name Field name Access Address Bits Description RSTMODS_SET DTIMER2RST 4000_1020h [12] module reset bit. To exercise TIMER2 a module reset, FW has to set and clear the proper bit accordingly.
Page 389 XDPP1100 technical reference manual Digital power controller Central processing unit subsystem Register name Field name Access Address Bits Description RSTMODS_CLR BIFREGRST 4000_1024h BIF REG reset bit. To exercise a module reset, FW has to set and clear the proper bit accordingly.
Page 390: Memory
0: Status of module reset unchanged 1: Release reset 15.4 Memory XDPP1100 contains three different memory types: ROM, RAM and OTP. They provide the infrastructure to: Store the application code • Provide an execution space • Support configurability and trimming parameters •...
Page 391: Random-Access Memory
XDPP1100 technical reference manual Digital power controller Central processing unit subsystem The ROM memory BIST is a HW engine used during chip production to verify the proper functionality of the module (self-check functional test). It reads the entire content of the ROM, generating a signature that is checked for correctness.
Page 392: Otp Memory Map
XDPP1100 technical reference manual Digital power controller Central processing unit subsystem interface macro interface wrapper Power-up FSM Figure 107 OTP module block diagram 15.4.3.1 OTP memory map OTP data can be read by FW starting from address 1002_0000h, but to simplify the address decoding logic, it can also be accessed at addresses 0002_0000h, 0003_0000h and 1003_0000h.
Page 393: Otp Configuration Interface
XDPP1100 technical reference manual Digital power controller Central processing unit subsystem Address Size Description 1003_FFFFh 1004_0000h 5001_FFFFh 5002_0000h OTP configuration registers 5002_0078h 15.4.3.2 OTP configuration interface It is possible for FW to configure OTP block behavior, or access the OTP macro indirectly or perform a specific test procedure (BIST) using the registers mapped on APB space starting from 5002_0000h.
Page 394 XDPP1100 technical reference manual Digital power controller Central processing unit subsystem Table 98 OTP instructions for indirect access Instruction Instruction Source/destination Description value register Program and verify 128 bits into OTP Data taken from 5h01 PROG and VERIFY (complete write sequence: write,...
Page 395: Otp Timing Configuration
XDPP1100 technical reference manual Digital power controller Central processing unit subsystem “PROG and VERIFY” operation executes a complete write sequence: Writing the data into the OTP with a WRITE pulse with a timing defined in PROG_PULSE_REG field of • OTP_PROG_C register Reading back the data with MRA-MRB-MR defined in READ1_MRAB and READ1_MR registers •...
Page 396: Otp Direct Access
XDPP1100 technical reference manual Digital power controller Central processing unit subsystem PROG_PULSE_REG, PROG_SOAK_PULSE_REG and BIST_READ_TIMEOUT control the READ pulse width during standard programming, soaking and the BIST procedure, respectively. VPP_WARMUP_REG and VPP_WARMDOWN_REG are used to define timings of the internal charge pump during a program phase: VPP_WARMUP_REG defines how long the charge pump needs to be activated for before the programming start;...
Page 397 XDPP1100 technical reference manual Digital power controller Central processing unit subsystem OTP timing requirements are specified in Table 100. Table 100 OTP timing requirements Timing Description Requirement [ns] READ address setup time READ address hold-time READ pulse width READ recovery time 14.8...
Page 398 XDPP1100 technical reference manual Digital power controller Central processing unit subsystem But the worst-case scenario is when the microcontroller asks for an address different from the prefetching one while the prefetch FSM is executing the caching access (Figure 110). In this case prefetch FSM must abort its transfer and allow AHB FSM to proceed with the new access.
Page 399: Otp Module Registers
XDPP1100 technical reference manual Digital power controller Central processing unit subsystem a system point of view, it needs to be mitigated, for example by copying the OTP program onto the RAM and executing it from the RAM. 15.4.3.6 OTP module registers...
Page 400 XDPP1100 technical reference manual Digital power controller Central processing unit subsystem Register name Field name Access Address Bits Description 3: AHB = 12.5 MHz CONF FL_EVEN 5002_0004h Even row “flip” control. 0: Do not flip even rows 1: Flip even rows...
Page 401 XDPP1100 technical reference manual Digital power controller Central processing unit subsystem Register name Field name Access Address Bits Description DATAW3 DATA 5002_001Ch [31:0] DATA[127:96] written to OTP by PROG and PROG+Verify instructions. READ_MRAB MRB_READ 5002_0020h [15:0] MRB register setting to be used for OTP READ.
Page 402 XDPP1100 technical reference manual Digital power controller Central processing unit subsystem Register name Field name Access Address Bits Description INT_RAW RAW_INSTR_DONE 5002_0050h Raw (unmasked) instruction status. 0: OTP instruction not complete 1: OTP instruction complete INT_RAW RAW_READ_FAULT 5002_0050h Raw (unmasked) READ fault status.
Page 403 XDPP1100 technical reference manual Digital power controller Central processing unit subsystem Register name Field name Access Address Bits Description INT_ACTIVE_C PWR_STAT 5002_005Ch [0] Writing 1 clears PWRUP_DONE on INT_ACTIVE register. INT_ACTIVE_C INSTR_DONE 5002_005Ch [1] Writing 1 clears INSTR_DONE on INT_ACTIVE register.
Page 404: Memory Management Unit
The MMU handles the memory space in sectors of 1 kB; for example, 80 kB ROM is represented by 80 LUT entries, one for each of the 1 kB sectors. In the XDPP1100 MMU there are a total of 176 LUTs: 80 ROM LUTs •...
Page 405: Mmu Registers
XDPP1100 technical reference manual Digital power controller Central processing unit subsystem Write protection: If the Cortex®-M0 address is within 0000_0000h to 0000_03FFFh, the operation is a write • and this bit is set, the MMU reports an illegal access fault.
Page 406 XDPP1100 technical reference manual Digital power controller Central processing unit subsystem Register name Field name Access Address Bits Description MMU_LUT_RO PROT 4000_4004h Defines the write protection of the M1_DATA target address block in the target memory space. Any write attempt to a protected block will result in an illegal access fault.
Page 407 XDPP1100 technical reference manual Digital power controller Central processing unit subsystem Register name Field name Access Address Bits Description MMU_LUT_RO BASE_ADR 4000_400Ch [9:8] Defines the target memory space M3_DATA into which the ROM section is remapped. 0: ROM 1: OTP...
Page 408 XDPP1100 technical reference manual Digital power controller Central processing unit subsystem Register name Field name Access Address Bits Description to a protected block will result in an illegal access fault. 0: Disable write protection 1: Enable write protection MMU_LUT_RO BLK_ADR...
Page 409 XDPP1100 technical reference manual Digital power controller Central processing unit subsystem Register name Field name Access Address Bits Description 1: OTP 2: RAM1 3: RAM2 MMU_LUT_RO PROT 4000_4024h Defines the write protection of the target address block in the target M9_DATA memory space.
Page 410 XDPP1100 technical reference manual Digital power controller Central processing unit subsystem Register name Field name Access Address Bits Description MMU_LUT_RO BLK_ADR 4000_402Ch [7:1] Defines the target address block M11_DATA into which the ROM section is remapped. MMU_LUT_RO BASE_ADR 4000_402Ch [9:8]...
Page 411 XDPP1100 technical reference manual Digital power controller Central processing unit subsystem Register name Field name Access Address Bits Description MMU_LUT_RO PROT 4000_4038h Defines the write protection of the M14_DATA target address block in the target memory space. Any write attempt to a protected block will result in an illegal access fault.
Page 412 XDPP1100 technical reference manual Digital power controller Central processing unit subsystem Register name Field name Access Address Bits Description MMU_LUT_RO BASE_ADR 4000_4040h [9:8] Defines the target memory space M16_DATA into which the ROM section is remapped. 0: ROM 1: OTP...
Page 413 XDPP1100 technical reference manual Digital power controller Central processing unit subsystem Register name Field name Access Address Bits Description to a protected block will result in an illegal access fault. 0: Disable write protection 1: Enable write protection MMU_LUT_RO BLK_ADR...
Page 414 XDPP1100 technical reference manual Digital power controller Central processing unit subsystem Register name Field name Access Address Bits Description 1: OTP 2: RAM1 3: RAM2 MMU_LUT_RO PROT 4000_4058h Defines the write protection of the target address block in the target M22_DATA memory space.
Page 415 XDPP1100 technical reference manual Digital power controller Central processing unit subsystem Register name Field name Access Address Bits Description MMU_LUT_RO BLK_ADR 4000_4060h [7:1] Defines the target address block M24_DATA into which the ROM section is remapped. MMU_LUT_RO BASE_ADR 4000_4060h [9:8]...
Page 416 XDPP1100 technical reference manual Digital power controller Central processing unit subsystem Register name Field name Access Address Bits Description MMU_LUT_RO PROT 4000_406Ch Defines the write protection of the M27_DATA target address block in the target memory space. Any write attempt to a protected block will result in an illegal access fault.
Page 417 XDPP1100 technical reference manual Digital power controller Central processing unit subsystem Register name Field name Access Address Bits Description MMU_LUT_RO BASE_ADR 4000_4074h [9:8] Defines the target memory space M29_DATA into which the ROM section is remapped. 0: ROM 1: OTP...
Page 418 XDPP1100 technical reference manual Digital power controller Central processing unit subsystem Register name Field name Access Address Bits Description to a protected block will result in an illegal access fault. 0: Disable write protection 1: Enable write protection MMU_LUT_RO BLK_ADR...
Page 419 XDPP1100 technical reference manual Digital power controller Central processing unit subsystem Register name Field name Access Address Bits Description 1: OTP 2: RAM1 3: RAM2 MMU_LUT_RO PROT 4000_408Ch Defines the write protection of the target address block in the target M35_DATA memory space.
Page 420 XDPP1100 technical reference manual Digital power controller Central processing unit subsystem Register name Field name Access Address Bits Description MMU_LUT_RO BLK_ADR 4000_4094h [7:1] Defines the target address block M37_DATA into which the ROM section is remapped. MMU_LUT_RO BASE_ADR 4000_4094h [9:8]...
Page 421 XDPP1100 technical reference manual Digital power controller Central processing unit subsystem Register name Field name Access Address Bits Description MMU_LUT_RO PROT 4000_40A0h Defines the write protection of the M40_DATA target address block in the target memory space. Any write attempt to a protected block will result in an illegal access fault.
Page 422 XDPP1100 technical reference manual Digital power controller Central processing unit subsystem Register name Field name Access Address Bits Description MMU_LUT_RO BASE_ADR 4000_40A8h [9:8] Defines the target memory space M42_DATA into which the ROM section is remapped. 0: ROM 1: OTP...
Page 423 XDPP1100 technical reference manual Digital power controller Central processing unit subsystem Register name Field name Access Address Bits Description to a protected block will result in an illegal access fault. 0: Disable write protection 1: Enable write protection MMU_LUT_RO BLK_ADR...
Page 424 XDPP1100 technical reference manual Digital power controller Central processing unit subsystem Register name Field name Access Address Bits Description 1: OTP 2: RAM1 3: RAM2 MMU_LUT_RO PROT 4000_40C0h Defines the write protection of the target address block in the target M48_DATA memory space.
Page 425 XDPP1100 technical reference manual Digital power controller Central processing unit subsystem Register name Field name Access Address Bits Description MMU_LUT_RO BLK_ADR 4000_40C8h [7:1] Defines the target address block M50_DATA into which the ROM section is remapped. MMU_LUT_RO BASE_ADR 4000_40C8h [9:8]...
Page 426 XDPP1100 technical reference manual Digital power controller Central processing unit subsystem Register name Field name Access Address Bits Description MMU_LUT_RO PROT 4000_40D4h Defines the write protection of the M53_DATA target address block in the target memory space. Any write attempt to a protected block will result in an illegal access fault.
Page 427 XDPP1100 technical reference manual Digital power controller Central processing unit subsystem Register name Field name Access Address Bits Description MMU_LUT_RO BASE_ADR 4000_40DCh [9:8] Defines the target memory space M55_DATA into which the ROM section is remapped. 0: ROM 1: OTP...
Page 428 XDPP1100 technical reference manual Digital power controller Central processing unit subsystem Register name Field name Access Address Bits Description to a protected block will result in an illegal access fault. 0: Disable write protection 1: Enable write protection MMU_LUT_RO BLK_ADR...
Page 429 XDPP1100 technical reference manual Digital power controller Central processing unit subsystem Register name Field name Access Address Bits Description 1: OTP 2: RAM1 3: RAM2 MMU_LUT_RO PROT 4000_40F4h Defines the write protection of the target address block in the target M61_DATA memory space.
Page 430 XDPP1100 technical reference manual Digital power controller Central processing unit subsystem Register name Field name Access Address Bits Description MMU_LUT_RO BLK_ADR 4000_40FCh [7:1] Defines the target address block M63_DATA into which the ROM section is remapped. MMU_LUT_RO BASE_ADR 4000_40FCh [9:8]...
Page 431 XDPP1100 technical reference manual Digital power controller Central processing unit subsystem Register name Field name Access Address Bits Description MMU_LUT_RO PROT 4000_4108h Defines the write protection of the M66_DATA target address block in the target memory space. Any write attempt to a protected block will result in an illegal access fault.
Page 432 XDPP1100 technical reference manual Digital power controller Central processing unit subsystem Register name Field name Access Address Bits Description MMU_LUT_RO BASE_ADR 4000_4110h [9:8] Defines the target memory space M68_DATA into which the ROM section is remapped. 0: ROM 1: OTP...
Page 433 XDPP1100 technical reference manual Digital power controller Central processing unit subsystem Register name Field name Access Address Bits Description to a protected block will result in an illegal access fault. 0: Disable write protection 1: Enable write protection MMU_LUT_RO BLK_ADR...
Page 434 XDPP1100 technical reference manual Digital power controller Central processing unit subsystem Register name Field name Access Address Bits Description 1: OTP 2: RAM1 3: RAM2 MMU_LUT_RO PROT 4000_4128h Defines the write protection of the target address block in the target M74_DATA memory space.
Page 435 XDPP1100 technical reference manual Digital power controller Central processing unit subsystem Register name Field name Access Address Bits Description MMU_LUT_RO BLK_ADR 4000_4130h [7:1] Defines the target address block M76_DATA into which the ROM section is remapped. MMU_LUT_RO BASE_ADR 4000_4130h [9:8]...
Page 436 XDPP1100 technical reference manual Digital power controller Central processing unit subsystem Register name Field name Access Address Bits Description MMU_LUT_RO PROT 4000_413Ch Defines the write protection of the M79_DATA target address block in the target memory space. Any write attempt to a protected block will result in an illegal access fault.
Page 437 XDPP1100 technical reference manual Digital power controller Central processing unit subsystem Register name Field name Access Address Bits Description MMU_LUT_OT BASE_ADR 4000_4204h [9:8] Defines the target memory space P1_DATA into which the OTP section is remapped. 0: ROM 1: OTP...
Page 438 XDPP1100 technical reference manual Digital power controller Central processing unit subsystem Register name Field name Access Address Bits Description to a protected block will result in an illegal access fault. 0: Disable write protection 1: Enable write protection MMU_LUT_OT BLK_ADR...
Page 439 XDPP1100 technical reference manual Digital power controller Central processing unit subsystem Register name Field name Access Address Bits Description 1: OTP 2: RAM1 3: RAM2 MMU_LUT_OT PROT 4000_421Ch Defines the write protection of the target address block in the target P7_DATA memory space.
Page 440 XDPP1100 technical reference manual Digital power controller Central processing unit subsystem Register name Field name Access Address Bits Description MMU_LUT_OT BLK_ADR 4000_4224h [7:1] Defines the target address block P9_DATA into which the OTP section is remapped. MMU_LUT_OT BASE_ADR 4000_4224h [9:8]...
Page 441 XDPP1100 technical reference manual Digital power controller Central processing unit subsystem Register name Field name Access Address Bits Description MMU_LUT_OT PROT 4000_4230h Defines the write protection of the P12_DATA target address block in the target memory space. Any write attempt to a protected block will result in an illegal access fault.
Page 442 XDPP1100 technical reference manual Digital power controller Central processing unit subsystem Register name Field name Access Address Bits Description MMU_LUT_OT BASE_ADR 4000_4238h [9:8] Defines the target memory space P14_DATA into which the OTP section is remapped. 0: ROM 1: OTP...
Page 443 XDPP1100 technical reference manual Digital power controller Central processing unit subsystem Register name Field name Access Address Bits Description to a protected block will result in an illegal access fault. 0: Disable write protection 1: Enable write protection MMU_LUT_OT BLK_ADR...
Page 444 XDPP1100 technical reference manual Digital power controller Central processing unit subsystem Register name Field name Access Address Bits Description 1: OTP 2: RAM1 3: RAM2 MMU_LUT_OT PROT 4000_4250h Defines the write protection of the target address block in the target P20_DATA memory space.
Page 445 XDPP1100 technical reference manual Digital power controller Central processing unit subsystem Register name Field name Access Address Bits Description MMU_LUT_OT BLK_ADR 4000_4258h [7:1] Defines the target address block P22_DATA into which the OTP section is remapped. MMU_LUT_OT BASE_ADR 4000_4258h [9:8]...
Page 446 XDPP1100 technical reference manual Digital power controller Central processing unit subsystem Register name Field name Access Address Bits Description MMU_LUT_OT PROT 4000_4264h Defines the write protection of the P25_DATA target address block in the target memory space. Any write attempt to a protected block will result in an illegal access fault.
Page 447 XDPP1100 technical reference manual Digital power controller Central processing unit subsystem Register name Field name Access Address Bits Description MMU_LUT_OT BASE_ADR 4000_426Ch [9:8] Defines the target memory space P27_DATA into which the OTP section is remapped. 0: ROM 1: OTP...
Page 448 XDPP1100 technical reference manual Digital power controller Central processing unit subsystem Register name Field name Access Address Bits Description to a protected block will result in an illegal access fault. 0: Disable write protection 1: Enable write protection MMU_LUT_OT BLK_ADR...
Page 449 XDPP1100 technical reference manual Digital power controller Central processing unit subsystem Register name Field name Access Address Bits Description 1: OTP 2: RAM1 3: RAM2 MMU_LUT_OT PROT 4000_4284h Defines the write protection of the target address block in the target P33_DATA memory space.
Page 450 XDPP1100 technical reference manual Digital power controller Central processing unit subsystem Register name Field name Access Address Bits Description MMU_LUT_OT BLK_ADR 4000_428Ch [7:1] Defines the target address block P35_DATA into which the OTP section is remapped. MMU_LUT_OT BASE_ADR 4000_428Ch [9:8]...
Page 451 XDPP1100 technical reference manual Digital power controller Central processing unit subsystem Register name Field name Access Address Bits Description MMU_LUT_OT PROT 4000_4298h Defines the write protection of the P38_DATA target address block in the target memory space. Any write attempt to a protected block will result in an illegal access fault.
Page 452 XDPP1100 technical reference manual Digital power controller Central processing unit subsystem Register name Field name Access Address Bits Description MMU_LUT_OT BASE_ADR 4000_42A0h [9:8] Defines the target memory space P40_DATA into which the OTP section is remapped. 0: ROM 1: OTP...
Page 453 XDPP1100 technical reference manual Digital power controller Central processing unit subsystem Register name Field name Access Address Bits Description to a protected block will result in an illegal access fault. 0: Disable write protection 1: Enable write protection MMU_LUT_OT BLK_ADR...
Page 454 XDPP1100 technical reference manual Digital power controller Central processing unit subsystem Register name Field name Access Address Bits Description 1: OTP 2: RAM1 3: RAM2 MMU_LUT_OT PROT 4000_42B8h Defines the write protection of the target address block in the target P46_DATA memory space.
Page 455 XDPP1100 technical reference manual Digital power controller Central processing unit subsystem Register name Field name Access Address Bits Description MMU_LUT_OT BLK_ADR 4000_42C0h [7:1] Defines the target address block P48_DATA into which the OTP section is remapped. MMU_LUT_OT BASE_ADR 4000_42C0h [9:8]...
Page 456 XDPP1100 technical reference manual Digital power controller Central processing unit subsystem Register name Field name Access Address Bits Description MMU_LUT_OT PROT 4000_42CCh Defines the write protection of the P51_DATA target address block in the target memory space. Any write attempt to a protected block will result in an illegal access fault.
Page 457 XDPP1100 technical reference manual Digital power controller Central processing unit subsystem Register name Field name Access Address Bits Description MMU_LUT_OT BASE_ADR 4000_42D4h [9:8] Defines the target memory space P53_DATA into which the OTP section is remapped. 0: ROM 1: OTP...
Page 458 XDPP1100 technical reference manual Digital power controller Central processing unit subsystem Register name Field name Access Address Bits Description to a protected block will result in an illegal access fault. 0: Disable write protection 1: Enable write protection MMU_LUT_OT BLK_ADR...
Page 459 XDPP1100 technical reference manual Digital power controller Central processing unit subsystem Register name Field name Access Address Bits Description 1: OTP 2: RAM1 3: RAM2 MMU_LUT_OT PROT 4000_42ECh Defines the write protection of the target address block in the target P59_DATA memory space.
Page 460 XDPP1100 technical reference manual Digital power controller Central processing unit subsystem Register name Field name Access Address Bits Description MMU_LUT_OT BLK_ADR 4000_42F4h [7:1] Defines the target address block P61_DATA into which the OTP section is remapped. MMU_LUT_OT BASE_ADR 4000_42F4h [9:8]...
Page 461 XDPP1100 technical reference manual Digital power controller Central processing unit subsystem Register name Field name Access Address Bits Description MMU_LUT_RA PROT 4000_4400h Defines the write protection of the M10_DATA target address block in the target memory space. Any write attempt to a protected block will result in an illegal access fault.
Page 462 XDPP1100 technical reference manual Digital power controller Central processing unit subsystem Register name Field name Access Address Bits Description MMU_LUT_RA BASE_ADR 4000_4408h [9:8] Defines the target memory space M12_DATA into which the RAM1 section is remapped. 0: ROM 1: OTP...
Page 463 XDPP1100 technical reference manual Digital power controller Central processing unit subsystem Register name Field name Access Address Bits Description to a protected block will result in an illegal access fault. 0: Disable write protection 1: Enable write protection MMU_LUT_RA BLK_ADR...
Page 464 XDPP1100 technical reference manual Digital power controller Central processing unit subsystem Register name Field name Access Address Bits Description 1: OTP 2: RAM1 3: RAM2 MMU_LUT_RA PROT 4000_4420h Defines the write protection of the target address block in the target M18_DATA memory space.
Page 465 XDPP1100 technical reference manual Digital power controller Central processing unit subsystem Register name Field name Access Address Bits Description MMU_LUT_RA BLK_ADR 4000_4428h [7:1] Defines the target address block M110_DATA into which the RAM1 section is remapped. MMU_LUT_RA BASE_ADR 4000_4428h [9:8]...
Page 466 XDPP1100 technical reference manual Digital power controller Central processing unit subsystem Register name Field name Access Address Bits Description MMU_LUT_RA PROT 4000_4434h Defines the write protection of the M113_DATA target address block in the target memory space. Any write attempt to a protected block will result in an illegal access fault.
Page 467 XDPP1100 technical reference manual Digital power controller Central processing unit subsystem Register name Field name Access Address Bits Description MMU_LUT_RA BASE_ADR 4000_443Ch [9:8] Defines the target memory space M115_DATA into which the RAM1 section is remapped. 0: ROM 1: OTP...
Page 468 XDPP1100 technical reference manual Digital power controller Central processing unit subsystem Register name Field name Access Address Bits Description to a protected block will result in an illegal access fault. 0: Disable write protection 1: Enable write protection MMU_LUT_RA BLK_ADR...
Page 469 XDPP1100 technical reference manual Digital power controller Central processing unit subsystem Register name Field name Access Address Bits Description 1: OTP 2: RAM1 3: RAM2 MMU_LUT_RA PROT 4000_4514h Defines the write protection of the target address block in the target M25_DATA memory space.
Page 470 XDPP1100 technical reference manual Digital power controller Central processing unit subsystem Register name Field name Access Address Bits Description MMU_LUT_RA BLK_ADR 4000_451Ch [7:1] Defines the target address block M27_DATA into which the RAM2 section is remapped. MMU_LUT_RA BASE_ADR 4000_451Ch [9:8]...
Page 471 XDPP1100 technical reference manual Digital power controller Central processing unit subsystem Register name Field name Access Address Bits Description MMU_LUT_RA PROT 4000_4528h Defines the write protection of the M210_DATA target address block in the target memory space. Any write attempt to a protected block will result in an illegal access fault.
Page 472 XDPP1100 technical reference manual Digital power controller Central processing unit subsystem Register name Field name Access Address Bits Description MMU_LUT_RA BASE_ADR 4000_4530h [9:8] Defines the target memory space M212_DATA into which the RAM2 section is remapped. 0: ROM 1: OTP...
Page 473 XDPP1100 technical reference manual Digital power controller Central processing unit subsystem Register name Field name Access Address Bits Description to a protected block will result in an illegal access fault. 0: Disable write protection 1: Enable write protection MMU_LUT_RA BLK_ADR...
Page 474 XDPP1100 technical reference manual Digital power controller Central processing unit subsystem Register name Field name Access Address Bits Description [24]: FAULTCOM [25]: TEST [25]: TESTSTAT [25]: Reserved MMU_PER_SP 4000_4604h [27:0] Enables the write protection of the ACE_SET peripherals mapped in the peripheral space.
Page 475 XDPP1100 technical reference manual Digital power controller Central processing unit subsystem Register name Field name Access Address Bits Description [0]: Not used [1]: WDT, D , GPIO TIMER [2]: UART, I C, PMBus [3]: Trim [4]: Analog [5]: VSP0 [6]: VSP1...
Page 476: Dma Controller
XDPP1100 technical reference manual Digital power controller Central processing unit subsystem Register name Field name Access Address Bits Description 1: Register reports the latest illegal address causing a fault MMU_ERR_RP 4000_4708h Write-only register that clears T_CLR MMU_ERR_RPT. 15.6 DMA controller The DMA controller is an Arm®...
Page 477: Dma Block Diagram
XDPP1100 technical reference manual Digital power controller Central processing unit subsystem 15.6.1 DMA block diagram The DMA block diagram is shown in Figure 112. APB block AHB block AHB-Lite Configuration memory DMA data master control mapped transfer interface registers Requests...
Page 478: Dma Channel Assignment
Table 104. The DMA macro supports single transfer requests (SREQs) and multiple transfer requests (REQs), but multiple transfer requests are currently not supported by the XDPP1100. DMA channel 0 has the highest priority, channel 15 the lowest. Table 104 DMA channel assignment table...
Page 479: Dma Registers
XDPP1100 technical reference manual Digital power controller Central processing unit subsystem 15.6.4 DMA registers The relevant DMA-related registers and their descriptions are provided in Table 105. Table 105 DMA-related register description Register name Field name Access Address Bits Description DMA_STATUS...
Page 480 XDPP1100 technical reference manual Digital power controller Central processing unit subsystem Register name Field name Access Address Bits Description [0] Controls HPROT[1] to indicate if a privileged access is occurring Notes: 1. When bit[n]=1, then the corresponding H is high PROT 2.
Page 481 XDPP1100 technical reference manual Digital power controller Central processing unit subsystem Register name Field name Access Address Bits Description For each bit [x], On READ: 0: DMA channel x responds to requests that it receives on dma_req or dma_sreq. The controller performs both 2 single bus transfers.
Page 482 XDPP1100 technical reference manual Digital power controller Central processing unit subsystem Register name Field name Access Address Bits Description DMA_CHNL_R CHNL_REQ_MASK_ 5000_0024h [15:0] The write-only register enables EQ_MASK_CLR DMA request on a per-channel basis. For each bit [x]: 0: No effect. Use the...
Page 483 XDPP1100 technical reference manual Digital power controller Central processing unit subsystem Register name Field name Access Address Bits Description 0: No effect. Use the CHNL_PRI_ALT_CLR Register to set bit [x] to 0. 1: Selects the alternate data structure for channel x...
Page 484 XDPP1100 technical reference manual Digital power controller Central processing unit subsystem Register name Field name Access Address Bits Description 0: dma_err is low 1: dma_err is high On WRITE: 0: No effect, status of dma_err is unchanged 1: Sets dma_err low...
Page 485: General-Purpose Input Output (Gpio) Module
The CPUS provides a number of GPIO pins, which are organized into blocks of eight GPIO pins each. The XDPP1100 controller contains two GPIO blocks (identical instance, replicated twice): GPIO0 and GPIO1. Each GPIO register set can be accessed with a different base address: GPIO_0: 6004_0000h •...
Page 486 XDPP1100 technical reference manual Digital power controller Central processing unit subsystem Register name Field name Access Address Bits Description In order to write to GPIODATA, the corresponding bits in the mask, resulting from the address bus PADDR[9:2], must be high.
Page 487 XDPP1100 technical reference manual Digital power controller Central processing unit subsystem Register name Field name Access Address Bits Description GPIOIBE INTEDGE 6004_0408h [7:0] The GPIOIBE register is the interrupt both edges register. When 6005_0408h the corresponding bit in GPIOIS is...
Page 488 XDPP1100 technical reference manual Digital power controller Central processing unit subsystem Register name Field name Access Address Bits Description detected (raw, prior to masking by GPIOIE.INTENA), indicating that all the requirements have been met, before they are finally allowed to trigger by GPIOIE.
Page 489 XDPP1100 technical reference manual Digital power controller Central processing unit subsystem Register name Field name Access Address Bits Description All bits are cleared by a reset, therefore no PrimeCell GPIO line is set to hardware control by default. For each bit [x]:...
Page 490: Wdt Module
XDPP1100 technical reference manual Digital power controller Central processing unit subsystem Register name Field name Access Address Bits Description GPIOPCellID2 GPIOPCellID2 6004_0FF8h [7:0] CellID[23:16]. Together with the other cell ID registers, CellID[31:0] is 6005_0FF8h used as a standard cross-peripheral ID system. In this case CellID[31:0] = 0xB105F00D.
Page 491: Watchdog Block Diagram
XDPP1100 technical reference manual Digital power controller Central processing unit subsystem 15.8.1 Watchdog block diagram The watchdog block structure is shown in Figure 113. Test Free running integration counter registers Identitification Address registers decoder Read data Lock register generation Figure 113 Watchdog block structure 15.8.2...
Page 492 XDPP1100 technical reference manual Digital power controller Central processing unit subsystem Register name Field name Access Address Bits Description 1: Enable reset output WDOGINTCLR INTCLR 6000_000Ch [31:0] Interrupt clear. This write-only register clears the watchdog interrupt, and reloads the counter from the value in WDOGLOAD.
Page 493 XDPP1100 technical reference manual Digital power controller Central processing unit subsystem Register name Field name Access Address Bits Description WDOGITOP ITINT 6000_0F04h Integration test WDOGINT value. Sets the value of the WDOGINT signal when in integration test mode. 0: Set WDOGINT low...
Page 494: Modules
XDPP1100 technical reference manual Digital power controller Central processing unit subsystem Register name Field name Access Address Bits Description ID system. In this case CellID[31:0] = 0xB105F00D. WDOGPCELLID WDOGPCELLID3 6000_0FFCh [7:0] CellID[31:24]. Together with the other cell ID registers, CellID[31:0] is used as a standard cross-peripheral ID system.
Page 495: Dual-Timer Block Diagram
XDPP1100 technical reference manual Digital power controller Central processing unit subsystem 15.9.1 Dual-timer block diagram The dual-timer block diagram is shown in Figure 114. Free running counter 1 Test integration Free running registers counter 2 Identitification Address registers decoder Read data...
Page 496 XDPP1100 technical reference manual Digital power controller Central processing unit subsystem Register name Field name Access Address Bits Description TIM_SEQ0_TIMERLOAD value replaces the current count value. Then each time the counter reaches zero, the current count value is reset to the value written to TIM_SEQ0_TIMERBGLOAD.
Page 497 XDPP1100 technical reference manual Digital power controller Central processing unit subsystem Register name Field name Access Address Bits Description TIM_SEQ0_TIM CLRINT 6001_000Ch [31:0] Interrupt clear. A write of any value ERINTCLR 6002_000Ch to this write-only register clears the counter interrupt.
Page 498 XDPP1100 technical reference manual Digital power controller Central processing unit subsystem Register name Field name Access Address Bits Description If values are written to both the TIM_SEQ1_TIMERLOAD and TIM_SEQ1_TIMERBGLOAD registers before an enabled rising edge on TIMCLK, the following occurs:...
Page 499: Pmbus Module
XDPP1100 technical reference manual Digital power controller Central processing unit subsystem Register name Field name Access Address Bits Description 6003_0028h 1: Periodic mode TIM_SEQ1_TIM 6001_0028h Timer enable. ERCONTROL 6002_0028h 0: Timer disabled 6003_0028h 1: Timer enabled TIM_SEQ1_TIM CLRINT 6001_002Ch [31:0] Interrupt clear.
Page 500 XDPP1100 technical reference manual Digital power controller Central processing unit subsystem clr_irq Irq_bus fsm_stat PMBUS_APB fsm_ctrl fsm_cnfg SCL_OUT SDA_OUT SCL_IN SCL_IN_F SDA_IN SDA_IN_F I2CF PMBUS_TOP Figure 115 PMBus block diagram The PMBus module manages the I C/SMBus/PMBus transactions by using a CPU. The advantage of such an approach is to have a fully programmable, configurable, and extensible SMBus/PMBus interface that can support any kind of commands.
Page 501: Pmbus Clock Scheme
XDPP1100 technical reference manual Digital power controller Central processing unit subsystem provided to avoid clock stretch stalling; watchdogs are enabled only when a transaction is in progress. The PMB_FSM embeds an HW CRC logic for RX PEC and TX PEC calculations. The FSM is organized into two main sections: the RX section and the TX section.
Page 502: 15.10.3.1 Configuration
XDPP1100 technical reference manual Digital power controller Central processing unit subsystem 15.10.3.1 Configuration To enable the CPU to manage the PMBus transactions, the following actions must be performed (Figure 117): Enable the PMBus APB clocks interface (bif_per_pmbus_clk). • Configure and enable the PMBus KERNEL clocks (pmbus_kernel_clk).
Page 503: 15.10.3.2 Write Transaction
XDPP1100 technical reference manual Digital power controller Central processing unit subsystem 15.10.3.2 Write transaction The following is an example of how to manage an incoming WRITE_BYTE transaction with and without PEC, where the host places data on the I C bus and the slave decodes the data. A flow chart to manage a generic...
Page 504 XDPP1100 technical reference manual Digital power controller Central processing unit subsystem PMBUS Write Transaction Wait irq (RX) Wait for irq (START) Read I_CODE Read I_CODE Clear Interrupt flag: isr = isr Clear Interrupt flag: isr = isr Load Adr_lut with a valid set of address...
Page 505: 15.10.3.3 Read Byte Transaction
XDPP1100 technical reference manual Digital power controller Central processing unit subsystem 15.10.3.3 Read byte transaction Here the process of managing an incoming READ_BYTE transaction (Figure 119) with and without PEC is described, where the slave has to place data on the I C bus following an initial sequence where the host sends the read request.
Page 506 XDPP1100 technical reference manual Digital power controller Central processing unit subsystem Prepare the TX_BUFFER with the expected data, set the number of bytes to be transmitted, then trigger the • FSM to move forward. Wait for irq_tx or irq_stop interrupt assertion.
Page 507 XDPP1100 technical reference manual Digital power controller Central processing unit subsystem PMBUS Read Transaction Wait for irq_rx or irq_stop or irq_tx_after_start Wait for irq_rx_after_start Clear Interrupt flag: Irq_tx_after_start ? isr = isr Write Transation or Read address Slave_address = status.slave_address...
Page 508: 15.10.3.4 Pmbus Ara Command
XDPP1100 technical reference manual Digital power controller Central processing unit subsystem 15.10.3.4 PMBus ARA command The ARA incoming transaction can be managed with the following sequence (Figure 120): Enable irq_rx_ara to detect ARA transaction. • Wait for irq_rx_ara interrupt assertion.
Page 509: Pmbus Registers
XDPP1100 technical reference manual Digital power controller Central processing unit subsystem 15.10.4 PMBus registers The relevant PMBus-related registers and their descriptions are provided in Table 109. Table 109 PMBus-related register descriptions Register name Field name Access Address Bits Description STATUS...
Page 510 XDPP1100 technical reference manual Digital power controller Central processing unit subsystem Register name Field name Access Address Bits Description 1: SCL_IN is at high level STATUS SDA_IN 7008_0000h [27] Status of the debounced SDA input signal. 0: SDA_IN is at low level...
Page 511 XDPP1100 technical reference manual Digital power controller Central processing unit subsystem Register name Field name Access Address Bits Description 0: CPU is in charge to generate ACK/NACK 1: HW takes care of generation of ACK/NACK. HW must be properly programmed.
Page 512 7008_0004h [18:10] Set the maximum number of clock cycles for which the SCL clock line can be kept low by XDPP1100. This number is internally multiplied by 2 * PCLK period (nominal 10 ns). XDPP1100 keeps the SCL low to...
Page 513 XDPP1100 technical reference manual Digital power controller Central processing unit subsystem Register name Field name Access Address Bits Description 5: TX IRQ 6: Stop IRQ 7: Watchdog timeout IRQ 8: Busy IRQ ARA_CW EN_ARA_CW 7008_000Ch Reserved ARA_CW DIRECTION 7008_000Ch Set the transaction direction.
Page 514 XDPP1100 technical reference manual Digital power controller Central processing unit subsystem Register name Field name Access Address Bits Description ACK/NACK event after a byte has been received. 0: Always NACK 1: Select ADR_LUT comparison table or ARA_CW. Basically (if ADDR_LUT(i) == RXDATA then ACK) or (if ARA_CW.ara_adr == RXDATA...
Page 515 XDPP1100 technical reference manual Digital power controller Central processing unit subsystem Register name Field name Access Address Bits Description cleared at detection of a start event. CTRL_TX TX_TRIGGER 7008_0020h Trigger HW FSM to move on after a TX* interrupt has been received.
Page 516 XDPP1100 technical reference manual Digital power controller Central processing unit subsystem Register name Field name Access Address Bits Description 2: Set all the DATA_LUTs in the index interval [MIN_RANGE : MAX_RANGE] to 1 3: Initialize all the DATA_LUTs to 1...
Page 517 XDPP1100 technical reference manual Digital power controller Central processing unit subsystem Register name Field name Access Address Bits Description ADDR_LUT0_A TYPE 7008_0040h [10:9] Transaction type. Defines the type DDR_CW of transaction associated with the defined slave address. 0: PMBus transaction...
Page 518 XDPP1100 technical reference manual Digital power controller Central processing unit subsystem Register name Field name Access Address Bits Description 3: Reserved ADDR_LUT3_A EN_ADDR 7008_004Ch [1:0] Enable/Disable this ADDR_LUT3 DDR_CW configuration word. 0: ADDR configuration word is disabled 1: ADDR responds to write...
Page 519 XDPP1100 technical reference manual Digital power controller Central processing unit subsystem Register name Field name Access Address Bits Description 1: ADDR responds to write transactions only 2: ADDR responds to read transactions only 3: ADDR responds to both read and...
Page 520 XDPP1100 technical reference manual Digital power controller Central processing unit subsystem Register name Field name Access Address Bits Description ADDR_LUT7_A ADDR 7008_005Ch [8:2] Sets the slave address at which the DDR_CW PMBus interface will respond. ADDR_LUT7_A TYPE 7008_005Ch [10:9] Transaction type. Defines the type...
Page 521 XDPP1100 technical reference manual Digital power controller Central processing unit subsystem Register name Field name Access Address Bits Description [31:24] = Byte 3 [23:16] = Byte 2 [15:8] = Byte 1 [7:0] = Byte 0 DATA_LUT4_D DATA 7008_0090h [31:0] The 32-bit data word 4 in 8x32-bit...
Page 522 XDPP1100 technical reference manual Digital power controller Central processing unit subsystem Register name Field name Access Address Bits Description DATA_LUT_BIT INDEX 7008_00C0h [7:0] The DATA_LUT_BIT_SET.INDEX sets _SET one bit of the DATA_LUT 8x32-bit scratch table to “1”, where INDEX = 0 corresponds to DATA_LUT0_DATA_W.DATA[0]...
Page 523 XDPP1100 technical reference manual Digital power controller Central processing unit subsystem Register name Field name Access Address Bits Description STATUS_INPU STATUS_INPUT 7008_0118h [7:0] Loop 0 STATUS_INPUT command T[0] data for HW-based SMBALERT generation. STATUS_INPU STATUS_INPUT 7008_011Ch [7:0] Loop 1 STATUS_INPUT command...
Page 524 XDPP1100 technical reference manual Digital power controller Central processing unit subsystem Register name Field name Access Address Bits Description STATUS_OFF[1 STATUS_OFF 7008_0154h Loop 1 STATUS_OFF command data for HW-based SMBALERT generation. STATUS_BUSY STATUS_BUSY 7008_0158h Loop 0 STATUS_BUSY command data for HW-based SMBALERT generation.
Page 525 XDPP1100 technical reference manual Digital power controller Central processing unit subsystem Register name Field name Access Address Bits Description 1: Bit [x] enabled for SMBALERT generation STATUS_MASK STATUS_CML_MAS 7008_0180h [7:0] Loop 0 STATUS_CML mask to _LP0[4] enable/disable bits for SMBALERT generation.
Page 526 XDPP1100 technical reference manual Digital power controller Central processing unit subsystem Register name Field name Access Address Bits Description STATUS_MASK STATUS_INPUT_MA 7008_0198h [7:0] Loop 1 STATUS_INPUT mask to _LP1[2] enable/disable bits for SMBALERT generation. For each bit [x]: 0: Bit [x] enabled for SMBALERT...
Page 527: I 2 C Module
XDPP1100 technical reference manual Digital power controller Central processing unit subsystem 15.11 C module The XDPP1100 includes an Inventra™ I C (MI2CV) module. The Inventra™ MI2CV provides an interface between the microprocessor and an I C bus that conforms to the Philips I C Bus Protocol (April 1995 Update).
Page 528 XDPP1100 technical reference manual Digital power controller Central processing unit subsystem Table 110 Status register codes Code Status Bus error START condition transmitted Repeated START condition transmitted Address + Write bit transmitted, ACK received Address + Write bit transmitted, ACK not received...
Page 529: 15.11.1.2 Master Transmit
XDPP1100 technical reference manual Digital power controller Central processing unit subsystem 15.11.1.2 Master transmit In master transmit mode, the I C will transmit a number of bytes to a slave receiver. The master transmit mode is entered by setting the STA in the CNTR register bit to “1”. The I C will then test the C bus and will transmit a START condition when the bus is free.
Page 530 XDPP1100 technical reference manual Digital power controller Central processing unit subsystem Code MI2CV State Microprocessor Response Mext MI2CV Action Or Write byte to DATA, clear Transmit data byte, receive IFLG, AAK=1 If 10-bit addressing is being used, then after the first part of a 10-bit address and the write bit have been successfully transmitted, the status code will be 18h or 20h.
Page 531: 15.11.1.3 Master Receive
XDPP1100 technical reference manual Digital power controller Central processing unit subsystem Table 113 Master transmit status after a repeated START Code MI2CV State Microprocessor response Next MI2CV action Data byte transmitted, ACK Write byte to DATA, clear IFLG Transmit data byte, receive...
Page 532 XDPP1100 technical reference manual Digital power controller Central processing unit subsystem Code MI2CV State Microprocessor response Next MI2CV action Or set STA and STP, clear IFLG Arbitration lost, SLA + Write Clear IFLG, AAK=0 Receive data byte, transmit bit received, ACK transmitted...
Page 533: 15.11.1.4 Slave Transmit
XDPP1100 technical reference manual Digital power controller Central processing unit subsystem When all bytes have been received, a not ACK should be transmitted, then the STP bit should be set by writing a “1” to this bit in the CNTR register. The I C will transmit a STOP condition, clear the STP bit and return to idle state (status code F8h).
Page 534: I 2 C Registers
XDPP1100 technical reference manual Digital power controller Central processing unit subsystem address was received or 78h if the general call address was received. The IFLG bit must be cleared to “0” to allow the data transfer to continue. If the AAK bit in the CNTR register is set to “1”, then after each byte is received, an acknowledge bit (low level on SDA) is transmitted and the IFLG bit is set: the STAT register will then contain status code 80h (or 90h if slave receive mode was entered with the general call address).
Page 535 XDPP1100 technical reference manual Digital power controller Central processing unit subsystem Register name Field name Access Address Bits Description For 10-bit addressing: When ADDR.SLA[4:0]=11110b, the I peripheral recognizes this as the first part of a 10-bit address and if the next two bits match ADDR.SLAX[1:0]...
Page 536 XDPP1100 technical reference manual Digital power controller Central processing unit subsystem Register name Field name Access Address Bits Description CNTR IFLG 700B_0008h Interrupt flag. IFLG is automatically set to “1” when any of 28 (out of the possible 29) I C peripheral states is entered (see STAT.CODE).
Page 537 XDPP1100 technical reference manual Digital power controller Central processing unit subsystem Register name Field name Access Address Bits Description CNTR ENAB 700B_0008h Bus enable. 0: I C inputs are ignored and the I peripheral will not respond to any address on the bus...
Page 538 XDPP1100 technical reference manual Digital power controller Central processing unit subsystem Register name Field name Access Address Bits Description 0Ch: Slave address + write bit received, ACK transmitted 0Dh: Arbitration lost in address as master, slave address + write bit...
Page 539: Crc Module
XDPP1100 technical reference manual Digital power controller Central processing unit subsystem Register name Field name Access Address Bits Description this state, the CNTR.STP bit must be set and the CNTR.IFLG bit cleared. The peripheral will then return to idle state (status code F8h) and no...
Page 540: Crc Registers
XDPP1100 technical reference manual Digital power controller Central processing unit subsystem Initial value definition • Polynomial definition • Final XOR configuration • Data input reflection • Data output reflection • CRC HW implementation is shown in Figure 122. INIT[Y:0] REFIN Data In [X:0] X <= 31...
Page 541: Uart
XDPP1100 technical reference manual Digital power controller Central processing unit subsystem Register name Field name Access Address Bits Description polynomial will be: P(x)=x^32+x^26+x^23+x^22+x^16+x ^12+x^11+x^10+x^8+x^7+x^5+x^4+ x^2+x^1+x^0, i.e., VAL=0x04C11DB7. A lower order can be programmed by just left-shifting the polynomial. For example, to configure a P(x) = x^8+x^5+x^4+x^0, write a value of 0x31000000.
Page 542: Uart Block Diagram
XDPP1100 technical reference manual Digital power controller Central processing unit subsystem Programmable HW flow control • Fully programmable serial interface characteristics: • o data can be 5, 6, 7 or 8 bits o even, odd, stick or no-parity bit generation and detection...
Page 543 XDPP1100 technical reference manual Digital power controller Central processing unit subsystem Table 118 UART-related register description Register name Field name Access Address Bits Description UARTDR DATA 700C_0000h [7:0] Data character. Receive (read) data character. Transmit (write) data character. UARTDR 700C_0000h Framing error.
Page 544 XDPP1100 technical reference manual Digital power controller Central processing unit subsystem Register name Field name Access Address Bits Description associated with the character at the top of the FIFO. UARTRSR_UAR 700C_0004h Parity error. When set to 1, it TECR indicates that the parity of the...
Page 545 XDPP1100 technical reference manual Digital power controller Central processing unit subsystem Register name Field name Access Address Bits Description UARTFR 700C_0018h Data carrier detect. This bit is the complement of the UART data carrier detect, nUARTDCD, modem status input. That is, the bit is 1 when nUARTDCD is low.
Page 546 XDPP1100 technical reference manual Digital power controller Central processing unit subsystem Register name Field name Access Address Bits Description indicate if there is data in the transmit shift register. UARTFR 700C_0018h Ring indicator. This bit is the complement of the UART ring indicator, nUARTRI, modem status input.
Page 547 XDPP1100 technical reference manual Digital power controller Central processing unit subsystem Register name Field name Access Address Bits Description Example: If the required baud rate is 230400 and UARTCLK = 4 MHz then: Baud rate divisor = (4 × 106)/(16 ×...
Page 548 XDPP1100 technical reference manual Digital power controller Central processing unit subsystem Register name Field name Access Address Bits Description 1: Even parity. The UART generates or checks for an even number of 1s in the data and parity bits. UARTLCR_H...
Page 549 XDPP1100 technical reference manual Digital power controller Central processing unit subsystem Register name Field name Access Address Bits Description 0: IrDA SIR ENDEC is disabled. nSIROUT remains low (no light pulse generated), and signal transitions on SIRIN have no effect.
Page 550 XDPP1100 technical reference manual Digital power controller Central processing unit subsystem Register name Field name Access Address Bits Description outputs are also fed through to the modem inputs. This bit is cleared to 0 on reset, to disable loopback. UARTCR 700C_0030h Transmit enable.
Page 551 XDPP1100 technical reference manual Digital power controller Central processing unit subsystem Register name Field name Access Address Bits Description programmed to 1, the output is 0. For DTE this can be used as ring indicator (RI). UARTCR RTSEn 700C_0030h [14] RTS HW flow control enable.
Page 552 XDPP1100 technical reference manual Digital power controller Central processing unit subsystem Register name Field name Access Address Bits Description UARTIMSC RIMIM 700C_0038h nUARTRI modem interrupt mask. A read returns the current mask for the UARTRIINTR interrupt. On a write of 1, the mask of the UARTRIINTR interrupt is set.
Page 553 XDPP1100 technical reference manual Digital power controller Central processing unit subsystem Register name Field name Access Address Bits Description UARTFEINTR interrupt is set. A write of 0 clears the mask. UARTIMSC PEIM 700C_0038h Parity error interrupt mask. A read returns the current mask for the UARTPEINTR interrupt.
Page 554 XDPP1100 technical reference manual Digital power controller Central processing unit subsystem Register name Field name Access Address Bits Description UARTRIS PERIS 700C_003Ch Parity error interrupt status. Returns the raw interrupt state of the UARTPEINTR interrupt. UARTRIS BERIS 700C_003Ch Break error interrupt status.
Page 555 XDPP1100 technical reference manual Digital power controller Central processing unit subsystem Register name Field name Access Address Bits Description interrupt state of the UARTBEINTR interrupt. UARTMIS OEMIS 700C_0040h [10] Overrun error masked interrupt status. Returns the masked interrupt state of the UARTOEINTR interrupt.
Page 556 XDPP1100 technical reference manual Digital power controller Central processing unit subsystem Register name Field name Access Address Bits Description UARTDMACR TXDMAE 700C_0048h Transmit DMA enable. If this bit is set to 1, DMA for the transmit FIFO is enabled. UARTDMACR...
Page 557: Debugger Port
15.14 Debugger port The debugger port on the XDPP1100 is implemented through the Cortex®-M0 serial wire debugger (SWD) interface, a two-wire serial protocol that is used to access the Cortex® debug access point (DAP). Cortex® DAP is a specific HW, integrated into the M0 microcontroller, that can take the control of the execution flow to allow an external debugger to access every register (on the Cortex®-M0 memory map), to...
Page 558: Serial Wire Debugger Interface
(it can normally be configured from 1 MHz to 20 MHz). XDPP1100 can achieve up to 20 MHz clock speed for SWCLK, but because SWCLK is asynchronous with respect to any internal device clock and proper synchronizations are in place in the Cortex® DAP, it is important that a minimum division ratio of 4 is maintained between the internal core clock and the debugger clock itself.
Page 559 XDPP1100 technical reference manual Digital power controller Central processing unit subsystem Figure 125 SWD enabling logic on XADDR1 In functional mode, TEST_GATE is latched to Logic 0 during power-up (XADDR1 is connected to an external resistor), so SWD IOs cannot be enabled by mistake.
Page 560 XDPP1100 technical reference manual Digital power controller Central processing unit subsystem Figure 126 XADDR1 timing diagram Additionally, the SWD interface can be enabled any time after the power-up, by writing in the CPUS_CFG register (DS_DBGPORT bit) using the I C interface (or FW).
Page 561: Revision History
XDPP1100 technical reference manual Digital power controller Revision history Revision history Document Date of release Description of changes version V 1.0 2021-08-25 Initial public release • User Manual 561 of 562 V 1.0 2021-08-25...
Page 562 Infineon Technologies AG With respect to any examples, hints or any typical 81726 Munich, Germany values stated herein and/or any information regarding the application of the product, Infineon WARNINGS Technologies hereby disclaims any and all Due to technical requirements products may contain warranties and liabilities of any kind, including dangerous substances.

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