Page 1: About This Document
Motion Control Engine (MCE) for control of a motor and/or power factor correction (PFC) with an additional ® ® microcontroller (MCU) based on an Arm Cortex -M0 core. Reference Manual Please read the Important Notice and Warnings at the end of this document V1.0 www.infineon.com 2020-05-28...
Page 2 IMC300A iMOTION Controller with additional microcontroller About this document By integrating both the required hardware and software to perform control of a permanent magnet synchronous motor (PMSM) the MCE provides the shortest time to market for any motor system at the lowest system and development cost.
Page 3: Table Of Contents
IMC300A iMOTION Controller with additional microcontroller Table of contents Table of contents About this document ..............1 Table of contents .
Page 4 IMC300A iMOTION Controller with additional microcontroller Table of contents 4.2.2 Stacks ................50 4.2.3 Core Registers .
Page 5 IMC300A iMOTION Controller with additional microcontroller Table of contents 4.7.2 Wakeup from Sleep Mode ............. 74 4.7.3 Power Management Programming Hints .
Page 6 IMC300A iMOTION Controller with additional microcontroller Table of contents 5.3.3.1 Domains of Convergence ............96 5.3.3.2 Overflow Considerations .
Page 7 IMC300A iMOTION Controller with additional microcontroller Table of contents 6.1.1 Features ................121 6.1.2 Block Diagram .
Page 8 IMC300A iMOTION Controller with additional microcontroller Table of contents 7.4.2.11 RTC CTR Mirror Register updated event ..........139 7.4.2.12 RTC ATIM0 Mirror Register updated event .
Page 9 IMC300A iMOTION Controller with additional microcontroller Table of contents 7.4.6.27 IIC: NACK received event ............151 7.4.6.28 IIC: Arbitration lost event .
Page 10 IMC300A iMOTION Controller with additional microcontroller Table of contents 7.4.10.5 Index event detection event ............162 7.4.10.6 Phase detection error event .
Page 11 IMC300A iMOTION Controller with additional microcontroller Table of contents 10.4.2 SRAM Access ............... . 192 10.4.3 ROM Access .
Page 12 IMC300A iMOTION Controller with additional microcontroller Table of contents 12.2.3 Address Types ...............213 12.2.4 Module Specific Definitions .
Page 13 IMC300A iMOTION Controller with additional microcontroller Table of contents 12.9.6 Timing ................228 Prefetch Unit (PFU) .
Page 14 IMC300A iMOTION Controller with additional microcontroller Table of contents 14.5.5 Automatic DCO1 Calibration based on External Reference ....... 249 14.6 Service Request Generation .
Page 15 IMC300A iMOTION Controller with additional microcontroller Table of contents 14.9.6.14 Register PASSWD ..............290 14.9.6.15 Register MIRRSTS .
Page 16 IMC300A iMOTION Controller with additional microcontroller Table of contents 16.5 Debug Behavior ............... 310 16.6 Power, Reset and Clock .
Page 17 IMC300A iMOTION Controller with additional microcontroller Table of contents 18.2.1.2 Input Stages ..............330 18.2.1.3 Output Signals .
Page 18 IMC300A iMOTION Controller with additional microcontroller Table of contents 18.2.8.6 Receive Buffer Events and Interrupts ..........361 18.2.8.7 Receive FIFO Buffer in Filling Level Mode Usage Example .
Page 19 IMC300A iMOTION Controller with additional microcontroller Table of contents 18.4.2.1 Automatic Shadow Mechanism ........... . . 390 18.4.2.2 Mode Control Behavior .
Page 20 IMC300A iMOTION Controller with additional microcontroller Table of contents 18.5.3.3 Byte Stretching ..............422 18.5.3.4 Master Arbitration .
Page 21 IMC300A iMOTION Controller with additional microcontroller Table of contents 18.10.4.2.4 Register PSR [IIC Mode] ............463 18.10.4.2.5 Register PSCR .
Page 22 IMC300A iMOTION Controller with additional microcontroller Table of contents 18.11 Interconnects ............... . . 504 18.11.1 USIC0 Module Interconnects .
Page 23 IMC300A iMOTION Controller with additional microcontroller Table of contents 19.3.7.2 Transmit Acceptance Filtering ............544 19.3.8 Message Postprocessing .
Page 24 IMC300A iMOTION Controller with additional microcontroller Table of contents 19.5.3.6 Register CAN_MOAMRn ............596 19.5.3.7 Register CAN_MOARn .
Page 25 IMC300A iMOTION Controller with additional microcontroller Table of contents 20.2.5.4 External Count Signal ............. . 639 20.2.5.5 External Load .
Page 26 IMC300A iMOTION Controller with additional microcontroller Table of contents 20.7.2.5 Register CC4yTCSET ............. . . 698 20.7.2.6 Register CC4yTCCLR .
Page 27 IMC300A iMOTION Controller with additional microcontroller Table of contents 21.2.6 Synchronous Start ..............752 21.2.7 Using the POSIF .
Page 28 IMC300A iMOTION Controller with additional microcontroller Table of contents 21.8.2 POSIF1 Pins ............... . . 789 Analog-to-Digital Converter (ADC) .
Page 29 IMC300A iMOTION Controller with additional microcontroller Table of contents 22.6.9 Service Request Registers ............817 22.6.9.1 Register GLOBEFLAG .
Page 30 IMC300A iMOTION Controller with additional microcontroller Table of contents 24.6.2 Channel Registers ..............841 24.6.2.1 Register DATASy .
Page 31 IMC300A iMOTION Controller with additional microcontroller Table of contents 26.8.2.6 Register P4_PHCR1 ..............867 26.8.3 Pin Function Decision Control Register .
Page 32 IMC300A iMOTION Controller with additional microcontroller Table of contents 26.10.1 Input and Output Voltage .............892 26.10.2 Input Low and Input High Voltage .
Page 33 IMC300A iMOTION Controller with additional microcontroller Table of contents 28.4.1 Erase Flash Page ..............920 28.4.2 Erase, Program &...
Page 34 IMC300A iMOTION Controller with additional microcontroller Table of contents 29.8.2 Register SCS_DHCSR ..............938 29.8.2.1 Register SCS_DHCSR [Read Mode] .
Page 35: Introduction
Nonetheless the architecture of the IMC300A controller pursues successful ™ hardware and software concepts, which have been established in Infineon’s iMOTION Platform portfolio. Overview The IMC300A series devices combine the extended functionality and performance of the ARM Cortex-M0 core including the following: •...
Page 36 IMC300A iMOTION Controller with additional microcontroller 1 Introduction Analog Frontend Peripherals • Analog to Digital Converter (ADC) with up to 7 analog input channels and a fast 12-bit converter with adjustable gain • 4 channels of out of range comparators (ORC) •...
Page 37: Block Diagram
IMC300A iMOTION Controller with additional microcontroller 1 Introduction 1.1.1 Block Diagram The figures below show the toplevel block diagram and the functional blocks as well as their basic connectivity within the IMC300A system. iMOTION™ Application iMOTION™ MCE Controller Motor Controller JCOM PFC Controller ®...
Page 38 IMC300A iMOTION Controller with additional microcontroller 1 Introduction Analog System Debug System CORTEX-M0 2 x DCO ANACTRL AHB to APB Bridge PRNG AHB-Lite Bus MATH FLASH USIC0 CCU40 channel0 128kB CoPro USIC0 SRAM POSIF0 channel1 16kB CCU41 Controller ACMP & POSIF1 USIC1 channel0...
Page 39: Device Overview
IMC300A iMOTION Controller with additional microcontroller 1 Introduction 1.1.2 Device Overview The following table lists the available features per device type for the IMC300A series. Table 1 Features of IMC300A Device Types Features CPU frequency 48 MHz Operating temperature Ambient temperature -40 to 105 °C Operating voltage 3.0 V to 5.5 V ™...
Page 40: Cpu Subsystem
IMC300A iMOTION Controller with additional microcontroller 1 Introduction CPU Subsystem The CPU subsystem contains the ARM Cortex-M0 processor with its 32bit bus system, the Math Coprocessor, the processing of service requests either as event requests or interrupt requests and a powerful event request unit. 1.2.1 Central Processing Unit (CPU) The ARM Cortex-M0 processor is built on a highly area and power optimized 32-bit processor core, with a 3-stage...
Page 41: Communication Peripherals
IMC300A iMOTION Controller with additional microcontroller 1 Introduction Communication Peripherals Communication features are key requirements in today’s industrial systems. The IMC300A offers a set of peripherals supporting advanced communication protocols. Dedicated hardware peripherals are available for CAN, UART, SPI and I2C. 1.4.1 Universal Serial Interface Channel (USIC) The USIC is a flexible interface module covering several serial communication protocols such as UART, SPI and...
Page 42: Temperature Sensor (Dts)
IMC300A iMOTION Controller with additional microcontroller 1 Introduction 1.5.4 Temperature Sensor (DTS) The Temperature Sensor generates a measurement result that indicates directly the die temperature. It is also capable of generating interrupt requests when the temperature measurement crosses the selectable upper/ lower threshold value.
Page 43: Conventions
Attention: Please consult all parts of the documentation set to attain consolidated knowledge about your device. Application related guidance is provided by Users Guides and Application Notes. Please refer to http://www.infineon.com/iMOTION to get access to the latest versions of those documents. Copyright Notice ©...
Page 44: Bit Function Terminology
IMC300A iMOTION Controller with additional microcontroller 2 Conventions • Units are abbreviated as follows: MHz = Megahertz µs = Microseconds kBaud, kbit = 1000 characters/bits per second MBaud, Mbit = 1,000,000 characters/bits per second Kbyte, KB = 1024 bytes of memory Mbyte, MB= 1048576 bytes of memory In general, the k prefix scales a unit by 1000 whereas the K prefix scales a unit by 1024.
Page 45: Reserved Bits
IMC300A iMOTION Controller with additional microcontroller 2 Conventions Table 3 Register Access Modes Symbol Description PV (SV), U Access permitted in Privileged (Supervisor) Mode. ® Note: Cortex M0 processor does not support different privilege levels. Only Privileged (Supervisor) Mode is supported in iMOTION Controller. Symbol “U” and Symbol “PV”...
Page 46 Random Access Memory Real Time Clock System Control Unit Special Function Register Sample and Hold Sequencer Serial Peripheral Interface Single Pin Debug Interface (defined by Infineon) SRAM Static RAM Service Request Synchronous Serial Channel Start-up Software Serial Wire Debug Interface (defined by ARM)
Page 47 IMC300A iMOTION Controller with additional microcontroller 2 Conventions Watchdog Timer Reference Manual V1.0 2020-05-28...
Page 48: Motion Control Engine Interface
If the MCE experiences a number of frame errors it will automatically fall back to the default baud rate. In order to ease the implementation of the JCOM communication protocol Infineon provides the respective software driver for this JCOM interface.
Page 49: Features
IMC300A iMOTION Controller with additional microcontroller 4 Central Processing Unit (CPU) The Cortex-M0 processor closely integrates a configurable NVIC, to deliver industry leading interrupt performance. The NVIC provides 4 interrupt priority levels. The tight integration of the processor core and NVIC provides fast execution of interrupt service routines (ISRs), dramatically reducing the interrupt latency.
Page 50: Programmers Model
IMC300A iMOTION Controller with additional microcontroller 4 Central Processing Unit (CPU) Cortex-M0 components Cortex-M0 processor Debug Nested Breakpoint Vectored Cortex-M0 Interrupts Interrupt processor watchpoint Controller core unit (NVIC) Debug Debugger Bus Matrix Access Port Interface (DAP) AHB-Lite interface Single Pin or Serial Wire debug-port Figure 4 Cortex-M0 Block Diagram...
Page 51: Core Registers
IMC300A iMOTION Controller with additional microcontroller 4 Central Processing Unit (CPU) Table 5 Summary of processor mode, execution, and stack use options Processor mode Used to execute Stack used Thread Applications Main stack or process stack Handler Exception handlers Main stack 4.2.3 Core Registers Low registers...
Page 52: General-Purpose Registers
IMC300A iMOTION Controller with additional microcontroller 4 Central Processing Unit (CPU) Table 6 Core register set summary (continued) Name Type Reset value Description Unknown Stack Pointer on page 52 Unknown Link Register on page 53 See description Program Counter on page 53 Unknown Program Status Register on page 54...
Page 53: Link Register
IMC300A iMOTION Controller with additional microcontroller 4 Central Processing Unit (CPU) Stack Pointer Reset Value: 00000000 Value Value Field Bits Type Description Value 31:0 Content of Register 4.2.3.3 Link Register The Link Register (LR) is register R14. It stores the return information for subroutines, function calls, and exceptions.
Page 54: Program Status Register
IMC300A iMOTION Controller with additional microcontroller 4 Central Processing Unit (CPU) Value Value Field Bits Type Description Value 31:0 Content of Register 4.2.3.5 Program Status Register The Program Status Register (PSR) combines: • Application Program Status Register (APSR) • Interrupt Program Status Register (IPSR) •...
Page 55: Interrupt Program Status Register
IMC300A iMOTION Controller with additional microcontroller 4 Central Processing Unit (CPU) Field Bits Type Description Negative flag Zero flag Carry or borrow flag Overflow flag 27:0 Reserved 4.2.3.5.2 Interrupt Program Status Register The IPSR contains the exception type number of the current Interrupt Service Routine (ISR). See the register summary in Table 6 for its attributes.
Page 56: Execution Program Status Register
IMC300A iMOTION Controller with additional microcontroller 4 Central Processing Unit (CPU) (continued) Field Bits Type Description ISR_NUMBER Number of the current exception Thread mode Reserved Reserved HardFault Reserved Reserved Reserved Reserved Reserved Reserved Reserved SVCall Reserved Reserved PendSV SysTick IRQ0 Reserved See Exception types in Chapter 4.5.2...
Page 57: Interruptible-Restartable Instructions
IMC300A iMOTION Controller with additional microcontroller 4 Central Processing Unit (CPU) (continued) Field Bits Type Description Thumb state bit See Thumb state. 23:0 Reserved 4.2.3.5.4 Interruptible-restartable instructions When an interrupt occurs during the execution of an LDM, STM, PUSH, POP instruction, the processor abandons execution of the instruction.
Page 58: Control Register
IMC300A iMOTION Controller with additional microcontroller 4 Central Processing Unit (CPU) Field Bits Type Description 31:1 Reserved PRIMASK Priority Mask No effect. Prevents the activation of all exceptions with configurable priority. 4.2.3.7 CONTROL Register The CONTROL register controls the stack used when the processor is in Thread mode. See the register summary Table 6 for its attributes.
Page 59: Exceptions And Interrupts
IMC300A iMOTION Controller with additional microcontroller 4 Central Processing Unit (CPU) 4.2.4 Exceptions and Interrupts The Cortex-M0 processor supports interrupts and system exceptions. The processor and the NVIC prioritize and handle all exceptions. An interrupt or exception changes the normal flow of software control. The processor uses handler mode to handle all exceptions except for reset.
Page 60: Cmsis Functions
IMC300A iMOTION Controller with additional microcontroller 4 Central Processing Unit (CPU) 4.2.7 CMSIS Functions ISO/IEC C code cannot directly access some Cortex-M0 instructions. This section describes intrinsic functions that can generate these instructions, provided by the CMSIS and that might be provided by a C compiler. If a C compiler does not support an appropriate intrinsic function, an inline assembler may be used to access the relevant instruction.
Page 61: Memory Regions, Types And Attributes
IMC300A iMOTION Controller with additional microcontroller 4 Central Processing Unit (CPU) 0xFFFFFFFF Device 511MB 0xE0100000 0xE00FFFFF Private peripheral 1.0MB 0xE0000000 0xDFFFFFFF External device 1.0GB 0xA0000000 0x9FFFFFFF External RAM 1.0GB 0x60000000 0x5FFFFFFF Peripheral 0.5GB 0x40000000 0x3FFFFFFF SRAM 0.5GB 0x20000000 0x1FFFFFFF Code 0.5GB 0x00000000 Figure 6...
Page 62: Memory System Ordering Of Memory Accesses
IMC300A iMOTION Controller with additional microcontroller 4 Central Processing Unit (CPU) The different ordering requirements for Device and Strongly-ordered memory mean that the memory system can buffer a write to Device memory, but must not buffer a write to Strongly-ordered memory. The additional memory attributes include: Execute Never (XN) Means the processor prevents instruction accesses.
Page 63: Software Ordering Of Memory Accesses
IMC300A iMOTION Controller with additional microcontroller 4 Central Processing Unit (CPU) Table 10 Memory access behavior (continued) Address range Memory region Memory type Description 0xA0000000- External device Device External device memory. 0xDFFFFFFF 0xE0000000- Private Peripheral Strongly- ordered XN This region includes the NVIC, system timer, 0xE00FFFFF and system control block.
Page 64: Instruction Set
IMC300A iMOTION Controller with additional microcontroller 4 Central Processing Unit (CPU) Memory Register 24 23 1615 Address lsbyte msbyte Figure 8 Little-endian format (Example) Instruction Set Table 11 lists the supported Cortex-M0 instructions. For more information on the instructions and operands, please refer to [1].
Page 65 IMC300A iMOTION Controller with additional microcontroller 4 Central Processing Unit (CPU) Table 11 Cortex-M0 instructions (continued) Mnemonic Operands Brief description Flags Instruction Synchronization Barrier Rn{!}, reglist Load Multiple registers, increment after Rt, label Load Register from PC-relative address - Rt, [Rn, <Rm|#imm>] Load Register with word LDRB Rt, [Rn, <Rm|#imm>]...
Page 66: Intrinsic Functions
IMC300A iMOTION Controller with additional microcontroller 4 Central Processing Unit (CPU) Table 11 Cortex-M0 instructions (continued) Mnemonic Operands Brief description Flags SXTB Rd, Rm Sign extend byte SXTH Rd, Rm Sign extend halfword Rn, Rm Logical AND based test UXTB Rd, Rm Zero extend a byte UXTH...
Page 67: Exception Types
IMC300A iMOTION Controller with additional microcontroller 4 Central Processing Unit (CPU) 4.5.2 Exception Types The exception types are described in Table Table 12 Exception types Exception Types Descriptions Reset Reset is invoked on power up or a warm reset. The exception model treats reset as a special form of exception.
Page 68: Exception Handlers
IMC300A iMOTION Controller with additional microcontroller 4 Central Processing Unit (CPU) For an asynchronous exception, other than reset, the processor can execute additional instructions between when the exception is triggered and when the processor enters the exception handler. Software can disable the exceptions in Table 13 which have configurable priority, see Interrupt Clear-enable Register in Interrupt System chapter.
Page 69: Vector Table Remap
IMC300A iMOTION Controller with additional microcontroller 4 Central Processing Unit (CPU) Exception number IRQ number Offset Vector IRQ31 0x00BC IRQ2 0x0048 IRQ1 0x0044 IRQ0 0x0040 Systick 0x003C PendSV 0x0038 Reserved SVCall 0x002C Reserved 0x0010 Hard fault 0x000C Reserved Reset 0x0004 Initial SP value 0x0000 Figure 9...
Page 70: Exception Priorities
IMC300A iMOTION Controller with additional microcontroller 4 Central Processing Unit (CPU) Table 14 Remapped Vector Table (continued) Exception IRQ Number Vector Default Vector Address Remapped Vector Number Address Reset 0000’0004 1000’1004 HardFault 0000’000C 2000’000C SVCall 0000’002C 2000’002C PendSV 0000’0038 2000’0038 SysTick 0000’003C 2000’003C...
Page 71 IMC300A iMOTION Controller with additional microcontroller 4 Central Processing Unit (CPU) Source of figure [8]. Return This occurs when the exception handler is completed, and: • there is no pending exception with sufficient priority to be serviced • the completed exception handler was not handling a late-arriving exception. The processor pops the stack and restores the processor state to the state it had before the interrupt occurred.
Page 72: Exception Entry
IMC300A iMOTION Controller with additional microcontroller 4 Central Processing Unit (CPU) Source of figure [8]. 4.5.6.1 Exception entry Exception entry occurs when there is a pending exception with sufficient priority and either: • the processor is in Thread mode • the new exception is of higher priority than the exception being handled, in which case the new exception preempts the original exception.
Page 73: Exception Return
IMC300A iMOTION Controller with additional microcontroller 4 Central Processing Unit (CPU) If another higher priority exception occurs during exception entry, the processor starts executing the exception handler for this exception and does not change the pending status of the earlier exception. This is the late arrival case.
Page 74: Lockup
IMC300A iMOTION Controller with additional microcontroller 4 Central Processing Unit (CPU) 4.6.1 Lockup The processor enters a lockup state if a fault occurs when executing the HardFault handlers, or if the system generates a bus error when unstacking the PSR on an exception return using the MSP. When the processor is in lockup state it does not execute any instructions.
Page 75: Power Management Programming Hints
IMC300A iMOTION Controller with additional microcontroller 4 Central Processing Unit (CPU) • debug event, if debug is enabled • exception at a priority that would preempt any currently active exceptions, if PRIMASK was set to 0 Note: If PRIMASK is set to 1, an interrupt or exception that has a higher priority than the current exception priority will cause the processor to wake up.
Page 76: System Control Block
IMC300A iMOTION Controller with additional microcontroller 4 Central Processing Unit (CPU) 4.8.2 System control block The System Control Block (SCB) provides system implementation information, and system control. This includes configuration, control, and reporting of the system exceptions. 4.8.2.1 System control block usage hints and tips Ensure software uses aligned 32-bit word size transactions to access all the system control block registers.
Page 77: Scs Registers
IMC300A iMOTION Controller with additional microcontroller 4 Central Processing Unit (CPU) Table 17 Register Overview (continued) Short Name Description Offset Access Mode Description see Address Read Write SHPR3 System Handler Priority PV, 32 PV, 32 Page Register 3 SHCSR System Handler Control and PV, 32 PV, 32 Page...
Page 78: Register Icsr
IMC300A iMOTION Controller with additional microcontroller 4 Central Processing Unit (CPU) 4.9.1.2 Register ICSR The ICSR: • provides: set-pending and clear-pending bits for the PendSV and SysTick exceptions • indicates: the exception number of the exception being processed whether there are preempted active exceptions the exception number of the highest priority pending exception whether any interrupts are pending.
Page 79: Register Aircr
IMC300A iMOTION Controller with additional microcontroller 4 Central Processing Unit (CPU) (continued) Field Bits Type Description 21:18 Reserved Read as 0; should be written with 0. ISRPENDING Interrupt Pending Flag This bit sets the interrupt pending flag, excluding faults. Interrupt not pending Interrupt pending.
Page 80: Register Scr
IMC300A iMOTION Controller with additional microcontroller 4 Central Processing Unit (CPU) AIRCR Address: E000ED0C Application Interrupt and Reset Control Register Reset Value: FA050000 VECTKEY ENDI SYSR ANNE ESET Field Bits Type Description Reserved Read as 0; should be written with 0. Reserved Must be written with 0.
Page 81: Register Ccr
IMC300A iMOTION Controller with additional microcontroller 4 Central Processing Unit (CPU) SLEE SLEE EXIT Field Bits Type Description Reserved Read as 0; should be written with 0. SLEEPONEXIT Sleep-on-exit This bit indicates sleep-on-exit when returning from Handler mode to Thread mode. Do not sleep when returning to Thread mode.
Page 82: System Handler Priority Registers
IMC300A iMOTION Controller with additional microcontroller 4 Central Processing Unit (CPU) STKA LIGN LIGN _TRP Field Bits Type Description Reserved Read as 0; should be written with 0. UNALIGN_TRP Unaligned Access Traps This bit always reads as 1, indicates that all unaligned accesses generate a HardFault.
Page 83: Register Shpr2
IMC300A iMOTION Controller with additional microcontroller 4 Central Processing Unit (CPU) Each PRI_N field is 8 bits wide, but the IMC300A implements only bits [7:6] of each field, and bits [5:0] read as zero and ignore writes. 4.9.1.6.1 Register SHPR2 The SHPR2 register sets the priority level for the SVCall handler.
Page 84: Register Shcsr
IMC300A iMOTION Controller with additional microcontroller 4 Central Processing Unit (CPU) 4.9.1.7 Register SHCSR The SHCSR register controls and provides the status of system handlers. SHCSR Address: E000ED24 System Handler Control and State Register Reset Value: 00000000 SVCA LLPE NDED Field Bits Type...
Page 85: Register Syst_Rvr
IMC300A iMOTION Controller with additional microcontroller 4 Central Processing Unit (CPU) NTFL CLKS TICK Field Bits Type Description ENABLE Counter Enable This bit enables the counter. Counter disabled. Counter enabled. TICKINT SysTick Exception Request This bit enables the SysTick exception request. Counting down to zero does not assert the SysTick exception request.
Page 86: Register Syst_Cvr
IMC300A iMOTION Controller with additional microcontroller 4 Central Processing Unit (CPU) SYST_RVR Address: E000E014 SysTick Reload Value Register Reset Value: XXXXXXXX RELOAD RELOAD Field Bits Type Description RELOAD 23:0 Reload Value This field sets the value to load into the SYST_CVR register when the counter is enabled and when it reaches 0.
Page 87: Register Syst_Calib
IMC300A iMOTION Controller with additional microcontroller 4 Central Processing Unit (CPU) Field Bits Type Description CURRENT 23:0 SysTick Counter Current Value When read, it returns the current value of the SysTick counter. A write of any value clears the field to 0, and also clears the SYST_CSR.COUNTFLAG bit to 0.
Page 88: Math Coprocessor (Math)
IMC300A iMOTION Controller with additional microcontroller 5 MATH Coprocessor (MATH) MATH Coprocessor (MATH) Overview The Math Coprocessor (MATH) module comprises of two independent sub-blocks to support the CPU in math- intensive computations: a Divider Unit (DIV) for signed and unsigned 32-bit division operations and a CORDIC (COrdinate Rotation DIgital Computer) Coprocessor for computation of trigonometric, linear or hyperbolic functions.
Page 89: Division Operation
IMC300A iMOTION Controller with additional microcontroller 5 MATH Coprocessor (MATH) 32-bit divide by 16-bit 16-bit divide by 16-bit • Operands pre-processing with configurable number of: Left shifts for dividend Right shifts for divisor • Result post-processing with configurable number of shifts and shift direction Note: The execution time of 35 kernel clock cycles for a division operation does not include the time to access the operand and result registers, which takes an additional part of the time for a division...
Page 90: Start Mode Selection
IMC300A iMOTION Controller with additional microcontroller 5 MATH Coprocessor (MATH) Kernel Clock DIVCON.ST DIVST.BSY EVFR.DIVEOC QUOT Figure 12 Timing Diagram for a Division Operation Note: Reading the QUOT and RMD registers while BSY=1 will cause the DIV to insert wait states onto the bus until the active calculation is completed (BSY=0).
Page 91 IMC300A iMOTION Controller with additional microcontroller 5 MATH Coprocessor (MATH) In both cases, the error will be indicated by the EVFR.DIVERR flag. An interrupt request to NVIC can be generated if it is enabled through EVIER.DIVERRIEN. The division operation will still proceed as normal and complete in 35 kernel clock cycles. The error flag becomes set at the same clock cycle as DIVEOC.
Page 92: Operand/Result Pre-/Post-Processing
IMC300A iMOTION Controller with additional microcontroller 5 MATH Coprocessor (MATH) Table 19 Overflow Error Conditions DIVCON.DIVMODE Dividend (Hex) Dividend (Dec) Divisor (Hex) Divisor (Dec) 8000’0000 FFFF’FFFF 8000’0000 FFFF 8000 -32768 FFFF The DIV does not detect for overflow errors that is due to result post-processing. In this case, user must always ensure that the result after post-processing is still within the boundaries of DIV.
Page 93: Features
IMC300A iMOTION Controller with additional microcontroller 5 MATH Coprocessor (MATH) 5.3.1.1 Features The key features of the MATH are listed below: • Modes of operation Supports all CORDIC operating modes for solving circular (trigonometric), linear (multiply-add, divide- add) and hyperbolic functions Integrated look-up tables (LUTs) for all operating modes •...
Page 94: Normalized Result Data
IMC300A iMOTION Controller with additional microcontroller 5 MATH Coprocessor (MATH) As the first step on starting a CORDIC calculation (provided the corresponding KEEP bits are not set), the initial data is loaded from the data registers CORDx to the internal kernel data registers. During the calculation, the kernel data registers always hold the latest intermediate data.
Page 95: Math Operating Modes
IMC300A iMOTION Controller with additional microcontroller 5 MATH Coprocessor (MATH) The CORDIC calculated data includes an inherent gain factor K resulting from the rotation or vectoring. The value K is different for each CORDIC function, as shown in Table Table 21 CORDIC Function Inherent Gain Factor for Result Data Function Approximated Gain K...
Page 96: Domains Of Convergence
IMC300A iMOTION Controller with additional microcontroller 5 MATH Coprocessor (MATH) Table 22 MATH Operating Modes and Corresponding Result Data (continued) Function Rotation Mode Vectoring Mode For solving cosh(Z) and sinh(Z) and e , set For solving sqrt(x ), set X = x / k, Y = y / k. X = 1 / k, Y = 0.
Page 97: Overflow Considerations
IMC300A iMOTION Controller with additional microcontroller 5 MATH Coprocessor (MATH) Z data must converge towards 0. In circular function, this means |Z| ≤ integer value representing 1.74 radians. For linear function, |Z| ≤ 2. In hyperbolic function, |Z| ≤ integer value representing 1.11 radians. Vectoring Mode Y data must converge towards 0.
Page 98: Accuracy Of Math
IMC300A iMOTION Controller with additional microcontroller 5 MATH Coprocessor (MATH) The Z data is always handled as integer, based on the normalization factor for circular or hyperbolic function. In case of linear function, accessible Z data is a real number with fixed input and result data form of S4.19 (signed 4Q19) which is a fraction with 19 decimal places.
Page 99 IMC300A iMOTION Controller with additional microcontroller 5 MATH Coprocessor (MATH) integer. In case the data is a rational number, the magnitude of deviation has to be interpreted. For example, Z for linear vectoring mode of the data form S4.19 - ND = 1 (01 ) means the difference from expected real data has magnitude of no more than |2 |;...
Page 100: Performance Of Math
IMC300A iMOTION Controller with additional microcontroller 5 MATH Coprocessor (MATH) Table 24 Normalized Deviation of a Calculation (continued) Mode X Normalized Deviation Y or Z Normalized Deviation Linear Rotation Input conditions: Useful Domain (|Z| ≤ 2) 0 : 100% 0 : 48.2181% ND for X ≤...
Page 101: Global Functions
IMC300A iMOTION Controller with additional microcontroller 5 MATH Coprocessor (MATH) Global Functions Since the DIV and CORDIC have their own set of control and data registers, they can work independently from one another. However, they share a common bus interface and some global functions. 5.4.1 Result Chaining The Math Coprocessor supports result chaining between the DIV and CORDIC.
Page 102: Handling Busy Flags When Result Chaining Is Enabled
IMC300A iMOTION Controller with additional microcontroller 5 MATH Coprocessor (MATH) To avoid any potential deadlock situation, application must take care to avoid the following two scenarios when using the result chaining feature: DVS is chained to QUOT or RMD while DIVCON.STMODE = 0 DVS is chained to CORRx and CORDX is chained to QUOT or RMD, and at the same time both DIVCON.STMODE and CON.ST_MODE = 0 5.4.1.2...
Page 103: Debug Behaviour
IMC300A iMOTION Controller with additional microcontroller 5 MATH Coprocessor (MATH) EVFCR EVFR EVIER Clear CDEOCC CDEOC CDEOCIEN EVFSR CDEOCS CORDIC End of Calculation event EVFCR EVFR EVIER Clear CDERRC CDERR CDERRIEN EVFSR CDERRS CORDIC Error event EVFCR EVFR EVIER Logic Clear InterruptService DIVEOCC...
Page 104: Power, Reset And Clock
IMC300A iMOTION Controller with additional microcontroller 5 MATH Coprocessor (MATH) • Hard Suspend Mode The kernel clock is immediately switched off, thereby stopping all calculations • Soft Suspend Mode Any active calculation is allowed to continue and only after it is completed, will the kernel clock be switched off After the kernel clock is switched off, all registers become read-only.
Page 105: Global Registers Description
IMC300A iMOTION Controller with additional microcontroller 5 MATH Coprocessor (MATH) Table 26 Register Overview (continued) Short Name Description Offset Access Mode Description see Addr. Read Write GLBCON Global Control Register 0004 U, PV U, PV Page Module Identification Register 0008 U, PV Page EVIER...
Page 106 IMC300A iMOTION Controller with additional microcontroller 5 MATH Coprocessor (MATH) SUSCFG CORDZRC CORDYRC CORDXRC DVSRC DVDRC Field Bits Type Description DVDRC Dividend Register Result Chaining The DVD register in DIV will be updated with the selected result register value when the result chaining trigger event occurs. No result chaining is selected QUOT register is the selected source RMD register is the selected source...
Page 107: Register Math_Id
IMC300A iMOTION Controller with additional microcontroller 5 MATH Coprocessor (MATH) (continued) Field Bits Type Description CORDYRC 10:9 CORDY Register Result Chaining The CORDY register in CORDIC will be updated with the selected result register value when the result chaining trigger event occurs.
Page 108: Register Evier
IMC300A iMOTION Controller with additional microcontroller 5 MATH Coprocessor (MATH) Field Bits Type Description MOD_REV Module Revision Number MOD_REV defines the revision number. The value of a module revision starts with 01 (first revision). MOD_TYPE 15:8 Module Type This bit field is C0 .
Page 109: Register Evfr
IMC300A iMOTION Controller with additional microcontroller 5 MATH Coprocessor (MATH) 5.8.1.4 Register EVFR This register contains the status flags for each event. If set, it indicates that the event has been detected. EVFR Address: 0010 Event Flag Register Reset Value: 0000 0000 DIVE DIVE...
Page 110: Register Evfcr
IMC300A iMOTION Controller with additional microcontroller 5 MATH Coprocessor (MATH) DIVE DIVE Field Bits Type Description DIVEOCS Divider End of Calculation Event Flag Set No effect. Sets the Divider end of calculation event flag in EVFR register. Interrupt will be generated if enabled in EVIER register.
Page 111: Divider Registers Description
IMC300A iMOTION Controller with additional microcontroller 5 MATH Coprocessor (MATH) DIVE DIVE Field Bits Type Description DIVEOCC Divider End of Calculation Event Flag Clear No effect. Clears the Divider end of calculation event flag in EVFR register. DIVERRC Divider Error Event Flag Clear No effect.
Page 112: Register Dvs
IMC300A iMOTION Controller with additional microcontroller 5 MATH Coprocessor (MATH) Field Bits Type Description 31:0 Dividend Value 5.8.2.2 Register DVS The DVS register is used to store the divisor operand of the division. It can be written by software and if result chaining is enabled, also by hardware.
Page 113: Register Rmd
IMC300A iMOTION Controller with additional microcontroller 5 MATH Coprocessor (MATH) 5.8.2.4 Register RMD The RMD register is used to store the remainder result of the division. It will be automatically updated by hardware upon each completion of a division operation. Note: Wait states will be inserted on the bus if the RMD register is read while BSY = 1.
Page 114 IMC300A iMOTION Controller with additional microcontroller 5 MATH Coprocessor (MATH) Write access to DIVCON register is ignored while BSY=1. No bus error will be generated in this case. Note: If result-chaining is enabled, refer also to Chapter 5.4.1.2 for description on handling of the busy flag. DIVCON Address: 0034...
Page 115: Cordic Registers Description
IMC300A iMOTION Controller with additional microcontroller 5 MATH Coprocessor (MATH) (continued) Field Bits Type Description QSCNT 12:8 Quotient Shift Count If QSCNT is not equal to 0, it indicates the number of bits the quotient will be shifted by, after the division. If QSCNT=0, no shift operation will take place.
Page 116: Register Con
IMC300A iMOTION Controller with additional microcontroller 5 MATH Coprocessor (MATH) (continued) Field Bits Type Description KEEPX Last X Result as Initial Data for New Calculation If set, a new calculation will use the value of the result from the previous calculation as the initial data. In other words, the respective kernel data register will not be overwritten by the contents of the shadow data register at the beginning of the new calculation.
Page 117 IMC300A iMOTION Controller with additional microcontroller 5 MATH Coprocessor (MATH) Field Bits Type Description Start Calculation If ST_MODE = 1, set ST to start a CORDIC calculation. Is effective only while BSY is not set. This bit may be set with the other bits of this register in one write access.
Page 118: Cordx
IMC300A iMOTION Controller with additional microcontroller 5 MATH Coprocessor (MATH) 5.8.3.3 CORDx The Data registers are used to initialize the X, Y and Z parameters. 5.8.3.3.1 Register CORDX CORDX Address: 0048 CORDIC X Data Register Reset Value: 0000 0000 DATA DATA Field Bits...
Page 119: Corrx
IMC300A iMOTION Controller with additional microcontroller 5 MATH Coprocessor (MATH) DATA DATA Field Bits Type Description Reserved DATA 31:8 Initial Z Parameter Data 5.8.3.4 CORRx The result data from CORDIC calculation will be written to the respective result registers. Any read access on these registers while STATC.BSY is set (a calculation is still running) will cause the kernel to issue a bus wait until BSY is reset.
Page 120: Register Corrz
IMC300A iMOTION Controller with additional microcontroller 5 MATH Coprocessor (MATH) RESULT RESULT Field Bits Type Description Reserved RESULT 31:8 Y Calculation Result 5.8.3.4.3 Register CORRZ CORRZ Address: 005C CORDIC Z Result Register Reset Value: 0000 0000 RESULT RESULT Field Bits Type Description Reserved...
Page 121: Service Request Processing
IMC300A iMOTION Controller with additional microcontroller 6 Service Request Processing Service Request Processing A hardware pulse is called Service Request (SR) in an IMC300A system. Service Requests are the fastest way to send trigger “messages” between connected on‑chip resources. An SR can generate any of the following requests •...
Page 122: Service Request Distribution
IMC300A iMOTION Controller with additional microcontroller 6 Service Request Processing On-Chip Unit PORTS Outputs Interconnections On-Chip Unit NVIC PORTS Inputs CPU Core Figure 16 Block Diagram on Service Request Processing Service Request Distribution Figure 17 shows an example of how a service request can be distributed concurrently. To support the concurrent distribution to multiple receivers, the receiving modules are capable to enable/disable incoming requests.
Page 123 IMC300A iMOTION Controller with additional microcontroller 6 Service Request Processing Embedded real time services Connectivity between On-Chip Units and PORTS is real time application and also chip package dependant. Related connectivity and availability of pins can be looked up in the •...
Page 124: Interrupt Subsystem (Nvic)
IMC300A iMOTION Controller with additional microcontroller 7 Interrupt Subsystem (NVIC) Interrupt Subsystem (NVIC) The interrupt Subsystem in IMC300A consists of the Nested Vectored Interrupt Controller (NVIC) and the respective modules’ interrupt generation blocks. Note: The CPU exception model is described in the CPU chapter. Nested Vectored Interrupt Controller (NVIC) The NVIC is an integral part of the Cortex M0 processor unit.
Page 125 IMC300A iMOTION Controller with additional microcontroller 7 Interrupt Subsystem (NVIC) Table 30 Interrupt Node assignment Node ID Service Request Service Request Service Request Source A Source B Source C SCU.SR0 CAN0.SR0 CCU40.SR0 SCU.SR1 CAN0.SR1 CCU80.SR0 SCU.SR2 CAN0.SR2 CCU80.SR1 ERU0.SR0 ERU1.SR0 CAN0.SR0 ERU0.SR1 ERU1.SR1...
Page 126: Interrupt Signal Generation
IMC300A iMOTION Controller with additional microcontroller 7 Interrupt Subsystem (NVIC) 7.1.3 Interrupt Signal Generation In IMC300A, all peripherals support only the generation of pulse interrupts. Pulse interrupts are also described as edge-triggered interrupts. A pulse interrupt is an interrupt signal sampled synchronously on the rising edge of the processor clock (MCLK). To ensure the NVIC detects the interrupt, the peripheral asserts the interrupt signal for at least one MCLK clock cycle, during which the NVIC detects the pulse and latches the interrupt.
Page 127: Accessing Cpu Registers Using Cmsis
IMC300A iMOTION Controller with additional microcontroller 7 Interrupt Subsystem (NVIC) Table 31 CMSIS functions for NVIC control (continued) CMSIS interrupt control function Description void NVIC_ClearPendingIRQ (IRQn_t IRQn) Clear IRQn pending status void NVIC_SetPriority (IRQn_t IRQn, uint32_t priority) Set priority for IRQn uint32_t NVIC_GetPriority (IRQn_t IRQn) Read priority of IRQn void NVIC_SystemReset (void)
Page 128: Interrupt Latency
IMC300A iMOTION Controller with additional microcontroller 7 Interrupt Subsystem (NVIC) 24 23 16 15 PRI_3 PRI_2 PRI_1 PRI_0 IPR7 (node 31) (node 30) (node 29) (node 28) PRI_3 PRI_2 PRI_1 PRI_0 IPRn (node 4n+3) (node 4n+2) (node 4n+1) (node 4n) PRI_3 PRI_2 PRI_1...
Page 129: General Module Interrupt Structure
IMC300A iMOTION Controller with additional microcontroller 7 Interrupt Subsystem (NVIC) MCLK 16-cycle latency Interrupt instruction at due to core becomes remapped (Instructions in the remapped vector table ) Active in NVIC interrupt vector Overall interrupt latency = 21 MCLK cycles Figure 20 Typical IMC300A Interrupt Latency This assumes the following conditions:...
Page 130: Registers
IMC300A iMOTION Controller with additional microcontroller 7 Interrupt Subsystem (NVIC) Enable Service Request Output event X to NVIC Status Clear Clear bit Interrupt flag Routing Management N trigger block sources Outputs Set bit Figure 21 Typical Module Interrupt Structure To enable a module HW event for interrupt generation, SW has to: •...
Page 131: Nvic Registers
IMC300A iMOTION Controller with additional microcontroller 7 Interrupt Subsystem (NVIC) Table 34 Register Overview (continued) Short Name Description Offset Access Mode Description See Address Read Write NVIC_ICER Interrupt Clear-enable U, PV U, PV Page Registers NVIC_ISPR Interrupt Set-pending U, PV U, PV Page Registers...
Page 132: Register Nvic_Ispr
IMC300A iMOTION Controller with additional microcontroller 7 Interrupt Subsystem (NVIC) CLRENA CLRENA Field Bits Type Description CLRENA 31:0 Interrupt Node Clear-enable Read: Interrupt node disabled. Write: No effect Read: Interrupt node enabled. Write: Disable interrupt node. 7.3.1.3 Register NVIC_ISPR The ISPR register forces interrupt nodes into the pending state, and shows which interrupt nodes are pending. NVIC_ISPR Address: E000E200...
Page 133: Register Nvic_Iprx (X=0-7)
IMC300A iMOTION Controller with additional microcontroller 7 Interrupt Subsystem (NVIC) CLRPEND CLRPEND Field Bits Type Description CLRPEND 31:0 Interrupt Node Clear-pending Read: Interrupt node is not pending. Write: No effect. Read: Interrupt node is pending. Write: Remove interrupt state from pending. Note: Writing 1 to an ICPR bit does not affect the active state of the corresponding interrupt node.
Page 134: Register Scu_Intcr0
IMC300A iMOTION Controller with additional microcontroller 7 Interrupt Subsystem (NVIC) These registers are also described in the SCU chapter. 7.3.2.1 Register SCU_INTCR0 This register selects the interrupt source for interrupt node 0 to 15. SCU_INTCR0 Address: 4001006C Interrupt Control Register 0 Reset Value: 00000000 INTSEL15...
Page 135: Interrupt Request Source Overview
IMC300A iMOTION Controller with additional microcontroller 7 Interrupt Subsystem (NVIC) Interrupt Request Source Overview An overview of all IMC300A interrupt sources and related register bits are shown in the next few pages. 7.4.1 Interrupt source: SCU.SR0 7.4.1.1 Flash double bit ECC event Table 35 SCU.SR0 - Flash double bit ECC event Flash ECC double bit error has two status flags, each having its own clear bit.
Page 136: Usic Ram Parity Error Event
IMC300A iMOTION Controller with additional microcontroller 7 Interrupt Subsystem (NVIC) Table 37 SCU.SR0 - SRAM parity error event (continued) Type Register Bits Set flag SCU_SRSET PESRAMI Clear flag SCU_SRCLR PESRAMI Node pointer 7.4.1.4 USIC RAM parity error event Table 38 SCU.SR0 - USIC RAM parity error event Type Register...
Page 137: Vddp Pre-Warning Event
IMC300A iMOTION Controller with additional microcontroller 7 Interrupt Subsystem (NVIC) Table 40 SCU.SR1 - Standby clock failure event (continued) Type Register Bits Node pointer 7.4.2.2 VDDP pre-warning event Table 41 SCU.SR1 - VDDP pre-warning event Type Register Bits Interrupt enable SCU_SRMSK VDDPI Status flag...
Page 138: Dts Done Event
IMC300A iMOTION Controller with additional microcontroller 7 Interrupt Subsystem (NVIC) 7.4.2.5 DTS done event Table 44 SCU.SR1 - DTS done event Type Register Bits Interrupt enable SCU_SRMSK TSE_DONE Status flag SCU_SRRAW TSE_DONE Set flag SCU_SRSET TSE_DONE Clear flag SCU_SRCLR TSE_DONE Node pointer 7.4.2.6 DTS compare high event...
Page 139: Rtc Periodic Event
IMC300A iMOTION Controller with additional microcontroller 7 Interrupt Subsystem (NVIC) Table 47 SCU.SR1 - WDT pre-warning event (continued) Type Register Bits Clear flag SCU_SRCLR PRWARN Node pointer 7.4.2.9 RTC periodic event Table 48 SCU.SR1 - RTC periodic event Type Register Bits Interrupt enable Status flag...
Page 140: Rtc Atim0 Mirror Register Updated Event
IMC300A iMOTION Controller with additional microcontroller 7 Interrupt Subsystem (NVIC) 7.4.2.12 RTC ATIM0 Mirror Register updated event Table 51 SCU.SR1 - RTC ATIM0 Mirror Register updated event Type Register Bits Interrupt enable SCU_SRMSK RTC_ATIM0 Status flag SCU_SRRAW RTC_ATIM0 Set flag SCU_SRSET RTC_ATIM0 Clear flag...
Page 141: Interrupt Source: Scu.sr2
IMC300A iMOTION Controller with additional microcontroller 7 Interrupt Subsystem (NVIC) Table 54 SCU.SR1 - RTC TIM1 Mirror Register updated event (continued) Type Register Bits Clear flag SCU_SRCLR RTC_TIM1 Node pointer 7.4.3 Interrupt source: SCU.SR2 7.4.3.1 Out of range comparator x event (x=0,4,6,7) Table 55 SCU.SR2 - Out of range comparator x event (x=0,4,6,7) Type...
Page 142: Interrupt Source: Erux.sr[3:0] (X=0-1)
IMC300A iMOTION Controller with additional microcontroller 7 Interrupt Subsystem (NVIC) 7.4.4 Interrupt source: ERUx.SR[3:0] (x=0-1) 7.4.4.1 ERUx_IOUTy (y=0-3) See chapter on ERUx for details. 7.4.5 Interrupt source: MATH.SR0 7.4.5.1 CORDIC end of calculation event Table 57 MATH.SR0 - CORDIC end of calculation event Type Register Bits...
Page 143: Div Error Event
IMC300A iMOTION Controller with additional microcontroller 7 Interrupt Subsystem (NVIC) 7.4.5.4 DIV error event Table 60 MATH.SR0 - DIV error event Type Register Bits Interrupt enable MATH_EVIER DIVERRIEN Status flag MATH_EVFR DIVERR Set flag MATH_EVFSR DIVERRS Clear flag MATH_EVFCR DIVERRC Node pointer 7.4.6 Interrupt source: USICx_SR[5:0] (x=0-1)
Page 144: Usic: Transmit Shift Event
IMC300A iMOTION Controller with additional microcontroller 7 Interrupt Subsystem (NVIC) Table 63 USICx_SR[5:0] (x=0-1) - USIC: Alternate receive event (continued) Type Register Bits Status flag USICx_CHy_PSR Set flag Clear flag USICx_CHy_PSCR CAIF Node pointer USICx_CHy_INPR AINP 7.4.6.4 USIC: Transmit shift event Table 64 USICx_SR[5:0] (x=0-1) - USIC: Transmit shift event Type...
Page 145: Usic: Brg Event
IMC300A iMOTION Controller with additional microcontroller 7 Interrupt Subsystem (NVIC) 7.4.6.7 USIC: BRG event Table 67 USICx_SR[5:0] (x=0-1) - USIC: BRG event Type Register Bits Interrupt enable USICx_CHy_CCR BRGIEN Status flag USICx_CHy_PSR BRGIF Set flag Clear flag USICx_CHy_PSCR CBRGIF Node pointer USICx_CHy_INPR PINP 7.4.6.8...
Page 146: Usic: Standard Receive Buffer Event
IMC300A iMOTION Controller with additional microcontroller 7 Interrupt Subsystem (NVIC) 7.4.6.10 USIC: Standard receive buffer event Table 71 USICx_SR[5:0] (x=0-1) - USIC: Standard receive buffer event Type Register Bits Interrupt enable USICx_CHy_RBCTR SRBIEN Status flag USICx_CHy_TRBSR SRBI Set flag Clear flag USICx_CHy_TRBSCR CSRBI Node pointer...
Page 147: Asc: Synchronisation Break Detected Event
IMC300A iMOTION Controller with additional microcontroller 7 Interrupt Subsystem (NVIC) 7.4.6.13 ASC: Synchronisation break detected event Table 75 USICx_SR[5:0] (x=0-1) - ASC: Synchronisation break detected event Type Register Bits Interrupt enable USICx_CHy_PCR SBDIEN Status flag USICx_CHy_PSR Set flag Clear flag USICx_CHy_PSCR CSBD Node pointer...
Page 148: Asc: Format Error In Stop Bit 1 Event
IMC300A iMOTION Controller with additional microcontroller 7 Interrupt Subsystem (NVIC) Table 78 USICx_SR[5:0] (x=0-1) - ASC: Format error in stop bit 0 event (continued) Type Register Bits Clear flag USICx_CHy_PSCR CFER0 Node pointer USICx_CHy_INPR PINP 7.4.6.17 ASC: Format error in stop bit 1 event Table 79 USICx_SR[5:0] (x=0-1) - ASC: Format error in stop bit 1 event Type...
Page 149: Ssc: Msls Event Detected Event
IMC300A iMOTION Controller with additional microcontroller 7 Interrupt Subsystem (NVIC) 7.4.6.20 SSC: MSLS event detected event Table 82 USICx_SR[5:0] (x=0-1) - SSC: MSLS event detected event Type Register Bits Interrupt enable USICx_CHy_PCR MSLSIEN Status flag USICx_CHy_PSR MSLSEV Set flag Clear flag USICx_CHy_PSCR CMSLSEV Node pointer...
Page 150: Iic: Start Condition Received Event
IMC300A iMOTION Controller with additional microcontroller 7 Interrupt Subsystem (NVIC) Table 85 USICx_SR[5:0] (x=0-1) - IIC: Wrong TDF code detected event (continued) Type Register Bits Clear flag USICx_CHy_PSCR CWTDF Node pointer USICx_CHy_INPR PINP 7.4.6.24 IIC: Start condition received event Table 86 USICx_SR[5:0] (x=0-1) - IIC: Start condition received event Type Register...
Page 151: Iic: Nack Received Event
IMC300A iMOTION Controller with additional microcontroller 7 Interrupt Subsystem (NVIC) 7.4.6.27 IIC: NACK received event Table 89 USICx_SR[5:0] (x=0-1) - IIC: NACK received event Type Register Bits Interrupt enable USICx_CHy_PCR NACKIEN Status flag USICx_CHy_PSR NACK Set flag Clear flag USICx_CHy_PSCR CNACK Node pointer USICx_CHy_INPR...
Page 152: Iic: Ack Received Event
IMC300A iMOTION Controller with additional microcontroller 7 Interrupt Subsystem (NVIC) Table 92 USICx_SR[5:0] (x=0-1) - IIC: Error detected event (continued) Type Register Bits Clear flag USICx_CHy_PSCR CERR Node pointer USICx_CHy_INPR PINP 7.4.6.31 IIC: ACK received event Table 93 USICx_SR[5:0] (x=0-1) - IIC: ACK received event Type Register Bits...
Page 153: Iis: Wa Rising Edge Event
IMC300A iMOTION Controller with additional microcontroller 7 Interrupt Subsystem (NVIC) 7.4.6.34 IIS: WA rising edge event Table 96 USICx_SR[5:0] (x=0-1) - IIS: WA rising edge event Type Register Bits Interrupt enable USICx_CHy_PCR WAREIEN Status flag USICx_CHy_PSR WARE Set flag Clear flag USICx_CHy_PSCR CWARE Node pointer...
Page 154: Channel Event Y (Y=0-7) Event
IMC300A iMOTION Controller with additional microcontroller 7 Interrupt Subsystem (NVIC) Table 99 VADC0_C0SR[1:0] and VADC0_GxSR[1:0] (x=0-1) - Source Event 1 event (continued) Type Register Bits Status flag VADC0_GxSEFLAG SEV1 Set flag VADC0_GxSEFLAG SEV1 Clear flag VADC0_GxSEFCLR SEV1 Node pointer VADC0_GxSEVNP SEV1NP 7.4.7.3 Channel Event y (y=0-7) event...
Page 155: Global Source Event
IMC300A iMOTION Controller with additional microcontroller 7 Interrupt Subsystem (NVIC) 7.4.7.6 Global Source Event Table 103 VADC0_C0SR[1:0] and VADC0_GxSR[1:0] (x=0-1) - Global Source Event Type Register Bits Interrupt enable VADC0_BRSMR ENSI Status flag VADC0_GLOBEFLAG SEVGLB Set flag VADC0_GLOBEFLAG SEVGLB Clear flag VADC0_GLOBEFLAG SEVGLBCLR Node pointer...
Page 156: Event 2 Edge(S) Information From Event Selector
IMC300A iMOTION Controller with additional microcontroller 7 Interrupt Subsystem (NVIC) Table 106 CCU4x_SR[3:0] (x=0-1) - Event 1 edge(s) information from event selector (continued) Type Register Bits Status flag CCU4x_CC4yINTS E1AS Set flag CCU4x_CC4ySWS SE1A Clear flag CCU4x_CC4ySWR RE1A Node pointer CCU4x_CC4ySRS E1SR 7.4.8.3...
Page 157: Compare Match While Counting Down Event
IMC300A iMOTION Controller with additional microcontroller 7 Interrupt Subsystem (NVIC) 7.4.8.6 Compare Match while counting down event Table 110 CCU4x_SR[3:0] (x=0-1) - Compare Match while counting down event Type Register Bits Interrupt enable CCU4x_CC4yINTE CMDE Status flag CCU4x_CC4yINTS CMDS Set flag CCU4x_CC4ySWS SCMD Clear flag...
Page 158: Event 1 Edge(S) Information From Event Selector
IMC300A iMOTION Controller with additional microcontroller 7 Interrupt Subsystem (NVIC) Table 113 CCU8x_SR[1:0] (x=0-1) - Event 0 edge(s) information from event selector (continued) Type Register Bits Status flag CCU8x_CC8yINTS E0AS Set flag CCU8x_CC8ySWS SE0A Clear flag CCU8x_CC8ySWR RE0A Node pointer CCU8x_CC8ySRS E0SR 7.4.9.2...
Page 159: Compare Match While Counting Up From Compare Channel 1 Event
IMC300A iMOTION Controller with additional microcontroller 7 Interrupt Subsystem (NVIC) 7.4.9.5 Compare Match while counting up from compare channel 1 event Table 117 CCU8x_SR[1:0] (x=0-1) - Compare Match while counting up from compare channel 1 event Type Register Bits Interrupt enable CCU8x_CC8yINTE CMU1E Status flag...
Page 160: Compare Match While Counting Down From Compare Channel 2 Event
IMC300A iMOTION Controller with additional microcontroller 7 Interrupt Subsystem (NVIC) 7.4.9.8 Compare Match while counting down from compare channel 2 event Table 120 CCU8x_SR[1:0] (x=0-1) - Compare Match while counting down from compare channel 2 event Type Register Bits Interrupt enable CCU8x_CC8yINTE CMD2E Status flag...
Page 161: Occurrence Of Correct Hall Event
IMC300A iMOTION Controller with additional microcontroller 7 Interrupt Subsystem (NVIC) Table 123 POSIFx.SR[1:0] (x=0-1) - Transition at Hall inputs events (continued) Type Register Bits Status flag POSIFx_PFLG HIES Set flag POSIFx_SPFLG SHIE Clear flag POSIFx_RPFLG RHIE Node pointer POSIFx_PFLGE HIESEL 7.4.10.2 Occurrence of correct Hall event Table 124...
Page 162: Index Event Detection Event
IMC300A iMOTION Controller with additional microcontroller 7 Interrupt Subsystem (NVIC) 7.4.10.5 Index event detection event Table 127 POSIFx.SR[1:0] (x=0-1) - Index event detection event Type Register Bits Interrupt enable POSIFx_PFLGE EINDX Status flag POSIFx_PFLG INDXS Set flag POSIFx_SPFLG SINDX Clear flag POSIFx_RPFLG RINDX Node pointer...
Page 163: Direction Change Event
IMC300A iMOTION Controller with additional microcontroller 7 Interrupt Subsystem (NVIC) Table 130 POSIFx.SR[1:0] (x=0-1) - Period clock generation event (continued) Type Register Bits Clear flag POSIFx_RPFLG RPCLK Node pointer POSIFx_PFLGE PCLSEL 7.4.10.9 Direction change event Table 131 POSIFx.SR[1:0] (x=0-1) - Direction change event Type Register Bits...
Page 164: Last Error Code Event
IMC300A iMOTION Controller with additional microcontroller 7 Interrupt Subsystem (NVIC) 7.4.11.3 Last Error Code event Table 134 CAN0.SR[3:0] - Last Error Code event Type Register Bits Interrupt enable CAN0_NCRx LECIE Status flag CAN0_NSRx Set flag Clear flag Node pointer CAN0_NIPRx LECINP 7.4.11.4 Fast Last Error Code event...
Page 165: Transmit Pending Event
IMC300A iMOTION Controller with additional microcontroller 7 Interrupt Subsystem (NVIC) Table 137 CAN0.SR[3:0] - Receive Pending event (continued) Type Register Bits Clear flag CAN0_MOCTRn RESRXPND Node pointer CAN0_MOIPRn RXINP 7.4.11.7 Transmit Pending event Table 138 CAN0.SR[3:0] - Transmit Pending event Type Register Bits...
Page 166: Event Request Unit (Eru)
IMC300A iMOTION Controller with additional microcontroller 8 Event Request Unit (ERU) Event Request Unit (ERU) As described in the Service Request Processing chapter, IMC300A uses the Event Request Unit (ERU) to support the programmable interconnection for the processing of service requests. There are 2 instances of ERU in IMC300A, ERU0 and ERU1.
Page 167: Event Request Select Unit (Ers)
IMC300A iMOTION Controller with additional microcontroller 8 Event Request Unit (ERU) • The Trigger Cross Connect Matrix distributes the events and status flags to the Output Channels. Additionally, trigger signals from other modules are made available and can be combined with the local triggers.
Page 168 IMC300A iMOTION Controller with additional microcontroller 8 Event Request Unit (ERU) Each of the four ETLx units has an associated EXICONx register, that controls all options of an ETLx (the register also holds control bits for the associated ERSx unit, e.g. EXICONx (x=0-3) to control ERS0 and ETL0).
Page 169: Cross Connect Matrix
IMC300A iMOTION Controller with additional microcontroller 8 Event Request Unit (ERU) Cross Connect Matrix The matrix shown in Figure 25 distributes the trigger signals (TRxy) and status signals (EXICONx.FL) from the different ETLx units between the OGUy units. In addition, it receives peripheral trigger signals that can be OR- combined with the ETLx trigger signals in the OGUy units.
Page 170: Output Gating Unit (Oguy)
IMC300A iMOTION Controller with additional microcontroller 8 Event Request Unit (ERU) Output Gating Unit (OGUy) Each OGUy (y = 0-3) unit combines the available trigger events and status flags from the Input Channels and distributes the results to the system. Figure 26 illustrates the logic blocks within an OGUy unit.
Page 171 IMC300A iMOTION Controller with additional microcontroller 8 Event Request Unit (ERU) • ERU_GOUTy to output the pattern match or pattern miss information (inverted pattern match), or a permanent 0 or 1 under software control for gating purposes in other modules. •...
Page 172: Power, Reset And Clock
IMC300A iMOTION Controller with additional microcontroller 8 Event Request Unit (ERU) A service request is issued when the trigger event occurs while the pattern detection shows a pattern miss. • Independent of pattern detection (EXOCONy.GP = 01 In this mode, each occurring trigger event leads to a service request. The pattern detection output can be used independently from the trigger combination for gating purposes of other peripherals (independent use of ERU_TOUTy and ERU_PDOUTy with service requests on trigger events).
Page 173: Eru Registers
IMC300A iMOTION Controller with additional microcontroller 8 Event Request Unit (ERU) Table 141 Register Overview (continued) Short Name Description Offset Access Mode Description Address Read Write EXICON0 ERU External Input Control Selection 0010 U, PV U, PV Page EXICON1 ERU External Input Control Selection 0014 U, PV U, PV...
Page 174: Register Exiconx
IMC300A iMOTION Controller with additional microcontroller 8 Event Request Unit (ERU) (continued) Field Bits Type Description EXS1A Event Source Select for A1 (ERS1) This bit field defines which input is selected for A1. Input ERU_1A0 is selected Input ERU_1A1 is selected Input ERU_1A2 is selected Input ERU_1A3 is selected EXS1B...
Page 175 IMC300A iMOTION Controller with additional microcontroller 8 Event Request Unit (ERU) EXICONx (x=0-3) Address: + 4*x Event Input Control x Reset Value: 0000 0000 Field Bits Type Description Output Trigger Pulse Enable for ETLx This bit enables the generation of an output trigger pulse at TRxy when the selected edge is detected (set condition for the status flag FL).
Page 176: Register Exoconx
IMC300A iMOTION Controller with additional microcontroller 8 Event Request Unit (ERU) (continued) Field Bits Type Description Output Channel Select for ETLx Output Trigger Pulse This bit field defines which Output Channel OGUy is targeted by an enabled trigger pulse TRxy. Trigger pulses are sent to OGU0 Trigger pulses are sent to OGU1 Trigger pulses are sent to OGU2...
Page 177 IMC300A iMOTION Controller with additional microcontroller 8 Event Request Unit (ERU) IPEN IPEN IPEN IPEN Field Bits Type Description Internal Trigger Source Selection This bit field defines which input is selected as peripheral trigger input for OGUy. The peripheral trigger function is disabled Input ERU_OGUy1 is selected Input ERU_OGUy2 is selected Input ERU_OGUy3 is selected...
Page 178: Interconnects
IMC300A iMOTION Controller with additional microcontroller 8 Event Request Unit (ERU) (continued) Field Bits Type Description 31:16, Reserved 11:6 Read as 0; should be written with 0. 8.10 Interconnects This section describes how the ERU0 and ERU1 module is connected within the IMC300A system. PORTS NVIC.SRn PORTS...
Page 179 IMC300A iMOTION Controller with additional microcontroller 8 Event Request Unit (ERU) Table 142 ERU0 Pin Connections (continued) Global Input/Output Connected To Description ERU0.0B0 P2.0 ERU0.0B1 P2.2 ERU0.0B2 ORC0.OUT ERU0.0B3 ERU0.1A0 ACMP1.OUT ERU0.1A1 ERU0.1A2 ERU0.1A3 ERU0.1B0 P2.1 ERU0.1B1 ERU0.1B2 ERU0.1B3 ERU0.2A0 ACMP2.OUT ERU0.2A1 P2.6...
Page 180 IMC300A iMOTION Controller with additional microcontroller 8 Event Request Unit (ERU) Table 142 ERU0 Pin Connections (continued) Global Input/Output Connected To Description ERU0.OGU21 CCU40.SR2 ERU0.OGU22 ERU0.OGU23 ERU0.OGU31 CCU40.SR3 ERU0.OGU32 ERU0.OGU33 ERU0.PDOUT0 CCU40.IN0AJ; CCU40.IN1AD; CCU41.IN0AJ; CCU41.IN1AD; USIC0_CH1.HWIN0; P2.11; ERU0.GOUT0 P2.11; ERU0.TOUT0 not connected ERU0.IOUT0 NVIC;...
Page 181: Eru1 Connections
IMC300A iMOTION Controller with additional microcontroller 8 Event Request Unit (ERU) Table 142 ERU0 Pin Connections (continued) Global Input/Output Connected To Description ERU0.GOUT2 P2.1; ERU0.TOUT2 not connected ERU0.IOUT2 NVIC; CCU40.IN2AK; CCU41.IN2AK; ERU0.PDOUT3 CCU40.IN2AD; CCU40.IN3AJ; CCU41.IN2AD; CCU41.IN3AJ; P2.0; ERU0.GOUT3 P2.0; ERU0.TOUT3 not connected ERU0.IOUT3 NVIC;...
Page 182 IMC300A iMOTION Controller with additional microcontroller 8 Event Request Unit (ERU) Table 143 ERU1 Pin Connections (continued) Global Input/Output Connected To Description ERU1.1B2 CCU80.ST3 ERU1.1B3 CCU81.ST3 ERU1.2A0 ACMP2.OUT ERU1.2A1 ERU1.2A2 P4.6 ERU1.2A3 ERU1.2B0 CCU40.ST2 ERU1.2B1 CCU41.ST2 ERU1.2B2 CCU80.ST1 ERU1.2B3 CCU81.ST1 ERU1.3A0 ACMP0.OUT ERU1.3A1...
Page 183 IMC300A iMOTION Controller with additional microcontroller 8 Event Request Unit (ERU) Table 143 ERU1 Pin Connections (continued) Global Input/Output Connected To Description ERU1.PDOUT0 CCU40.IN0AW; CCU40.IN1AY; CCU41.IN0AW; CCU41.IN1AY; POSIF1.IN0D; P4.0; ERU1.GOUT0 P4.0 ERU1.TOUT0 not connected ERU1.IOUT0 NVIC; CCU40.CLKA; CCU40.IN0AX; CCU41.IN0AX; CCU41.CLKB; POSIF1.EWHEB;...
Page 184 IMC300A iMOTION Controller with additional microcontroller 8 Event Request Unit (ERU) Table 143 ERU1 Pin Connections (continued) Global Input/Output Connected To Description ERU1.IOUT2 NVIC; CCU40.IN2AX; CCU41.IN2AX; POSIF1.MSETF; ERU1.PDOUT3 CCU40.IN3AW; CCU40.IN2AY; CCU41.IN2AY; CCU41.IN3AW; P4.3; ERU1.GOUT3 P4.3 ERU1.TOUT3 not connected ERU1.IOUT3 NVIC; CCU40.IN3AX;...
Page 185: Bus System
IMC300A iMOTION Controller with additional microcontroller 9 Bus System Bus System The single master bus system in IMC300A consists of a high-performance system bus based on the industry AMBA 3 AHB-Lite Protocol standard for memories and high-bandwidth on-chip peripherals and a narrower APB for low-bandwidth on-chip peripherals.
Page 186: Memory Organization
IMC300A iMOTION Controller with additional microcontroller 10 Memory Organization Memory Organization This chapter provides description of the system memory organization, memory accesses and memory protection strategy. 10.1 Overview ™ The memory map in IMC300A is based on standard ARM Cortex-M0 system memory map. 10.1.1 Features The memory map implements the following features:...
Page 187: Memory Regions
IMC300A iMOTION Controller with additional microcontroller 10 Memory Organization 10.2 Memory Regions The IMC300A device-specific address map contains on-chip memories and peripherals. The memory regions for IMC300A are described in Table 144. Table 144 Memory Regions Start (hex) End (hex) Size (hex) Space name Usage...
Page 188 IMC300A iMOTION Controller with additional microcontroller 10 Memory Organization Table 145 Address space: Code (continued) Address range Description Access Type Read Write 10000000 - 10000DFF Flash Sector 0 (non-user-readable) 10000E00 - 10000FFF Flash Sector 0 U, PV (user-readable) 10001000 - 10020FFF Flash (128 Kbytes) U, PV U, PV...
Page 189 IMC300A iMOTION Controller with additional microcontroller 10 Memory Organization Table 147 Address space: System peripherals (continued) Address range Description Access Type Read Write 40040000 - 4004007F Port 0 U, PV U, PV 40040080 - 400400FF reserved 40040100 - 4004017F Port 1 U, PV U, PV 40040180...
Page 190 IMC300A iMOTION Controller with additional microcontroller 10 Memory Organization Table 148 Address space: Central peripherals (continued) Address range Description Access Type Read Write 48034000 - 480341FF SHS0 U, PV U, PV 48034200 - 4803FFFF reserved 48040000 - 480401FF CCU40 CC40 and Kernel U, PV U, PV Registers...
Page 191 IMC300A iMOTION Controller with additional microcontroller 10 Memory Organization Table 149 Address space: Application peripherals (continued) Address range Description Access Type Read Write 50014000 - 500141FF POSIF1 U, PV U, PV 50014200 - 5001FFFF reserved 50020000 - 5003FFFF reserved 50040000 - 500402FF MultiCAN Node 0 and U, PV...
Page 192: Memory Access
IMC300A iMOTION Controller with additional microcontroller 10 Memory Organization Address space: Vendor specific 1 Table 153 Address space: Vendor specific 1 Address range Description Access Type Read Write E0100000 - EFFFFFFF reserved Address space: Vendor specific 2 Table 154 Address space: Vendor specific 2 Address range Description Access Type...
Page 193: Rom Access
IMC300A iMOTION Controller with additional microcontroller 10 Memory Organization 10.4.3 ROM Access The IMC300A provides 8 Kbytes of ROM, which contains the startup software, vector table and user routines. Read accesses to the ROM require no wait states. 10.5 Memory Protection Strategy Two aspects of memory protection are considered: Intellectual Property (IP) Protection Memory Access Protection during Run-time...
Page 194: Register Scu_Passwd
IMC300A iMOTION Controller with additional microcontroller 10 Memory Organization Access is opened for maximum 32 MCLKs if the “close access” password is not written. If “open access” password is written again before the end of 32 MCLK cycles, there will be a recount of 32 MCLK cycles. Table 156 shows the list of protected bit in IMC300A.
Page 195: Peripheral Privilege Access Control
IMC300A iMOTION Controller with additional microcontroller 10 Memory Organization Field Bits Type Description MODE Bit Protection Scheme Control Bits Scheme disabled - direct access to the protected bits is allowed. Scheme enabled - the bit field PASS has to be written with the passwords to open and close the access to the protected bits.
Page 196: Debug Behaviour
IMC300A iMOTION Controller with additional microcontroller 10 Memory Organization Invalid Address Accesses to invalid addresses result in error responses. Invalid addresses are defined as those that do not mapped to any valid resources. This applies to single addresses and to wider address ranges. Some invalid addresses within valid module address ranges may not produce error responses and this is specific to individual modules.
Page 197: Peripheral Access Unit (Pau)
IMC300A iMOTION Controller with additional microcontroller 11 Peripheral Access Unit (PAU) Peripheral Access Unit (PAU) This chapter describes Peripheral Access Unit (PAU) in IMC300A. 11.1 Overview The PAU supports access control of memories and peripherals in a central place. 11.1.1 Features The PAU provides the following features: •...
Page 198: Peripheral Availability And Memory Size
IMC300A iMOTION Controller with additional microcontroller 11 Peripheral Access Unit (PAU) Table 157 Peripherals Availability and Privilege Access Control (continued) Peripheral Address Grouping AVAILn.AVAILx bit PRIVDIS.PDISx bit VADC0 Group 1 SFRs AVAIL1.7 PRIVDIS1.7 SHS0 SHS0 AVAIL1.8 PRIVDIS1.8 CCU40 CCU40_CC40 and CCU40 Kernel AVAIL1.9 PRIVDIS1.9 SFRs...
Page 199: Service Request Generation
IMC300A iMOTION Controller with additional microcontroller 11 Peripheral Access Unit (PAU) 11.4 Service Request Generation The PAU generates a hard fault exception when there is an access to an invalid address. 11.5 Debug Behaviour The PAU does not support a suspend mode while the system is halted by the debugger. That means that the PAU continues its operation during debug halt.
Page 200: Peripheral Privilege Access Registers (Privdisn)
IMC300A iMOTION Controller with additional microcontroller 11 Peripheral Access Unit (PAU) Table 159 Register Overview (continued) Short Name Description Offset Access Mode Description See Addr. Read Write FLSIZE Flash Size Register 0404 U, PV Page RAM0SIZE RAM0 Size Register 0410 U, PV Page Reserved...
Page 201: Register Privdis1
IMC300A iMOTION Controller with additional microcontroller 11 Peripheral Access Unit (PAU) (continued) Field Bits Type Description PDIS19 WDT Privilege Disable Flag WDT is accessible. WDT is not accessible. PDIS20 MATH Global SFRs and Divider Privilege Disable Flag MATH Global SFRs and Divider are accessible. MATH Global SFRs and Divider are not accessible.
Page 202 IMC300A iMOTION Controller with additional microcontroller 11 Peripheral Access Unit (PAU) Field Bits Type Description PDIS0 USIC0 Channel 0 Privilege Disable Flag USIC0 Channel 0 is accessible. USIC0 Channel 0 is not accessible. PDIS1 USIC0 Channel 1 Privilege Disable Flag USIC0 Channel 1 is accessible.
Page 203: Register Privdis2
IMC300A iMOTION Controller with additional microcontroller 11 Peripheral Access Unit (PAU) (continued) Field Bits Type Description PDIS26 CCU41 CC41 Privilege Disable Flag CCU41 CC41 is accessible. CCU41 CC41 is not accessible. PDIS27 CCU41 CC42 Privilege Disable Flag CCU41 CC42 is accessible. CCU41 CC42 is not accessible.
Page 204: Peripheral Availability Registers (Availn)
IMC300A iMOTION Controller with additional microcontroller 11 Peripheral Access Unit (PAU) (continued) Field Bits Type Description PDIS12 POSIF0 Privilege Disable Flag POSIF0 is accessible. POSIF0 is not accessible. PDIS15 DAC0 Privilege Disable Flag DAC0 is accessible. DAC0 is not accessible. PDIS16 CCU81 Kernel SFRs and CC80 Privilege Disable Flag CCU81 Kernel SFRs and CC80 are accessible.
Page 205: Register Avail0
IMC300A iMOTION Controller with additional microcontroller 11 Peripheral Access Unit (PAU) 11.8.2.1 Register AVAIL0 AVAIL0 Address: 0040 Peripheral Availability Register 0 Reset Value: 07FF 00FF AVAI AVAI AVAI AVAI AVAI AVAI AVAI AVAI AVAI AVAI Field Bits Type Description AVAIL5 RAM Block 1 Availability Flag RAM block 1 is not available.
Page 206: Register Avail1
IMC300A iMOTION Controller with additional microcontroller 11 Peripheral Access Unit (PAU) (continued) Field Bits Type Description AVAIL26 Port 4 Availability Flag Port 4 is not available. Port 4 is available. 19:16, 4:0 r Reserved 31:27, Reserved 15:8 11.8.2.2 Register AVAIL1 AVAIL1 Address: 0044...
Page 207: Register Avail2
IMC300A iMOTION Controller with additional microcontroller 11 Peripheral Access Unit (PAU) (continued) Field Bits Type Description AVAIL8 SHS0 Availability Flag SHS0 is not available. SHS0 is available. AVAIL9 CCU40 kernel SFRs and CC40 Availability Flag CCU40 kernel SFRs and CC40 is not available. CCU40 kernel SFRs and CC40 is available.
Page 208 IMC300A iMOTION Controller with additional microcontroller 11 Peripheral Access Unit (PAU) AVAIL2 Address: 0048 Peripheral Availability Register 2 Reset Value: 30BFF00F AVAI AVAI AVAI AVAI AVAI AVAI AVAI AVAI AVAIL AVAI AVAI AVAI AVAI AVAI Field Bits Type Description AVAIL0 CCU80 kernel SFRs and CC80 Availability Flag CCU80 kernel SFRs and CC80 are not available.
Page 209: Memory Size Registers
IMC300A iMOTION Controller with additional microcontroller 11 Peripheral Access Unit (PAU) (continued) Field Bits Type Description AVAIL19 CCU81 CC83 Availability Flag CCU81 CC83 is not available. CCU81 CC83 is available. AVAIL20 MultiCAN Node 0 and Global SFRs Availability Flag MultiCAN node 0 and Global SFRs are not available. MultiCAN node 0 and Global SFRs are available.
Page 210: Register Flsize
IMC300A iMOTION Controller with additional microcontroller 11 Peripheral Access Unit (PAU) Field Bits Type Description ADDR 13:8 ROM Size Size of user-readable ROM in bytes = ADDR * 256 31:14, 7:0 r Reserved 11.8.3.2 Register FLSIZE FLSIZE Address: 0404 Flash Size Register Reset Value: ADDR ADDR...
Page 211 IMC300A iMOTION Controller with additional microcontroller 11 Peripheral Access Unit (PAU) (continued) Field Bits Type Description 31:13, 7:0 r Reserved Reference Manual V1.0 2020-05-28...
Page 212: Flash Architecture
IMC300A iMOTION Controller with additional microcontroller 12 Flash Architecture Flash Architecture This chapter describes the non volatile memory (NVM) module. 12.1 Overview The IMC300A has an embedded user-programmable NVM for storage of user code and data. 12.1.1 Features The NVM has the following features: •...
Page 213: Data Portions
IMC300A iMOTION Controller with additional microcontroller 12 Flash Architecture The erased state of a cell is ‘1’. Forcing an NVM cell to this state is called erasing. Erasing is possible with a granularity of a page (see below). Writing The written state of a cell is ‘0’. Changing an erased cell to this state is called writing. Writing is possible with a granularity of a block (see below).
Page 214: Module Components
IMC300A iMOTION Controller with additional microcontroller 12 Flash Architecture Table 160 Module Specific Definitions Module size [KB] 128 + 4 Constant name Value Comment N_BLOCKS Number of blocks per page N_PAGES Number of pages per sector N_LOG_SEC 32 + 1 Number of sectors (RW + RO) 12.3 Module Components...
Page 215: Sector
IMC300A iMOTION Controller with additional microcontroller 12 Flash Architecture Block N_BLOCK-1 Block 0 Block 1 138-bit data (including parity and ECC) Page_structure.vsd Figure 31 Structure of a Page 12.3.1.2 Sector 16 pages form a sector. 12.4 Functional Description The NVM module supports read and write accesses to the memory and to the special function registers (SFRs). No read-modify-write mechanism is supported for SFRs.
Page 216: Memory Erase
IMC300A iMOTION Controller with additional microcontroller 12 Flash Architecture not observed, the already provided words are discarded. If in this case the last provided word is addressing a word 0, this word is already accepted as the first word of a new block write procedure. Intermediate read operations do not influence the write data transfer.
Page 217: Erase-Protection And Write-Protection
IMC300A iMOTION Controller with additional microcontroller 12 Flash Architecture compared to the normal read level to ensure that the data is really programmed with suitably distinct levels for written and erased bits. The verification result can be read at SFR NVMSTATUS. Stand-alone verify operations can also be started by setting the SFR NVMPROG to the corresponding value.
Page 218: Power, Reset And Clock
IMC300A iMOTION Controller with additional microcontroller 12 Flash Architecture 12.7 Power, Reset and Clock The following sections describe the power, reset and clock sources of the NVM module. 12.7.1 Power Supply The NVM module sources all voltages required for read, program and erase operations from the on-chip Embedded Voltage Regulator (EVR).
Page 219: Nvm Register
IMC300A iMOTION Controller with additional microcontroller 12 Flash Architecture Table 162 Registers Overview Register Short Name Register Long Name Offset Address Page Number NVMSTATUS NVM Status Register 0000 Page NVMPROG NVM Programming Control Register 0004 Page NVMCONF NVM Configuration Register 0008 Page Registers Access...
Page 220: Register Nvmprog
IMC300A iMOTION Controller with additional microcontroller 12 Flash Architecture (continued) Field Bits Type Description ECC1READ ECC1 Read The flag accumulates ECC single bit failure during the last memory read operations. It is reset by hardware when NVMPROG.RSTECC is written. ECC1RDOK, No ECC single bit failure occurred. ECC1RDFAIL, At least one ECC single bit failure was detected and corrected.
Page 221 IMC300A iMOTION Controller with additional microcontroller 12 Flash Architecture RSTE RSTV ACTION Field Bits Type Description 15:14 Reserved Read as 0; should by written with 0. RSTECC Reset ECC Can only be set by software, is reset automatically by hardware. NOP, No action.
Page 222 IMC300A iMOTION Controller with additional microcontroller 12 Flash Architecture (continued) Field Bits Type Description ACTION ACTION: [VERIFY, ONE_SHOT, OPTYPE] This field selects an erase, write, or verify operation. See also More details on ACTION. ACTION is a concatenation of three bit fields: ACTION[7:6] = VERIFY, ACTION[5:4] = ONE_SHOT and ACTION[3:0] = OPTYPE.
Page 223: Register Nvmconf
IMC300A iMOTION Controller with additional microcontroller 12 Flash Architecture If the correct erasing of a page or sector is to be verified, a separate sequence using ACTION.VERIFY = 11 has to be started. A verify operation requires the provision of the data for a complete block and always includes the ECC bits. The ECC bits for every block are generated automatically when the data is written.
Page 224: Example Sequences
IMC300A iMOTION Controller with additional microcontroller 12 Flash Architecture (continued) Field Bits Type Description SECPROT 11:4 Sector Protection This field defines the number of write, erase, verify protected sectors, starting with physical sector 0. Reserved Read as 0; should be written with 0. HRLEV Hardread Level Defines single hardread level for verification with...
Page 225: Writing Blocks
IMC300A iMOTION Controller with additional microcontroller 12 Flash Architecture 12.9.1.2 Writing Blocks This sequence requires the target blocks are already erased. Additional assumption: NVMPROG.ACTION = 00 Start a continuous write operation: Write NVMPROG.ACTION = 61 or A1 , respectively, if an automatic verification of the written data is to be performed or not.
Page 226: Erasing Sectors
IMC300A iMOTION Controller with additional microcontroller 12 Flash Architecture 12.9.2.4 Erasing Sectors Assumption: NVMPROG.ACTION = 00 Start a continuous sector erase operation: Write NVMPROG.ACTION = A4 Write dummy data for one word to one arbitrary word-aligned physical address of the sector to be erased.
Page 227: Sleep Mode
IMC300A iMOTION Controller with additional microcontroller 12 Flash Architecture Table 163 Incremental Update of a Block with Specially Constructed Data Operation Block Write Data Resulting Block Content Erase block FFFFFFFF FFFFFFFF FFFFFFFF FFFFFFFF Add 1 value FFFFFFFF FFFFFFFC FFFFFFFF FFFFFFFC FFFFFFFF FFFFFFFC FFFFFFFF FFFFFFFC Add 2 value...
Page 228: Timing
IMC300A iMOTION Controller with additional microcontroller 12 Flash Architecture NVMSTATUS.BUSY = 1 and NVMSTATUS.SLEEP = 1 until sleep mode is reached. NVMSTATUS.BUSY = 0 and NVMSTATUS.SLEEP = 1 while in sleep mode. To Wake-up from Sleep Mode Any wake-up event and NVMCONF.NVM_ON = 1 NVMSTATUS.BUSY = 1 and NVMSTATUS.SLEEP = 1 until active mode is reached.
Page 229 IMC300A iMOTION Controller with additional microcontroller 12 Flash Architecture block write complete Erase sleep_req=1 or VerifyWait VerifyBlock new NVM_ON=0 GotoSleep VERIFY=3, BUSY=0 BUSY=1 BUSY=1 block verify done erase (block verify done and ONE_SHOT=1) memory block write operation or new ACTION=0 write complete done...
Page 230: Prefetch Unit (Pfu)
IMC300A iMOTION Controller with additional microcontroller 13 Prefetch Unit (PFU) Prefetch Unit (PFU) The purpose of the Prefetch unit is to reduce the Flash latency gap at higher system frequencies to increase the instruction per cycle performance. 13.1 Overview The PFU consists mainly of: •...
Page 231: Pfu Control Register
IMC300A iMOTION Controller with additional microcontroller 13 Prefetch Unit (PFU) 13.2.1 PFU Control Register The PFU control register, PFUCR, is used to enable or disable the bypass to the PFU. This register is located in the SCU and is also described in the SCU chapter. 13.2.1.1 Register SCU_PFUCR SCU_PFUCR...
Page 232: System Control Unit (Scu)
IMC300A iMOTION Controller with additional microcontroller 14 System Control Unit (SCU) System Control Unit (SCU) The SCU is the SoC power, reset and a clock manager with additional responsibility of providing system stability protection and other auxiliary functions. 14.1 Overview The functionality of the SCU described in this chapter is organized in the following sub-chapters, representing different aspects of system control: •...
Page 233 IMC300A iMOTION Controller with additional microcontroller 14 System Control Unit (SCU) All the SFRs in SCU module are accessible via the AHB and the 16-bit APB bus interface as shown in Figure 34.The APB bus interface is used to access the group of SFR called ANACTRL register. These registers are used to configure the analog modules in the system, namely, the embedded voltage regulator (EVR) and the digitally controlled oscillators (DCO1 and DCO2).
Page 234: Miscellaneous Control Functions (Gcu)
IMC300A iMOTION Controller with additional microcontroller 14 System Control Unit (SCU) Interface of Clock Control Unit The Clock Control Unit (CCU) receives the clock source from the on-chip Digitally Controlled Oscillator (DCO). The CCU provides the clock signals to all other units of the chip. Interface of RTC Access to the RTC module is served over a serial interface.
Page 235: Service Request Sources
IMC300A iMOTION Controller with additional microcontroller 14 System Control Unit (SCU) 14.2.1.1 Service Request Sources The SCU supports service request sources listed in Table 164 and reflected in the SRRAW/SRRAW1, SRMSK/ SRMSK1, SRCLR/SRCLR1 SRSET/SRSET1 registers. The events that trigger these service requests are described in the respective module chapters or in the various sections within SCU.
Page 236: Summary Of Id
IMC300A iMOTION Controller with additional microcontroller 14 System Control Unit (SCU) All on-chip SRAMs provide protection of content via parity checking. The parity logic generates additional parity bits which are stored along with each data word at a write operation. A read operation implies checking of the previous stored parity information.
Page 237: Power Management (Pcu)
IMC300A iMOTION Controller with additional microcontroller 14 System Control Unit (SCU) • ASC BSL • CAN BSL • User productive mode • User Boot mode The input of boot pin are latched during the de-assertion of reset and stored in register bit STSTAT.HWCON. More details about the selection of this mode can be found in the “Boot and Startup”...
Page 238: Embedded Voltage Regulator (Evr)
IMC300A iMOTION Controller with additional microcontroller 14 System Control Unit (SCU) Sleep State The sleep state of the system corresponds to the sleep state of the CPU. The state is entered via WFI or WFE instruction of the CPU. In this state, the clock to the CPU is stopped. To save power, the clock of the peripherals that are not needed during sleep state can be gated by register CGATSET0 before entering sleep state.
Page 239: Power Validation
IMC300A iMOTION Controller with additional microcontroller 14 System Control Unit (SCU) 14.3.5 Power Validation A power validation circuit monitors the internal core supply voltage,V . It monitors that the core voltage is above the voltage threshold V which guarantees safe operation. Whenever the voltage falls below the DDCBO threshold level, a brownout reset is generated.
Page 240: Flash Power Control
IMC300A iMOTION Controller with additional microcontroller 14 System Control Unit (SCU) During a VDROP event, clock blanking happens and the detail description is documented in Clock Blanking page 244. CPU clock and peripheral clocks continue to run during VCLIP event. Note: When overflow event happens while the VDROP=1 (time to overflow based on the CNTADJ value is shorter than the time the device stays in a vdrop event), the 10-bit counter will automatically be...
Page 241: Reset Status
IMC300A iMOTION Controller with additional microcontroller 14 System Control Unit (SCU) • Loss of DCO1 clock when enabled • sources that trigger a master reset A system reset affects almost all logics. The only exceptions are RCU registers and Debug system when debug probe is present.
Page 242: Clock System And Control
IMC300A iMOTION Controller with additional microcontroller 14 System Control Unit (SCU) • Clock Supervisory Oscillator watchdog • Wide range of frequency scaling of system frequencies • Individual peripheral clock gating • Calibration of DCO based on external reference clock or the temperature sensor •...
Page 243 IMC300A iMOTION Controller with additional microcontroller 14 System Control Unit (SCU) IDIV[7:0] FDIV[9:0] Sync Unit DCO1 DCO1 MATH CCU8x POSIFx CCU4x DAC0 CLKCR.PCLKSEL MATH POSIF 8 - 96MHz CCU8 CCU4 DAC_clk Fractional PCLK Clock divider Doubler DCLK blanking n:1024 Divide MCLK by 2 PERIPH...
Page 244 IMC300A iMOTION Controller with additional microcontroller 14 System Control Unit (SCU) Table 167 PCLK and MCLK frequency range (continued) DCLK clock source DCLK frequency PCLK frequency MCLK frequency External oscillator via OSC_HP in 8MHz - 40MHz 15.6kHz - 40MHz 15.6kHz - 20MHz osc mode (4 - 20MHz) External clock via OSC_HP in...
Page 245 IMC300A iMOTION Controller with additional microcontroller 14 System Control Unit (SCU) The clock blanking is activated when V is detected to be below the VDROP threshold. Once the V is above this threshold, the enabled clocking is resume. This voltage drop detector is part of the EVR and it is activated by default upon any reset.
Page 246: Dco1 Oscillator Watchdog
IMC300A iMOTION Controller with additional microcontroller 14 System Control Unit (SCU) Fundamental Mode Crystal XTAL1 OSC_HP OSC_HP XTAL2 Figure 39 External Crystal Mode Circuitry for the High-Precision Oscillator MultiCAN+ Clock Figure 40 show the clock selection via the MultiCAN+ register bit CAN_MCR.CLKSEL. Refer to MultiCAN+ chapter for detailed description.
Page 247: Loss Of Dco1 Clock Detection And Recovery
IMC300A iMOTION Controller with additional microcontroller 14 System Control Unit (SCU) 14.5.2.2 Loss of DCO1 Clock Detection and Recovery Loss of DCO1 clock happens when the oscillator watchdog (OWD) detects a DCO1 frequency that is less than 75MHz or more than 105MHz during normal operation. In this case, an interrupt will be generated if it is enabled.
Page 248: Startup Control For System Clock
IMC300A iMOTION Controller with additional microcontroller 14 System Control Unit (SCU) The IMM100 remains in this loss of clock state until the next reset or after a successful clock recovery has been performed. A clock recovery could be carried out by restarting the detection by setting bit OSCCSR.XOWDRES. Upon detecting a stable external clock frequency, MCLK/PCLK will switched automatically to the external clock source.
Page 249 IMC300A iMOTION Controller with additional microcontroller 14 System Control Unit (SCU) OFFSET steps = b + a − b c − d e − d Equation 6 where : OFFSET value is range from 0 to 255 c is the measured temperature [°C] a is constant DCO_ADJLO_T2 b is constant DCO_ADJLO_T1 d is constant ANA_TSE_T1...
Page 250 IMC300A iMOTION Controller with additional microcontroller 14 System Control Unit (SCU) dco1_clk (48MHz) DCO1 ADJL inputs SYNC_DCO_EN Default XTAL_SEL Clock Synchronisation RTC_XTAL 1 32.768kHz Unit RTC_XTAL 2 OSC_LP Refclk XTAL 1 4 - 20MHz ANAOFFSET. XTAL 2 OSC_HP ADJL_OFFSET SYNC_ PRESCALER PRELOAD Figure 41...
Page 251 IMC300A iMOTION Controller with additional microcontroller 14 System Control Unit (SCU) Using OSC_HP as Reference for Calibration When OSC_HP is used, according to the wide range of selectable f frequency (e.g 4 - 20MHz crystal OSC_HP oscillator), these two values have to be calculated once for a defined and constant crystal frequency based on the formula 3000 ×...
Page 252 IMC300A iMOTION Controller with additional microcontroller 14 System Control Unit (SCU) 14.8 Power, Reset and Clock The SCU module implements functions that involve varoius types of modules controlled directly or via dedicated interfaces that are instantiated in different power, clock and reset domains. These modules are functionally considered parts of the SCU and therefore SCU is also considered a multi domain circuit in this sense.
Page 253 IMC300A iMOTION Controller with additional microcontroller 14 System Control Unit (SCU) Table 173 Registers Address Space Module Base Address End Address Note 4001 0000 4001 FFFF System Control Unit Registers Table 174 Registers Overview Short Name Description Offset Addr. Access Mode Description See Read Write...
Page 254 IMC300A iMOTION Controller with additional microcontroller 14 System Control Unit (SCU) Table 174 Registers Overview (continued) Short Name Description Offset Addr. Access Mode Description See Read Write ANASYNC2 DCO1 Sync 107C U, PV U,PV Page Control Register ANAOSCLPCTRL OSC_LP Control 108C U, PV U,PV...
Page 255 IMC300A iMOTION Controller with additional microcontroller 14 System Control Unit (SCU) Table 174 Registers Overview (continued) Short Name Description Offset Addr. Access Mode Description See Read Write SRMSK1 Service Request 005C U, PV U, PV Page Mask 1 SRCLR1 Service Request 0060 U, PV U, PV...
Page 256 IMC300A iMOTION Controller with additional microcontroller 14 System Control Unit (SCU) Field Bits Type Description VDEL_SELECT VDEL Range Select With these bits the VDDP range is set. 2.25V 3.0V 4.4V VDEL_TIM_ADJ VDEL Timing Setting These bits control the reaction speed of the VDEL. The value is determined by characterisation.
Page 257 IMC300A iMOTION Controller with additional microcontroller 14 System Control Unit (SCU) (continued) Field Bits Type Description VDDPPW VDDPPW Indication VDDP is above pre-warning threshold VDDP is below pre-warningthreshold 31:2 Reserved Read as 0; should be written with 0. 14.9.3 CCU Registers (SCU) 14.9.3.1 Register CLKCR Clock control register.
Page 258 IMC300A iMOTION Controller with additional microcontroller 14 System Control Unit (SCU) (continued) Field Bits Type Description IDIV 15:8 Divider Selection Divider is bypassed. 254; 255; Refer to Table 168 for some examples of MCLK frequency based on the value of IDIV. This bit is protected by the bit protection scheme as described in Memory Organization chapter PCLKSEL...
Page 259 IMC300A iMOTION Controller with additional microcontroller 14 System Control Unit (SCU) (continued) Field Bits Type Description VDDC2LOW VDDC too low VDDC is not too low and the fractional divider input clock is running at the targeted frequency VDDC is too low and the fractional divider input clock is not running at the targeted frequency VDDC2HIGH VDDC too high...
Page 260 IMC300A iMOTION Controller with additional microcontroller 14 System Control Unit (SCU) (continued) Field Bits Type Description DCLKSEL Doubler Clock Source Select DCO1 External clock via OSC_HP This bit is protected by the bit protection scheme as described in Memory Organization chapter 7:2,31:10 r Reserved Read as 0.
Page 261 IMC300A iMOTION Controller with additional microcontroller 14 System Control Unit (SCU) POSI USIC CCU4 CCU8 POSI USIC CCU4 CCU8 DAC0 Field Bits Type Description VADC VADC and SHS Gating Status gating de-asserted gating asserted CCU80 CCU80 Gating Status gating de-asserted gating asserted CCU40 CCU40 Gating Status...
Page 262 IMC300A iMOTION Controller with additional microcontroller 14 System Control Unit (SCU) (continued) Field Bits Type Description CCU41 CCU41 Gating Status gating de-asserted gating asserted USIC1 USIC1 Gating Status gating de-asserted gating asserted POSIF1 POSIF1 Gating Status gating de-asserted gating asserted MCAN0 MultiCAN Gating Status gating de-asserted...
Page 263 IMC300A iMOTION Controller with additional microcontroller 14 System Control Unit (SCU) (continued) Field Bits Type Description CCU40 CCU40 Gating Set no effect enable gating USIC0 USIC0 Gating Set no effect enable gating DAC0 DAC0 Gating Set no effect enable gating POSIF0 POSIF0 Gating Set no effect...
Page 264 IMC300A iMOTION Controller with additional microcontroller 14 System Control Unit (SCU) 14.9.3.6 Register CGATCLR0 Clock gating disable for IMC300A peripherals. Write one to selected bit to disable gating of corresponding clock, writing zeros has no effect. CGATCLR0 Address: 0310 Peripheral 0 Clock Gating Clear Reset Value: 0000 0000 POSI...
Page 265 IMC300A iMOTION Controller with additional microcontroller 14 System Control Unit (SCU) (continued) Field Bits Type Description RTC Gating Clear no effect disable gating CCU81 CCU81 Gating Clear no effect disble gating CCU41 CCU41 Gating Clear no effect disable gating USIC1 USIC1 Gating Clear no effect disable gating...
Page 266 IMC300A iMOTION Controller with additional microcontroller 14 System Control Unit (SCU) Field Bits Type Description OSC2L Oscillator Valid Low Status Bit This bit indicates if the frequency output of OSC is usable. This is checked by the Oscillator Watchdog The OSC frequency is usable The OSC frequency is not usable.
Page 267 IMC300A iMOTION Controller with additional microcontroller 14 System Control Unit (SCU) 14.9.4 CCU Registers (ANACTRL) 14.9.4.1 Register ANAOFFSET DCO1 Offset register. User is able to use bit ADJL_OFFSET to calibrate the DCO1 based on the temperature. ANAOFFSET Address: 106C DCO1 Offset Register Reset Value: 0040 ADJL_OFFSET...
Page 268 IMC300A iMOTION Controller with additional microcontroller 14 System Control Unit (SCU) Field Bits Type Description MODE OSC_LP Oscillator Mode Oscillator is enabled and in operation mode (OSC mode) Reserved Reserved Oscillator is in power down mode , Pad can be used in GPIO mode 15:2 Reserved...
Page 269 IMC300A iMOTION Controller with additional microcontroller 14 System Control Unit (SCU) (continued) Field Bits Type Description MODE OSC_HP Oscillator Mode This bit is protected by the bit protection scheme as described in Memory Organization chapter Oscillator is enabled and in active power mode with shaper enabled (OSC mode) Oscillator in power down mode with shaper enabled (External Clock Input Mode).
Page 270 IMC300A iMOTION Controller with additional microcontroller 14 System Control Unit (SCU) Field Bits Type Description SYNC_PRELOAD 13:0 Counter target value, which defines the update cycle Together with the bit field PRESCALER, this SFR field defines the DCO1 target frequency. This counter value has to be calculated according to the external clock frequency and prescaler value.
Page 271 IMC300A iMOTION Controller with additional microcontroller 14 System Control Unit (SCU) (continued) Field Bits Type Description SYNC_READY DCO1 frequency reached its target value If the DCO1 frequency is close to its target frequency, this bit has to be set. Actual DCO1 frequency is out of targe DCO1 is synchronized to the XTAL frequency Note: This bit is set to low after the synchronisation unit is...
Page 272 IMC300A iMOTION Controller with additional microcontroller 14 System Control Unit (SCU) (continued) Field Bits Type Description LCKEN Enable Lockup Status Reset by Lockup disabled Reset by Lockup enabled 31:11 Reserved 14.9.5.2 Register RSTSET Selective configuration of reset behaviour in the system. Write one to set selected bit, writing zeros has no effect.
Page 273 IMC300A iMOTION Controller with additional microcontroller 14 System Control Unit (SCU) Field Bits Type Description RSCLR Clear Reset Status no effect Clears field RSTSTAT.RSTSTAT LCKEN Enable Lockup Reset no effect Disable reset when Lockup gets asserted 9:1,31:11 r Reserved 14.9.5.4 Register RSTCON Enabling of reset triggered by critical events.
Page 274 IMC300A iMOTION Controller with additional microcontroller 14 System Control Unit (SCU) (continued) Field Bits Type Description MPERSTEN Enable MultiCAN+SRAM Parity Error Reset No reset when MultiCAN+ memory parity error occur Reset when MultiCAN+ memory parity error occur LOECRSTEN Enable Loss of External Clock Reset No reset when loss of external clock occur Reset when loss of external clock occur MRSTEN...
Page 275 IMC300A iMOTION Controller with additional microcontroller 14 System Control Unit (SCU) IDCHIP Address: 0004 Chip ID Register Reset Value: 0000 0000 IDCHIP IDCHIP Field Bits Type Description IDCHIP 31:0 CHIP ID 1XXX X00X IMC Family 1XXX X00X IMD Family 3XXX XXXX IMM Family 4XXX XXXX IMI Family...
Page 276 IMC300A iMOTION Controller with additional microcontroller 14 System Control Unit (SCU) Field Bits Type Description MANUFID 11:1 Manufactory Identity PARTNO 27:12 Part Number VERSION 31:28 Product version Reserved Read as 1; should be written with 1. 14.9.6.4 Register SSW0 Software support registers. SSW0 is used to change the BMI value.
Page 277 IMC300A iMOTION Controller with additional microcontroller 14 System Control Unit (SCU) Field Bits Type Description GSC40 Global Start Control CCU40 This register can be used to control a synchronous start of multiple timers of CCU40. It also can be used to control additional functions that are available in the timers, e.g.
Page 278 IMC300A iMOTION Controller with additional microcontroller 14 System Control Unit (SCU) SRRAW Address: 0038 SCU Raw Service Request Status Reset Value: 0000 0000 TSE_ RTC_ RTC_ TSE_ TSE_ RTC_ RTC_ RTC_ SBYC VCLI FLEC PESR ATIM ATIM LOCI HIGH TIM1 TIM0 LKFI Field...
Page 279 IMC300A iMOTION Controller with additional microcontroller 14 System Control Unit (SCU) (continued) Field Bits Type Description LOCI Loss of DCO1 Clock Event Status Before Masking Event has not occurred Event has occurred PESRAMI 16kbytes SRAM Parity Error Event Status Before Masking Event has not occurred Event has occurred PEU0I...
Page 280 IMC300A iMOTION Controller with additional microcontroller 14 System Control Unit (SCU) (continued) Field Bits Type Description TSE_HIGH DTS Compare High Temperature Event Status Before Masking Event has not occurred Event has occurred TSE_LOW DTS Compare Low Temperature Event Status Before Masking Event has not occurred Event has occurred Reserved...
Page 281 IMC300A iMOTION Controller with additional microcontroller 14 System Control Unit (SCU) (continued) Field Bits Type Description VDROPI VDROP Interrupt Mask disable interrupt enable interrupt ORCxI (x=0,4,6,7) Out of Range Comparator X Interrupt Mask disable interrupt enable interrupt LOCI Loss of DCO1 Clock Interrupt Mask disable interrupt enable interrupt PESRAMI...
Page 282 IMC300A iMOTION Controller with additional microcontroller 14 System Control Unit (SCU) (continued) Field Bits Type Description TSE_DONE DTS Measurement Done Interrupt Mask disable interrupt enable interrupt TSE_HIGH DTS Compare High Temperature Interrupt Mask disable interrupt enable interrupt TSE_LOW DTS Compare Low Temperature Interrupt Mask disable interrupt enable interrupt 2:1, 20,...
Page 283 IMC300A iMOTION Controller with additional microcontroller 14 System Control Unit (SCU) (continued) Field Bits Type Description ACMP0I Analog Comparator 0 Interrupt Clear no effect clear status bit in the raw status register ACMP1I Analog Comparator 1 Interrupt Clear no effect clear status bit in the raw status register ACMP2I Analog Comparator 2 Interrupt Clear...
Page 284 IMC300A iMOTION Controller with additional microcontroller 14 System Control Unit (SCU) (continued) Field Bits Type Description RTC_ATIM0 RTC ATIM0 Mirror Register Update Clear no effect clear status bit in the raw status register RTC_ATIM1 RTC ATIM1 Mirror Register Update Clear no effect clear status bit in the raw status register RTC_TIM0...
Page 285 IMC300A iMOTION Controller with additional microcontroller 14 System Control Unit (SCU) Field Bits Type Description PRWARN WDT pre-warning Interrupt Set no effect set status bit in the raw status register RTC Periodic Interrupt Set no effect set status bit in the raw status register RTC Alarm Interrupt Set no effect set status bit in the raw status register...
Page 286 IMC300A iMOTION Controller with additional microcontroller 14 System Control Unit (SCU) (continued) Field Bits Type Description FLCMPLTI Flash Operation Complete Interrupt Set no effect set status bit in the raw status register VCLIPI VCLIP Interrupt Set no effect set status bit in the raw status register SBYCLKFI Standby Clock Failure Interrupt Set no effect...
Page 287 IMC300A iMOTION Controller with additional microcontroller 14 System Control Unit (SCU) LOEC 1OFS Field Bits Type Description ACMP3I Analog Comparator 3 Event Status Before Masking Event has not occurred Event has occurred LOECI Loss of External OSC_HP Clock Event Status Before Masking Event has not occurred Event has occurred PEU1I...
Page 288 IMC300A iMOTION Controller with additional microcontroller 14 System Control Unit (SCU) Field Bits Type Description ACMP3I Analog Comparator 3 Interrupt Mask disable interrupt enable interrupt LOECI Loss of External OSC_HP Clock Interrupt Mask disable interrupt enable interrupt PEU1I USIC1 SRAM Parity Error Interrupt Mask disable interrupt enable interrupt PEMCI...
Page 289 IMC300A iMOTION Controller with additional microcontroller 14 System Control Unit (SCU) (continued) Field Bits Type Description PEU1I USIC1 SRAM Parity Error Interrupt Clear no effect clear status bit in the raw status register PEMCI MultiCAN SRAM Parity Error Interrupt Clear no effect clear status bit in the raw status register DCO1OFSI...
Page 290 IMC300A iMOTION Controller with additional microcontroller 14 System Control Unit (SCU) (continued) Field Bits Type Description DCO1OFSI DCO1 Out of SYNC Interrupt Set no effect set status bit in the raw status register 31:5 Reserved 14.9.6.14 Register PASSWD The PASSWD register is used to control the bit protection scheme. PASSWD Address: 0024...
Page 291 IMC300A iMOTION Controller with additional microcontroller 14 System Control Unit (SCU) 14.9.6.15 Register MIRRSTS Mirror status register for control of communication between SCU and RTC. MIRRSTS Address: 0048 Mirror Update Status Register Reset Value: 0000 0000 RTC_ RTC_ RTC_ RTC_ RTC_ ATIM ATIM...
Page 292 IMC300A iMOTION Controller with additional microcontroller 14 System Control Unit (SCU) Field Bits Type Description MTENS Parity Test Enable Control for 16kbytes SRAM Controls the test multiplexer for the 16kbytes SRAM. standard operation generate an inverted parity bit during a write operation 31:1 Reserved Should be written with 0.
Page 293 IMC300A iMOTION Controller with additional microcontroller 14 System Control Unit (SCU) INTSEL15 INTSEL14 INTSEL13 INTSEL12 INTSEL11 INTSEL10 INTSEL9 INTSEL8 INTSEL7 INTSEL6 INTSEL5 INTSEL4 INTSEL3 INTSEL2 INTSEL1 INTSEL0 Field Bits Type Description INTSELx (x=0-15) 2*x+1:2*x rw Interrupt Source Select for Node x Select source A Select source B Select source C...
Page 294 IMC300A iMOTION Controller with additional microcontroller 14 System Control Unit (SCU) HWCON Field Bits Type Description HWCON HW Configuration At master reset, the following values are latched HWCON.0 = P4.6 HWCON.1 = P4.7 User productive mode (UPM) ASC BSL Alternate Boot Mode (ABM) CAN BSL Note: These values are not used when the BMI is used to...
Page 295 IMC300A iMOTION Controller with additional microcontroller 15 Window Watchdog Timer (WDT) Window Watchdog Timer (WDT) Purpose of the Window Watchdog Timer module is improvement of system integrity. WDT triggers the system reset or other corrective action like e.g. an interrupt if the main program, due to some fault condition, neglects to regularly service the watchdog (also referred to as “kicking the dog”, “petting the dog”, “feeding the watchdog”...
Page 296 IMC300A iMOTION Controller with additional microcontroller 15 Window Watchdog Timer (WDT) 15.1.2 Block Diagram The WDT block diagram is shown in Figure Bus Interface PORTS wdt_service external watchdog WDT Registers SCU.GCU HALTED wdt_alarm SCU.RCU wdt_rst_req Timer SCU.CCU Figure 42 Watchdog Timer Block Diagram 15.2 Time-Out Mode An overflow results in an immediate reset request going to the RCU of the SCU via the signal wdt_rst_req...
Page 297 IMC300A iMOTION Controller with additional microcontroller 15 Window Watchdog Timer (WDT) First serviced serviced overflow Window Upper Bound Window Lower Bound Servicing servicing allowed allowed wdt_service wdt_alarm wdt_rst_req Figure 43 Reset without pre-warning The example scenario depicted in Figure 43 shows two consecutive service pulses generated from WDT module as the result of successful servicing within valid time windows.
Page 298 IMC300A iMOTION Controller with additional microcontroller 15 Window Watchdog Timer (WDT) First Second serviced overflow overflow Window Upper Bound Window Lower Bound Servicing servicing allowed allowed wdt_service wdt_alarm wdt_rst_req Figure 44 Reset after pre-warning The example scenario depicted in Figure 44 shows service pulse generated from WDT module as the result of successful servicing within valid time window.
Page 299 IMC300A iMOTION Controller with additional microcontroller 15 Window Watchdog Timer (WDT) serviced in wrong serviced window Window Upper Bound Window Lower Bound Servicing servicing allowed allowed wdt_service wdt_alarm wdt_rst_req Figure 45 Reset upon servicing in a wrong window The example in Figure 45 shows servicing performed outside of valid servicing window.
Page 300 IMC300A iMOTION Controller with additional microcontroller 15 Window Watchdog Timer (WDT) serviced with invalid magic serviced word Window Upper Bound Window Lower Bound Servicing servicing allowed allowed wdt_service wdt_alarm wdt_rst_req Figure 46 Reset upon servicing with a wrong magic word The example in Figure 46 shows servicing performed within a valid servicing window but with an invalid Magic...
Page 301 IMC300A iMOTION Controller with additional microcontroller 15 Window Watchdog Timer (WDT) The input clock of the WDT counter is provided by the internal 32kHz standby clock from SCU/CCU module, independently from the AHB interface clock. The WDT module clock is default disabled and can be enabled via the SCU_CGATCLR0 register. Enabling and disabling the module clock could cause load change and clock blanking could happen as explained in the CCU (Clock Gating Control) section of the SCU chapter.
Page 302 IMC300A iMOTION Controller with additional microcontroller 15 Window Watchdog Timer (WDT) 15.8.3 Enter Sleep/Deep-Sleep & Resume Operation The WDT counter clock can be configured to stop while in sleep or deep-sleep mode. No direct software interaction with the WDT is required in those modes and no watchdog time-out will fire if the WDT clock is configured to stop while CPU is sleeping.
Page 303 IMC300A iMOTION Controller with additional microcontroller 15 Window Watchdog Timer (WDT) Table 177 Register Overview (continued) Short Name Description Offset Access Mode Description See Addr. Read Write Window Lower Bound U, PV Page Window Upper Bound U, PV Page WDTSTS Watchdog Status Register U, PV Page...
Page 304 IMC300A iMOTION Controller with additional microcontroller 15 Window Watchdog Timer (WDT) Field Bits Type Description Enable disables watchdog timer, enables watchdog timer Pre-warning disables pre-warning enables pre-warning, Debug Suspend watchdog timer is stopped during debug halting mode watchdog timer is not stopped during debug halting mode 15:8 Service Indication Pulse Width Pulse width (SPW+1) of service indication...
Page 305 IMC300A iMOTION Controller with additional microcontroller 15 Window Watchdog Timer (WDT) Field Bits Type Description 31:0 Service Writing the magic word ABADCAFE while the timer value is within the window boundary will service the watchdog. 15.9.4 Register TIM The actual watchdog timer register count value. This register can be read by software in order to determine current position in the WDT time window.
Page 306 IMC300A iMOTION Controller with additional microcontroller 15 Window Watchdog Timer (WDT) 15.9.6 Register WUB The Window Upper Bound register defines the upper bound for servicing window. Servicing of the watchdog has only effect within the window boundary. Address: WDT Window Upper Bound Register Reset Value: FFFF FFFF Field...
Page 307 IMC300A iMOTION Controller with additional microcontroller 15 Window Watchdog Timer (WDT) 15.9.8 Register WDTCLR The status register contains sticky bitfield indicating occurrence of alarm condition. WDTCLR Address: 001C WDT Clear Register Reset Value: 00000000 Field Bits Type Description ALMC Pre-warning Alarm clears pre-warning alarm no-action 31:1...
Page 308 IMC300A iMOTION Controller with additional microcontroller 16 Real Time Clock (RTC) Real Time Clock (RTC) Real-time clock (RTC) is a clock that keeps track of the current time. RTCs are present in almost any electronic device which needs to keep accurate time in a digital format for clock displays and computer systems. 16.1 Overview The RTC module tracks time with separate registers for hours, minutes, and seconds.
Page 309 IMC300A iMOTION Controller with additional microcontroller 16 Real Time Clock (RTC) Time Counter alarm periodic_event Serial Prescaler Interface Registers 32.768 kHz clock Figure 47 Real Time Clock Block Diagram Structure 16.2 RTC Operation The RTC timer counts seconds, minutes, hours, days, days of week, months and years the time in separate fields (see Figure 48).
Page 310 IMC300A iMOTION Controller with additional microcontroller 16 Real Time Clock (RTC) 16.4 Service Request Processing The RTC generates service requests upon: • periodic timer events • configured alarm condition The service requests can be processed in the core domain as regular service requests or as wake-up triggers from sleep or deep sleep mode.
Page 311 IMC300A iMOTION Controller with additional microcontroller 16 Real Time Clock (RTC) ACMPx CGATSTAT 0.RTC IOUT 0 ERU0 rtc_clock 32.768kHz Standby Clock DCO2 (default) CLKCR .RTCCLKSEL Figure 49 RTC Clock selection The RTC module clock is default disabled and can be enabled via the SCU_CGATCLR0 register. Note: Before changing RTC clock source via CLKCR.RTCCLKSEL, the RTC clock must be gated using bit CGATSET0.RTC.
Page 312 IMC300A iMOTION Controller with additional microcontroller 16 Real Time Clock (RTC) 16.7.2 Configure and Enable Periodic Event The RTC periodic event configuration require programming in order to enable interrupt request generation out upon a change of value in the corresponding bit fields. •...
Page 313 IMC300A iMOTION Controller with additional microcontroller 16 Real Time Clock (RTC) Table 181 Register Overview (continued) Short Name Description Offset Access Mode Description See Addr. Read Write ATIM0 Alarm Time Register 0 0018 U, PV Page ATIM1 Alarm Time Register 1 001C U, PV Page...
Page 314 IMC300A iMOTION Controller with additional microcontroller 16 Real Time Clock (RTC) Field Bits Type Description RTC Module Enable disables RTC module enables RTC module Debug Suspend Control RTC is not stopped during halting mode debug RTC is stopped during halting mode debug 31:16 Divider Value reload value of RTC prescaler.
Page 315 IMC300A iMOTION Controller with additional microcontroller 16 Real Time Clock (RTC) (continued) Field Bits Type Description RPHO Raw Periodic Hours Service Request Set whenever hours count increments RPDA Raw Periodic Days Service Request Set whenever days count increments RPMO Raw Periodic Months Service Request Set whenever months count increments RPYE Raw Periodic Years Service Request...
Page 316 IMC300A iMOTION Controller with additional microcontroller 16 Real Time Clock (RTC) 16.8.5 Register MSKSR RTC Service Request Mask Register contains masking value for generation control of service requests or iterrupts. MSKSR Address: RTC Service Request Mask Register Reset Value: 0000 0000 Field Bits Type...
Page 317 IMC300A iMOTION Controller with additional microcontroller 16 Real Time Clock (RTC) CLRSR Address: RTC Clear Service Request Register Reset Value: 0000 0000 RPYE RPMI RPSE Field Bits Type Description RPSE Raw Periodic Seconds Interrupt Clear no effect clear status bit RPMI Raw Periodic Minutes Interrupt Clear no effect...
Page 318 IMC300A iMOTION Controller with additional microcontroller 16 Real Time Clock (RTC) Field Bits Type Description Alarm Seconds Compare Value Match of seconds timer count to this value triggers alarm seconds interrupt. Setting value equal or above 3C results in setting the field value to 0 13:8 Alarm Minutes Compare Value...
Page 319 IMC300A iMOTION Controller with additional microcontroller 16 Real Time Clock (RTC) Field Bits Type Description 11:8 Alarm Month Compare Value Match of months timer count to this value triggers alarm month interrupt. Setting value equal or above the number of days of the actual month count results in setting the field value to 0 31:16 Alarm Year Compare Value...
Page 320 IMC300A iMOTION Controller with additional microcontroller 16 Real Time Clock (RTC) (continued) Field Bits Type Description 13:8 Minutes Time Value Setting value equal or above 3C results in setting the field value to 0 Value can only be written, when RTC is disabled via bit CTR.ENB. 20:16 Hours Time Value Setting value equal or above 18...
Page 321 IMC300A iMOTION Controller with additional microcontroller 16 Real Time Clock (RTC) (continued) Field Bits Type Description 11:8 Month Time Value Setting value equal or above C results in setting the field value to Value can only be written, when RTC is disabled via bit CTR.ENB. Months counter starts with value 0 for the first month of year.
Page 322 IMC300A iMOTION Controller with additional microcontroller 17 Pseudo Random Number Generator (PRNG) Pseudo Random Number Generator (PRNG) 17.1 Overview The pseudo random bit generator (PRNG) provides random data with fast generation times. 17.1.1 Features The PRNG includes the following features: •...
Page 323 IMC300A iMOTION Controller with additional microcontroller 17 Pseudo Random Number Generator (PRNG) The width of the output data block is changed by setting the value of PRNG_CTRL.RDBS. This should be done before entering streaming mode, otherwise if the change is made during streaming, the new setting will not come into effect until the next generation cycle is started.
Page 324 IMC300A iMOTION Controller with additional microcontroller 17 Pseudo Random Number Generator (PRNG) Refer to Chapter 17.2.1 for the initialization steps. 17.7 Registers The interface of the PRNG comprises the registers PRNG_WORD, PRNG_CHK and PRNG_CTRL. Table 183 Registers Address Space Module Base Address End Address Note...
Page 325 IMC300A iMOTION Controller with additional microcontroller 17 Pseudo Random Number Generator (PRNG) Reading PRNG_WORD while the PRNG is running in key loading mode (configured by setting PRNG_CTRL.KLD) will return the last value written to the register, whereas write accesses to the register while the PRNG is running in streaming mode (PRNG_CTRL.KLD = ’0’) will be ignored.
Page 326 IMC300A iMOTION Controller with additional microcontroller 17 Pseudo Random Number Generator (PRNG) Field Bits Type Description Key Load Operation Mode STRM, Streaming mode (default) KLD, Key loading mode RDBS Random Data Block Size Set random data block size for read access (16 bits always used for key loading) RES, Reset state (no random data block size defined) value of...
Page 327 IMC300A iMOTION Controller with additional microcontroller 18 Universal Serial Interface Channel (USIC) Universal Serial Interface Channel (USIC) The Universal Serial Interface Channel module (USIC) is a flexible interface module covering several serial communication protocols. A USIC module contains two independent communication channels named USICx_CH0 and USICx_CH1, with x being the number of the USIC module (e.g.
Page 328 IMC300A iMOTION Controller with additional microcontroller 18 Universal Serial Interface Channel (USIC) Parity bit generation supported MSB or LSB first • IIC (Inter-IC Bus) Application baud rate 100 kbit/s to 400 kbit/s 7-bit and 10-bit addressing supported Full master and slave device capability Note: The real baud rates that can be achieved in a real application depend on the operating frequency of the device, timing parameters as described in the Data Sheet, signal delays on the PCB and timings of...
Page 329 IMC300A iMOTION Controller with additional microcontroller 18 Universal Serial Interface Channel (USIC) Each USIC channel offers the choice between several possible input and output pins connections for the communications signals. This allows a flexible assignment of USIC signals to pins that can be changed without resetting the device.
Page 330 IMC300A iMOTION Controller with additional microcontroller 18 Universal Serial Interface Channel (USIC) To Interrupt Interrupt Generation Registers Pins USICx Baud Rate Generator PERIPH Input Data Stages Data Shift Buffer (ASC, Unit SSC. ..) Channel 0 USICx Baud Rate Generator PERIPH Input Data Stages...
Page 331 IMC300A iMOTION Controller with additional microcontroller 18 Universal Serial Interface Channel (USIC) The inputs marked as “optional” are not needed for the standard function of a protocol and may be used for enhancements. The descriptions of protocol-specific items are given in the related protocol chapters. For the external frequency input, please refer to the baud rate generator section, and for the transmit data validation, to the data handling section.
Page 332 IMC300A iMOTION Controller with additional microcontroller 18 Universal Serial Interface Channel (USIC) 18.2.1.3 Output Signals For each protocol, up to 14 protocol-related output signals are available. The number of actually used outputs depends on the selected protocol. They can be classified according to their meaning for the protocols, see Table 187.
Page 333 IMC300A iMOTION Controller with additional microcontroller 18 Universal Serial Interface Channel (USIC) The available USIC signals and their port locations are listed in the interconnects section, see Interconnects on page 504. 18.2.1.4 Baud Rate Generator Each USIC Channel contains a baud rate generator structured as shown in Figure 51.
Page 334 IMC300A iMOTION Controller with additional microcontroller 18 Universal Serial Interface Channel (USIC) the shift data (handled by input stage DX0, DX3, DX4 and DX5), the shift clock (handled by the input stage DX1), and the shift control (handled by the input stage DX2). The signal DOUT[3:0] represents the shift data outputs. Optional Transmit Shift Data Input (s) Basic Data Buffer...
Page 335 IMC300A iMOTION Controller with additional microcontroller 18 Universal Serial Interface Channel (USIC) Control Info TCI RBUF01SR RBUF01SR TBUF RBUF0 RBUF1 Location Data TBUF31 TBUF01 RBUFSR TBUF00 RBUF RBUFD Mirror Data Write Access Data Read Access Debug Read Access Figure 53 Data Access Structure without additional Data Buffer It is recommended to read the received data words by accesses to RBUF and to avoid handling of RBUF0 and RBUF1.
Page 336 IMC300A iMOTION Controller with additional microcontroller 18 Universal Serial Interface Channel (USIC) The transmission control of the FIFO buffer can also use the transfer trigger and transfer gating scheme of the transmission logic for data validation (e.g. to trigger data transfers by events). Control Info TCI RBUF01SR RBUF01SR...
Page 337 IMC300A iMOTION Controller with additional microcontroller 18 Universal Serial Interface Channel (USIC) Use of PCR Bits The signification of the bits in register PCR is indicated by the protocol-related alias names for the different protocols. • PCR for the ASC protocol (see page 450) •...
Page 338 IMC300A iMOTION Controller with additional microcontroller 18 Universal Serial Interface Channel (USIC) Note: The stop mode selection strongly depends on the application needs and it is very unlikely that different stop modes are required in parallel in the same application. As a result, only one stop mode type (either 0 or 1) should be used in the bit fields in register KSCFG.
Page 339 IMC300A iMOTION Controller with additional microcontroller 18 Universal Serial Interface Channel (USIC) DXnCR DXnCR DXnCR DXnCR DSEL DPOL DSEN INSW DXnA DXnB Data Shift Unit DXnG DXnS Protocol Pre-Processor DXnINS Digital Edge Filter Detection DXnT DFEN DXnCR DXnCR Figure 56 Input Conditioning for DX[2:1] 18.2.3.2 Input Selection...
Page 340 IMC300A iMOTION Controller with additional microcontroller 18 Universal Serial Interface Channel (USIC) In order to adapt the filter sampling period to different applications, it can be programmed. The first possibility is the system frequency f . Longer pulses can be suppressed if the fractional divider output frequency f PERIPH selected.
Page 341 IMC300A iMOTION Controller with additional microcontroller 18 Universal Serial Interface Channel (USIC) DX1CR DX1CR DX1CR DSEN INSW DCEN Receive shift Similar to clock (DSU) structure of Transmit shift clock (DSU) Signal from Protocol Pre-processor Figure 57 Delay Compensation Enable in DX1 18.2.4 Operating the Baud Rate Generator The following blocks can be configured to operate the baud rate generator, see also...
Page 342 IMC300A iMOTION Controller with additional microcontroller 18 Universal Serial Interface Channel (USIC) × with n = STEP PERIPH 1024 Equation 10 The output frequency f of the fractional divider is selected for baud rate generation by BRG.CLKSEL = 00 18.2.4.2 External Frequency Input The baud rate can be generated referring to an external frequency input (instead of to f ) if the input stage...
Page 343 IMC300A iMOTION Controller with additional microcontroller 18 Universal Serial Interface Channel (USIC) × if PPPEN = 0 PDIV PDIV + 1 × if PPPEN = 1 PDIV MCLK PDIV + 1 Equation 13 CTQIN Divide by Divide Divide SCLK PDIV + 1 by 2 by 2 PDIV...
Page 344 IMC300A iMOTION Controller with additional microcontroller 18 Universal Serial Interface Channel (USIC) 18.2.4.5 Time Quanta Counter The time quanta counter CTQ associated to the protocol pre-processor allows to generate time intervals for protocol-specific purposes. The length of a time quantum t is given by the selected input frequency f CTQIN the programmed pre-divider value.
Page 345 IMC300A iMOTION Controller with additional microcontroller 18 Universal Serial Interface Channel (USIC) The mechanism for the polarity control of the SCLKOUT signal is similar to the one for MCLKOUT, but based on bit field BRG.SCLKCFG. The generation of the SCLKOUT signal is enabled/disabled by the protocol pre- processor.
Page 346 IMC300A iMOTION Controller with additional microcontroller 18 Universal Serial Interface Channel (USIC) 18.2.5.2 Transmit Data Shift Mode The transmit shift data can be selected to be shifted out one, two or four bits at a time through the corresponding number of output lines. This option allows the USIC to support protocols such as the Dual- and Quad-SSC.
Page 347 IMC300A iMOTION Controller with additional microcontroller 18 Universal Serial Interface Channel (USIC) Table 190 TCI Modes TCI Mode Effects Usage Word length Bit field SCTR.WLE is updated with TCI[3:0] if Can be used in all protocols to dynamically control a transmit buffer input location TBUFx is change the data word length between 1 and written 16 data bits per data word...
Page 348 IMC300A iMOTION Controller with additional microcontroller 18 Universal Serial Interface Channel (USIC) Data Shift Unit TCSR TDVTR TCSR DX2T Transfer Trigger TBUF Shift Control Data Input DX2 Validation Transfer Gating DX2S TDEN TDSSM TCSR TCSR Figure 63 Transmit Data Validation Transfer Gating A transfer gating logic enables or disables the data word transfer from TBUF under software or under hardware control.
Page 349 IMC300A iMOTION Controller with additional microcontroller 18 Universal Serial Interface Channel (USIC) • Bit TCSR.TDSSM = 1 has to be programmed to allow word-by-word data transmission with a kind of single- shot mechanism. After each transmission start, a new data word has to be loaded into the transmit buffer TBUF, either by software write actions to one of the transmit buffer input locations TBUFx or by an optional data buffer (e.g.
Page 350 IMC300A iMOTION Controller with additional microcontroller 18 Universal Serial Interface Channel (USIC) Shift Clock Domain RSR13 Shift Data Input 3 RSR03 RSR12 Shift Data Input 2 RSR02 RSR11 Shift Data Input 1 RSR01 RSR10 Shift Data Input 0 RSR00 Shift Control Shift Clock Input &...
Page 351 IMC300A iMOTION Controller with additional microcontroller 18 Universal Serial Interface Channel (USIC) Table 191 Receive Shift Register Composition (continued) Receive Shift Input stage Single Data Input Two Data Inputs Four Data Inputs Registers used (SCTR.DSM = 00 (SCTR.DSM = 10 (SCTR.DSM = 11 RSRx1 Not used...
Page 352 IMC300A iMOTION Controller with additional microcontroller 18 Universal Serial Interface Channel (USIC) Buffered Receive Data Receive Data Shift Data Receive OUTR RBUF Input(s) FIFO Data Shift Unit Buffered Transmit Transmit Data Transmit Data (DSU) Shift Data FIFO TBUF Output(s) Bypass USICx_C0 User Inter-...
Page 353 IMC300A iMOTION Controller with additional microcontroller 18 Universal Serial Interface Channel (USIC) Each FIFO buffer consists of a set of consecutive FIFO entries. The size of a FIFO data buffer can only be programmed as a power of 2, starting with 2 entries, then 4 entries, then 8 entries, etc. A FIFO data buffer can only start at a FIFO entry aligned to its size.
Page 354 IMC300A iMOTION Controller with additional microcontroller 18 Universal Serial Interface Channel (USIC) Similar to the case where STBTEN = 0, with the difference that the flag TRBSR.STBT is also set in addition to STBI. While STBT = 1, a standard transmit buffer event will be additionally triggered each time there is either a transfer data to TBUF event (for the case where LOF = 0) or write data to INx event (for the case where LOF = 1).
Page 355 IMC300A iMOTION Controller with additional microcontroller 18 Universal Serial Interface Channel (USIC) An interrupt is generated The interrupt is serviced due to the transition of and it is used to fill up the TBFLVL from 3 to 2. STBI FIFO with the next 2 data is set.
Page 356 IMC300A iMOTION Controller with additional microcontroller 18 Universal Serial Interface Channel (USIC) Standard Transmit Buffer Event The standard transmit buffer event is triggered by either: • The filling level of the transmit buffer (given by TRBSR.TBFLVL) exceeding (TBCTR.LOF = 1) or falling below (TBCTR.LOF = 0) a programmed limit (TBCTR.LIMIT).
Page 357 IMC300A iMOTION Controller with additional microcontroller 18 Universal Serial Interface Channel (USIC) Table 192 Transmit Buffer Events and Interrupt Handling Event Indication Flag Indication Interrupt SRx Output cleared by enabled by selected by Standard transmit buffer event TRBSR.STBI TRBSCR.CSTBI TBCTR.STBIEN TBCTR.STBINP TRBSR.STBT Cleared by...
Page 358 IMC300A iMOTION Controller with additional microcontroller 18 Universal Serial Interface Channel (USIC) Start of data transmission Write 1 16 data words to INx TRBSR. STBI=1? Clear STBI through TRBSCR.CSTBI Last data word is written? Write next 8 data words to INx End of transmission Figure 69...
Page 359 IMC300A iMOTION Controller with additional microcontroller 18 Universal Serial Interface Channel (USIC) Filling Level Sub-Mode with SRBTEN = 0 When RBCTR.SRBTEN = 0, a standard receive buffer event is triggered only under the condition of the filling level of the receive buffer (given by TRBSR.RBFLVL) transiting away from a programmed limit (RBCTR.LIMIT). •...
Page 360 IMC300A iMOTION Controller with additional microcontroller 18 Universal Serial Interface Channel (USIC) An interrupt is generated Interrupt is serviced and 2 data read outs from OUTR due to the transition of take place. RBFLVL from 1 to 2. SRBI is set. Example 1: RBCTR settings: SIZE = 8...
Page 361 IMC300A iMOTION Controller with additional microcontroller 18 Universal Serial Interface Channel (USIC) 18.2.8.6 Receive Buffer Events and Interrupts The receive FIFO buffer mechanism detects the following events, that can lead to an interrupt (if enabled): • Standard receive buffer event •...
Page 362 IMC300A iMOTION Controller with additional microcontroller 18 Universal Serial Interface Channel (USIC) RBCTR TRBSCR TRBSR RBCTR RBCTR Clear CSRBI SRBI STBIEN SRBINP ≥1 & Data Read Out RBCTR Event Standard Standard & New Data SRBTEN Receive Receive Received Event Buffer Buffer Interrupt TRBSR Event...
Page 363 IMC300A iMOTION Controller with additional microcontroller 18 Universal Serial Interface Channel (USIC) OUTR TRBSCR TRBSR RBCTR RBCTR Clear RCI[4] CSRBI SRBI SRBIEN SRBINP Standard Receive Standard Receive Buffer Event Buffer Interrupt New Data in OUTR Event Alternate Receive Alternate Receive Buffer Event Buffer Interrupt Clear...
Page 364 IMC300A iMOTION Controller with additional microcontroller 18 Universal Serial Interface Channel (USIC) RXFIFO Initialization The following code initializes the receive FIFO buffer in the given example: /// --------------------------------------------------------------------- /// Configure RXFIFO - RXFIFO starts from FIFO buffer entry 32 - RXFIFO size of 16 data words - Standard receive buffer event is triggered when fill level exceeds 7, i.e.
Page 365 IMC300A iMOTION Controller with additional microcontroller 18 Universal Serial Interface Channel (USIC) Start of data reception TRBSR. SRBI=1? Clear SRBI through TRBSCR.CSRBI Read out 8 data words from OUTR All data words are received? End of reception Figure 73 Simplified Data Reception Flow in Receive Buffer Filling Level Mode 18.2.8.8 FIFO Buffer Bypass The data bypass mechanism is part of the transmit FIFO control block.
Page 366 IMC300A iMOTION Controller with additional microcontroller 18 Universal Serial Interface Channel (USIC) • If the bypass data is valid for transmission and has either a higher transmit priority than the FIFO data or if the transmit FIFO is empty, the bypass data is transferred to TBUF. •...
Page 367 IMC300A iMOTION Controller with additional microcontroller 18 Universal Serial Interface Channel (USIC) In order to avoid data loss and stalling of the CPU due to delayed software accesses, the baud rate, the word length and the software access mechanism have to be taken into account. Each access to the FIFO data buffer area by software or by hardware takes one period of f .
Page 368 IMC300A iMOTION Controller with additional microcontroller 18 Universal Serial Interface Channel (USIC) FIFO / Bypass USIC Channel BDATA TBUF Transmit SELMD FIFO CTR[20:16] BSEL0 CTR[23:21] Bypass Control WLEMD WLE, EOF BWLE FLEMD FLE[4:0] FLE[4:0] FLE[5] FLE[5] HPCMD TCI[2:0] BHPC HPCDIR WAMD TCI[4] Figure 75...
Page 369 IMC300A iMOTION Controller with additional microcontroller 18 Universal Serial Interface Channel (USIC) ASC Module A ASC Module B DIN0 DIN0 RBUF RBUF DOUT0 DOUT0 TBUF TBUF Transfer Transfer Control Control Baud Rate Baud Rate PERIPH PERIPH Generator Generator (ASC A) (ASC B) Figure 76 ASC Signal Connections for Full-Duplex Communication...
Page 370 IMC300A iMOTION Controller with additional microcontroller 18 Universal Serial Interface Channel (USIC) • An idle time with the signal level 1. • One start of frame bit (SOF) with the signal level 0. • A data field containing a programmable number of data bits (1-63). •...
Page 371 IMC300A iMOTION Controller with additional microcontroller 18 Universal Serial Interface Channel (USIC) 18.3.2.3 Data Field The length of the data field (number of data bits) can be programmed by bit field SCTR.FLE. It can vary between 1 and 63 data bits, corresponding to values of SCTR.FLE = 0 to 62 (the value of 63 is reserved and must not be programmed in ASC mode).
Page 372 IMC300A iMOTION Controller with additional microcontroller 18 Universal Serial Interface Channel (USIC) • Configure data format The word length, the frame length, and the shift direction have to be set up according to the application requirements by programming the register SCTR. Write SCTR.TRM = 01 to enable ASC data transfers.
Page 373 IMC300A iMOTION Controller with additional microcontroller 18 Universal Serial Interface Channel (USIC) 1 Bit Time PCR.SP = 15 PCR.SP = 8 Time Quanta = sample taken if SMD = 0 = sample taken if SMD = 1 Figure 79 ASC Bit Timing The bit timing setup (number of time quanta and the sampling point definition) is common for the transmitter and the receiver.
Page 374 IMC300A iMOTION Controller with additional microcontroller 18 Universal Serial Interface Channel (USIC) STEP × × × × PERIPH 1024 PDIV + 1 PCTQ + 1 DCTQ + 1 Equation 16 Fractional divider mode (FDR.DM = 10 Table 195 shows examples of the baud rate calculation in fractional divider mode (FDR.DM = 10 Table 195 ASC Baud Rate Calculation in Fractional Divider Mode (MHz)
Page 375 IMC300A iMOTION Controller with additional microcontroller 18 Universal Serial Interface Channel (USIC) 18.3.3.5 Disabling ASC Mode In order to switch off ASC mode without any data corruption, the receiver and the transmitter have to be both idle. This is ensured by requesting Stop Mode 1 in register KSCFG. After waiting for the end of the frame, the ASC mode can be disabled.
Page 376 IMC300A iMOTION Controller with additional microcontroller 18 Universal Serial Interface Channel (USIC) Table 197 ASC protocol interrupt events (continued) Events Event flag Description Flag clear Interrupt enable Collision PSR.COL Transmitted value (DOUT0) does not match with the PSCR.CST3 PCR.CDEN detection input value of the DX1 input stage at the sample point of a bit.
Page 377 IMC300A iMOTION Controller with additional microcontroller 18 Universal Serial Interface Channel (USIC) The standard receive buffer event and the alternative receive buffer event can be used for the following operations in RCI mode (RBCTR.RNM = 1): • A standard receive buffer event (TRBSR.SRBI = 1) indicates that a data word can be read from OUTR that has been received without parity error.
Page 378 IMC300A iMOTION Controller with additional microcontroller 18 Universal Serial Interface Channel (USIC) Initiating data transmission Write transmit data word to TBUFx TBIF=1? Clear TBIF Last data word is transmitted? End of transmission Figure 80 Simplified Data Transmission Flow Data Reception Data reception is initiated with the detection of a valid start bit on the receive input line.The receiver continues to sample the incoming data frame and shifts it into the available receive shift register.
Page 379 IMC300A iMOTION Controller with additional microcontroller 18 Universal Serial Interface Channel (USIC) Start of data reception RIF or AIF=1? Clear RIF and AIF Read RBUF All data words are received? End of reception Figure 81 Simplified Data Reception Flow Interrupt Events on Data Transfer Figure 82 shows the interrupt events during an ASC data transfer for both the transmitter and the receiver.
Page 380 IMC300A iMOTION Controller with additional microcontroller 18 Universal Serial Interface Channel (USIC) 18.3.3.12 Initialization Code Example The following code shows an example of an ASC initialization sequence: void USIC0_CH1_Init(void) /// -------------------------------------------------------------------- /// 1. Enable USIC0 channel 1 /// -------------------------------------------------------------------- BPMODEN MODEN USIC0_CH1->KSCFG |= (1 <<...
Page 381 IMC300A iMOTION Controller with additional microcontroller 18 Universal Serial Interface Channel (USIC) /// -------------------------------------------------------------------- STPB USIC0_CH1->PCR = (8 << 8)|(0 << 1)|(1 << 0); /// -------------------------------------------------------------------- /// 7. Enable ASC protocol and select parity mode - No parity is selected /// -------------------------------------------------------------------- MODE USIC0_CH1->CCR = (0 <<...
Page 382 IMC300A iMOTION Controller with additional microcontroller 18 Universal Serial Interface Channel (USIC) the number of time quanta defined by PCR.PL. In order to support correct reception with pulse shaping by the transmitter, the sample point has to be adjusted in the receiver according to the applied pulse length. 0-Pulse for PL = 001 0-Pulse for...
Page 383 IMC300A iMOTION Controller with additional microcontroller 18 Universal Serial Interface Channel (USIC) If a 0 level is detected at a sample point of a bit after this event has been found, bit PSR.SBD is set and additionally, a protocol interrupt can be generated (if enabled by PCR.SBIEN = 1). The counting restarts from 0 each time a falling edge is found at input DIN0.
Page 384 IMC300A iMOTION Controller with additional microcontroller 18 Universal Serial Interface Channel (USIC) programmed with the captured CMTR.CTV value divided by twice the number of time quanta per bit (assuming BRG.PCTQ = 00 • Other symbols: The other symbols of a LIN frame can be handled with ASC data frames without specific actions. If LIN frames should be sent out on a frame base by the LIN master, the input DX2 can be connected to external timers to trigger the transmit actions (e.g.
Page 385 IMC300A iMOTION Controller with additional microcontroller 18 Universal Serial Interface Channel (USIC) A device operating in master mode controls the start and end of a data frame, as well as the generation of the shift clock and slave select signals. This comprises the baud rate setting for the shift clock and the delays between the shift clock and the slave select output signals.
Page 386 IMC300A iMOTION Controller with additional microcontroller 18 Universal Serial Interface Channel (USIC) SSC in Slave Mode SSC in Master Mode SCLKIN SCLKOUT Delay of ½ SCLKCFG Bit Time Input Stage SCLK Transfer Baud Rate Data Shift Unit Control Logic Generator Figure 88 SSC Shift Clock Signals Master Mode...
Page 387 IMC300A iMOTION Controller with additional microcontroller 18 Universal Serial Interface Channel (USIC) Table 198 Shift Clock Configuration in Master Mode SCLKCFG Description No delay, no polarity inversion (SCLKOUT equals SCLK) • The inactive level of SCLKOUT is 0, while no data frame is transferred. •...
Page 388 IMC300A iMOTION Controller with additional microcontroller 18 Universal Serial Interface Channel (USIC) Slave Mode In slave mode, the shift clock signal is handled by the input stage DX1. The signal SCLKIN is received from an external master, so the DX1 stage has to be connected to an input pin. For complete closed loop delay compensation in slave mode, the transmit shift clock from the input stage DX1 can be additionally routed to the SCLKOUT signal, which is otherwise not used in the slave mode.
Page 389 IMC300A iMOTION Controller with additional microcontroller 18 Universal Serial Interface Channel (USIC) SSC in Slave Mode SSC in Master Mode ..SELIN SELOx x = 0-7 SELCFG Input Stage MSLS Transfer Slave Select Data Shift Unit Control Logic Generator Figure 91 SSC Slave Select Signals...
Page 390 IMC300A iMOTION Controller with additional microcontroller 18 Universal Serial Interface Channel (USIC) 18.4.2 Operating the SSC This chapter contains SSC issues, that are of general interest and not directly linked to either master mode or slave mode. 18.4.2.1 Automatic Shadow Mechanism The contents of the baud rate control register BRG, bit fields SCTR.FLE as well as the protocol control register PCR are internally kept constant while a data frame is transferred (= while MSLS is active) by an automatic shadow mechanism.
Page 391 IMC300A iMOTION Controller with additional microcontroller 18 Universal Serial Interface Channel (USIC) The data word length information (defined by SCTR.WLE) is evaluated for each new data word, whereas the frame length information (defined by SCTR.FLE) is evaluated at the beginning at each start of a new frame. The length of an SSC data frame can be defined in two different ways: •...
Page 392 IMC300A iMOTION Controller with additional microcontroller 18 Universal Serial Interface Channel (USIC) Data Frame with LSB First (SCTR.SDIR= 0) Parity Mode FLE-1 Disabled (FLE+1) Bits Parity Mode Parity Enabled FLE-1 (FLE+1) + Parity Time Data Frame with MSB First (SCTR.SDIR= 1) Parity Mode Disabled FLE-1...
Page 393 IMC300A iMOTION Controller with additional microcontroller 18 Universal Serial Interface Channel (USIC) Table 199 SSC Data transfer interrupt handling (continued) Interrupt Indicated Description by bit Transmit shift PSR.TSIF Set after the start of the last data bit of a data word. interrupt Receiver start PSR.RSIF...
Page 394 IMC300A iMOTION Controller with additional microcontroller 18 Universal Serial Interface Channel (USIC) • A standard receive buffer event indicates that a data word can be read from OUTR that has not been the first word of a data frame. • An alternative receive buffer event indicates that the first data word of a new data frame can be read from OUTR.
Page 395 IMC300A iMOTION Controller with additional microcontroller 18 Universal Serial Interface Channel (USIC) Note: The USIC can only receive in master mode if it is transmitting, because the master frame handling refers to bit TDV of the transmitter part. 18.4.3.1 Baud Rate Generation The baud rate (determining the length of one data bit) of the SSC is defined by the frequency of the SCLK signal (one period of f represents one data bit).
Page 396 IMC300A iMOTION Controller with additional microcontroller 18 Universal Serial Interface Channel (USIC) Data Frame Data Word 0 Data Word 1 Shift Clock Transmit D0 D1 Data Receive D0 D1 D0 D1 Data Active MSLS Inactive SELOx (SELINV = 1) Figure 93 MSLS Generation in SSC Master Mode In SSC master mode, the slave select delays are defined as follows: Leading delay T...
Page 397 IMC300A iMOTION Controller with additional microcontroller 18 Universal Serial Interface Channel (USIC) • BRG.CTQSEL to define the input frequency f for the time quanta generation for T and T CTQIN • BRG.PCTQ to define the length of a time quantum (division of f by 1, 2, 3, or 4) for T and T CTQIN...
Page 398 IMC300A iMOTION Controller with additional microcontroller 18 Universal Serial Interface Channel (USIC) Table 201 SSC master mode protocol interrupt events Events Event flag Description Flag clear Interrupt enable MSLS PSR.MSLSEV Set with any change of the internal MSLS PSCR.CST2 PCR.MSLSIEN interrupt signal in maser mode (MSLS generation enabled).
Page 399 IMC300A iMOTION Controller with additional microcontroller 18 Universal Serial Interface Channel (USIC) data word in TBUF is sent out completely and the slave select delays T and T are applied. A new data frame can start with T with the next valid TBUF value. For software-handling of bit EOF, bit TCSR.WLEMD = 0 has to be programmed.
Page 400 IMC300A iMOTION Controller with additional microcontroller 18 Universal Serial Interface Channel (USIC) When the number of bits corresponding to the data word length is received, the contents of the receive shift register are transferred to the corresponding receive buffer (RBUF0 or RBUF1). This is indicated by an alternate receive interrupt event (PSR.AIF) if the received word is the first word of the frame, or by a receive interrupt event (PSR.RIF) if the received word represents subsequent words of the frame.
Page 401 IMC300A iMOTION Controller with additional microcontroller 18 Universal Serial Interface Channel (USIC) SCLKOUT MTSR MRST Data Word x Data Word 0 Data Frame SELOx MSLSEV TBIF TSIF TBIF TSIF MSLSEV RSIF RSIF Figure 95 Interrupt Events on Data Transfer Reference Manual V1.0 2020-05-28...
Page 402 IMC300A iMOTION Controller with additional microcontroller 18 Universal Serial Interface Channel (USIC) 18.4.3.8 Initialization Code Example The following code example implements a function to initialize a USIC channel for SSC master mode data transfers with a baud rate of 1500 kbit/s (f = 48 MHz): PERIPH void USIC0_CH1_SSC_MasterMode_Init(void)
Page 403 IMC300A iMOTION Controller with additional microcontroller 18 Universal Serial Interface Channel (USIC) - SELO0 is selected as the active select signal /// -------------------------------------------------------------------- SELO SELINV SELCTR MSLSEN USIC0_CH1->PCR = (1 << 16)|(1 << 3)|(1 << 2)|(1 << 1)|(1 << 0); /// -------------------------------------------------------------------- /// 7.
Page 404 IMC300A iMOTION Controller with additional microcontroller 18 Universal Serial Interface Channel (USIC) • Configure data transfer parameters Write TCSR.TDSSM = 1 and TCSR.TDEN = 01 to enable data transmission in single shot mode. • Select SSC protocol Enable SSC mode with CCR.MODE = 0001 •...
Page 405 IMC300A iMOTION Controller with additional microcontroller 18 Universal Serial Interface Channel (USIC) Frame length not known by the slave, no slave select In this case, the slave device’s software has to decide on data word base if a frame is finished. Bit field SCTR.FLE can be either programmed to the word length SCTR.WLE, or to its maximum value to disable the slave internal frame length evaluation by counting received bits.
Page 406 IMC300A iMOTION Controller with additional microcontroller 18 Universal Serial Interface Channel (USIC) Start of data Start of data transmission reception Write transmit data word to RIF or AIF=1? TBUFx RSIF=1? Clear RIF and AIF Clear RSIF Read RBUF Last data word All data words is transmitted? are received?
Page 407 IMC300A iMOTION Controller with additional microcontroller 18 Universal Serial Interface Channel (USIC) SCLKIN MTSR MRST Data Word x Data Word 0 Data Frame SELIN TBIF TSIF TBIF TSIF RSIF RSIF Figure 97 Interrupt Events on Data Transfer Reference Manual V1.0 2020-05-28...
Page 408 IMC300A iMOTION Controller with additional microcontroller 18 Universal Serial Interface Channel (USIC) 18.4.4.4 Initialization Code Example The following code example implements a function to initialize a USIC channel for SSC slave mode data transfers: void USIC0_CH1_SSC_SlaveMode_Init(void) /// -------------------------------------------------------------------- /// 1. Enable USIC0 channel 1 /// -------------------------------------------------------------------- BPMODEN MODEN...
Page 409 IMC300A iMOTION Controller with additional microcontroller 18 Universal Serial Interface Channel (USIC) PORT0->IOCR4 |= (0x27 << 18); 18.4.5 Multi-IO SSC Protocols Multi-IO SSC protocols, or specifically Dual-SSC and Quad-SSC, are extensions of the standard SSC protocol to double and quadruple the effective data transfer rates. This is achieved by transmitting and receiving data through two or four IO lines in parallel, in a half-duplex configuration.
Page 410 IMC300A iMOTION Controller with additional microcontroller 18 Universal Serial Interface Channel (USIC) 18.4.5.1 Operating the SSC in Multi-IO Modes In order to operate the multi-IO SSC in either master or slave mode, the following steps have to be taken in addition to the USIC channel initialization steps outlined in Chapter 18.4.3 Chapter...
Page 411 IMC300A iMOTION Controller with additional microcontroller 18 Universal Serial Interface Channel (USIC) Initialization The following code modifications can be made to the initialization code examples in Chapter 18.4.3.8 Chapter 18.4.4.4 to configure the USIC channel as a Quad-SSC master or slave: /// ------------------------------------------------------------ /// 5.
Page 412 IMC300A iMOTION Controller with additional microcontroller 18 Universal Serial Interface Channel (USIC) SSC Master Device SSC Slave Device SSC Master SSC Slave Module Module MTSR prop TBUF RBUF MRST prop RBUF TBUF Frame Frame Control Control Shift Clock prop Slave Select T prop Figure 100 SSC Closed-loop Delay...
Page 413 IMC300A iMOTION Controller with additional microcontroller 18 Universal Serial Interface Channel (USIC) 1) Without any delay compensation SCLK at master (Output driver stage) MTSR at master Master Data (Output driver stage) out_master prop in_slave SCLK at slave (input driver stage) MRST at slave Slave Data (Output driver stage)
Page 414 IMC300A iMOTION Controller with additional microcontroller 18 Universal Serial Interface Channel (USIC) SSC Master Device SSC Slave Device SSC Master SSC Slave Module Module MTSR prop TBUF RBUF MRST prop RBUF TBUF Frame Frame Control Control Shift Clock prop Slave Select T prop Figure 102 SSC Master Mode with Delay Compensation...
Page 415 IMC300A iMOTION Controller with additional microcontroller 18 Universal Serial Interface Channel (USIC) SSC Master Device SSC Slave Device SSC Master SSC Slave Module Module MTSR prop TBUF RBUF MRST prop RBUF TBUF Shift Clock prop Frame Frame (for Master Control Control Receive) Shift Clock...
Page 416 IMC300A iMOTION Controller with additional microcontroller 18 Universal Serial Interface Channel (USIC) where several masters can be connected to the bus and bus arbitration can take place, i.e. the IIC module can be master or slave. The master/slave operation of an IIC bus participant can change from frame to frame.
Page 417 IMC300A iMOTION Controller with additional microcontroller 18 Universal Serial Interface Channel (USIC) Table 203 IIC Symbol Definition Symbol Definition Bus idle SDA and SCL are high. No data transfer takes place currently. Data bit SDA stable during the high phase of SCL. SDA then represents the transferred bit value.
Page 418 IMC300A iMOTION Controller with additional microcontroller 18 Universal Serial Interface Channel (USIC) 18.5.2 Symbol Timing The symbol timing of the IIC is determined by the master generating the shift clock line SCL. It is different in each of the modes. •...
Page 419 IMC300A iMOTION Controller with additional microcontroller 18 Universal Serial Interface Channel (USIC) 18.5.2.2 Repeated Start Symbol During the first part of a repeated start symbol, an SCL low value is driven for the specified number of time quanta. Then a high value is output. After the detection of a rising edge at the SCL input, a normal start symbol is generated, as shown in Figure 107.
Page 420 IMC300A iMOTION Controller with additional microcontroller 18 Universal Serial Interface Channel (USIC) Data Bit Symbol HDEL Standard ..Mode Fast ..15 16 Mode Figure 109 Data Bit Symbol Output SDA changes after the time t defined by PCR.HDEL has elapsed if a falling edge is detected at the...
Page 421 IMC300A iMOTION Controller with additional microcontroller 18 Universal Serial Interface Channel (USIC) Select the passive output level to be high (SCTR.PDL = 1) and for the data output to be without inversion (SCTR.DOCFG = 00 Write SCTR.TRM = 11 to enable IIC data transfers. •...
Page 422 IMC300A iMOTION Controller with additional microcontroller 18 Universal Serial Interface Channel (USIC) STEP × × × × PERIPH 1024 PDIV + 1 PCTQ + 1 DCTQ + 1 Equation 23 Fractional divider mode (FDR.DM = 10 Table 204 shows examples of the baud rate calculation in fractional divider mode (FDR.DM = 10 Table 204 IIC Baud Rate Calculation in Fractional Divider Mode (MHz)
Page 423 IMC300A iMOTION Controller with additional microcontroller 18 Universal Serial Interface Channel (USIC) 18.5.3.5 Not Acknowledge and Error Conditions In case of a not acknowledge or an error, the TCSR.TDV flag remains set, but no further transmission will take place. User software must invalidate the transmit buffer and disable transmissions (by writing FMRL.MTDV = 10 before configuring the transmission (by writing TBUF) again with appropriate values to react on the previous event.
Page 424 IMC300A iMOTION Controller with additional microcontroller 18 Universal Serial Interface Channel (USIC) 18.5.3.7 Data Transfer Interrupt Handling The data transfer interrupts indicate events related to IIC frame handling. As the data input and output pins are the same in IIC protocol, a IIC transmitter also receives the output data at its input pin.
Page 425 IMC300A iMOTION Controller with additional microcontroller 18 Universal Serial Interface Channel (USIC) Table 206 IIC protocol interrupt events (continued) Events Event flag Description Flag clear Interrupt enable Repeated start PSR.RSCR Set after a valid repeated start condition is PSCR.CST3 PCR.RSCRIEN condition detected.
Page 426 IMC300A iMOTION Controller with additional microcontroller 18 Universal Serial Interface Channel (USIC) In addition to the match of the programmed address, the slave can also be configured to acknowledge the address byte 00 , which indicates a general call address. This is done by setting the bit PCR.ACK00 to 1. In order to allow selective acknowledges for the different values of the address byte(s), the following control mechanism is implemented: •...
Page 427 IMC300A iMOTION Controller with additional microcontroller 18 Universal Serial Interface Channel (USIC) Table 207 IIC protocol related information in RBUF register Field Description RBUF[8] Value of the received acknowledge bit. This information is also available in RBUFSR[8] as protocol argument. RBUF[9] This bit indicates the data byte received after a (repeated) start condition and following the address reception:...
Page 428 IMC300A iMOTION Controller with additional microcontroller 18 Universal Serial Interface Channel (USIC) The same code can be used for master and slave mode operation. If the slave address is not needed (i.e. master only operation), the bit field PCR.SLAD can be programmed to 0. void USIC0_CH1_IIC_Init(void) /// -------------------------------------------------------------------- /// 1.
Page 429 IMC300A iMOTION Controller with additional microcontroller 18 Universal Serial Interface Channel (USIC) HDEL STIM SLAD USIC0_CH1->PCR = (7 << 26) | (1 << 17) | (5 << 9);; /// -------------------------------------------------------------------- /// 7. Enable IIC protocol /// -------------------------------------------------------------------- MODE USIC0_CH1->CCR = (4 << 0); /// -------------------------------------------------------------------- /// 8.
Page 430 IMC300A iMOTION Controller with additional microcontroller 18 Universal Serial Interface Channel (USIC) Table 208 Master Transmit Data Formats (continued) TDF Code Description Receive data byte and send acknowledge This format is used by the master to read a data byte from a slave. The master acknowledges the transfer with a 0-level to continue the transfer.
Page 431 IMC300A iMOTION Controller with additional microcontroller 18 Universal Serial Interface Channel (USIC) read will be stored in RBUF0/1, but RDV0/1 will not be set. Therefore the dummy read will not generate a receive interrupt and the data byte will not be stored into the receive FIFO. If the transfer direction has changed in the current frame (master read access), the transmit data request (TDF = ) is not possible and won't be accepted (leading to a wrong TDF Code indication).
Page 432 IMC300A iMOTION Controller with additional microcontroller 18 Universal Serial Interface Channel (USIC) codes are considered as wrong. To abort the transfer in case of a wrong code, the STOP condition is generated immediately. • After a master device has received a non-acknowledge from a slave device, a stop condition will be sent out automatically, except if the following TDF code requests a repeated start condition.
Page 433 IMC300A iMOTION Controller with additional microcontroller 18 Universal Serial Interface Channel (USIC) 18.5.4.3 Master Transmit/Receive Modes In master transmit mode, the IIC sends a number of data bytes to a slave receiver. The TDF code sequence for the master transmit mode is shown in Table 211.
Page 434 IMC300A iMOTION Controller with additional microcontroller 18 Universal Serial Interface Channel (USIC) Table 213 TDF Code Sequence for Master Receive (10-bit Addressing Mode) TDF Code TBUF[10:8] TBUF[7:0] IIC Response Interrupt Events Sequence (TDF Code) 1st code Slave address Send START condition, SCR: Indicates a START (1st byte) + slave address (1st byte)
Page 435 IMC300A iMOTION Controller with additional microcontroller 18 Universal Serial Interface Channel (USIC) Master Transmit – Slave Receive TBIF TBIF TBIF Master Transmit Slave Address Data Data Slave Receive Master Receive – Slave Transmit TBIF TBIF TBIF Master Receive Slave Address Data Data Slave...
Page 436 IMC300A iMOTION Controller with additional microcontroller 18 Universal Serial Interface Channel (USIC) Additionally, the service request output SRx of the USIC channel that becomes activated in case of an event condition can be selected by an interrupt node pointer. This structure allows to assign events to interrupts, e.g. depending on the application, several events can share the same interrupt routine (several events activate the same SRx output) or can be handled individually (only one event activates one SRx output).
Page 437 IMC300A iMOTION Controller with additional microcontroller 18 Universal Serial Interface Channel (USIC) PSCR INPR Clear CTSIF TSIF TSIEN TSINP Transmit Shift Interrupt Transmit Shift Event (End of last transmit shift clock period of data word) PSCR INPR Clear CTBIF TBIF TBIEN TBINP Transmit Buffer...
Page 438 IMC300A iMOTION Controller with additional microcontroller 18 Universal Serial Interface Channel (USIC) RBUFSR PSCR INPR Clear PERR CRIF RIEN RINP Standard Standard Receive Event Receive Interrupt New Data in RBUF Event Alternate Alternate Receive Event Receive Interrupt Clear CAIF AIEN AINP INPR PSCR...
Page 439 IMC300A iMOTION Controller with additional microcontroller 18 Universal Serial Interface Channel (USIC) PSCR INPR Clear CBRGIF BRGIF BRGIEN PINP Baud Rate Generator Interrupt Baud Rate Generator Event (Capture mode timer reaches its maximum value ) Figure 116 Baud Rate Generator Event and Interrupt 18.6.4 Protocol-specific Events and Interrupts These events are related to protocol-specific actions that are described in the corresponding protocol chapters.
Page 440 IMC300A iMOTION Controller with additional microcontroller 18 Universal Serial Interface Channel (USIC) The USIC module is clocked by the main clock, MCLK, from SCU. MCLK is disabled by default and can be enabled via the SCU_CGATCLR0 register. Enabling and disabling the module clock could cause a load change and clock blanking could occur as described in the CCU (Clock Gating Control) section of the SCU chapter.
Page 441 IMC300A iMOTION Controller with additional microcontroller 18 Universal Serial Interface Channel (USIC) Table 217 USIC Kernel-Related and Kernel Registers Register Short Register Long Name Offset Access Mode Description see Name Addr. Read Write Module Registers Module Identification Register U, PV U, PV Page Channel Registers...
Page 442 IMC300A iMOTION Controller with additional microcontroller 18 Universal Serial Interface Channel (USIC) Table 217 USIC Kernel-Related and Kernel Registers (continued) Register Short Register Long Name Offset Access Mode Description see Name Addr. Read Write RBUF Receiver Buffer Register U, PV U, PV Page RBUFD...
Page 443 IMC300A iMOTION Controller with additional microcontroller 18 Universal Serial Interface Channel (USIC) Table 218 Registers Address Space Module Base Address End Address Note USIC0_CH0 48000000 480001FF – USIC0_CH1 48000200 480003FF – USIC1_CH0 48004000 480041FF – USIC1_CH1 48004200 480043FF – Table 219 FIFO and Reserved Address Space Module Base Address...
Page 444 IMC300A iMOTION Controller with additional microcontroller 18 Universal Serial Interface Channel (USIC) (continued) Field Bits Type Description MOD_TYPE 15:8 Module Type This bit field is C0 . It defines the module as a 32-bit module. MOD_NUMBER 31:16 Module Number Value This bit field defines the USIC module identification number (00AA = USIC).
Page 445 IMC300A iMOTION Controller with additional microcontroller 18 Universal Serial Interface Channel (USIC) (continued) Field Bits Type Description HPCEN Hardware Port Control Enable This bit enables the hardware port control for the specified set of DX[3:0] and DOUT[3:0] pins. The hardware port control is disabled. The hardware port control is enabled for DX0 and DOUT0.
Page 446 IMC300A iMOTION Controller with additional microcontroller 18 Universal Serial Interface Channel (USIC) (continued) Field Bits Type Description TBIEN Transmit Buffer Interrupt Enable This bit enables the interrupt generation in case of a transmit buffer event. The transmit buffer interrupt is disabled. The transmit buffer interrupt is enabled.
Page 447 IMC300A iMOTION Controller with additional microcontroller 18 Universal Serial Interface Channel (USIC) Field Bits Type Description SSC Protocol Available This bit indicates if the SSC protocol is available. The SSC protocol is not available. The SSC protocol is available. ASC Protocol Available This bit indicates if the ASC protocol is available.
Page 448 IMC300A iMOTION Controller with additional microcontroller 18 Universal Serial Interface Channel (USIC) Field Bits Type Description MODEN Module Enable This bit enables the module kernel clock and the module functionality. The module is switched off immediately (without respecting a stop condition). It does not react on mode control actions and the module clock is switched off.
Page 449 IMC300A iMOTION Controller with additional microcontroller 18 Universal Serial Interface Channel (USIC) INPR Address: Interrupt Node Pointer Register Reset Value: 0000 0000 PINP AINP RINP TBINP TSINP Field Bits Type Description TSINP Transmit Shift Interrupt Node Pointer This bit field defines which service request output SRx becomes activated in case of a transmit shift interrupt.
Page 450 IMC300A iMOTION Controller with additional microcontroller 18 Universal Serial Interface Channel (USIC) 18.10.4 Protocol Related Registers 18.10.4.1 Protocol Control Register The bits in the protocol control register define protocol-specific functions. They have to be configured by software before enabling a new protocol. Only the bits used for the selected protocol are taken into account, whereas the other bit positions always read as 0.
Page 451 IMC300A iMOTION Controller with additional microcontroller 18 Universal Serial Interface Channel (USIC) Field Bits Type Description Sample Mode This bit field defines the sample mode of the ASC receiver. The selected data input signal can be sampled only once per bit time or three times (in consecutive time quanta).
Page 452 IMC300A iMOTION Controller with additional microcontroller 18 Universal Serial Interface Channel (USIC) (continued) Field Bits Type Description FEIEN Format Error Interrupt Enable This bit enables the generation of a protocol interrupt if a format error is detected. The automatic detection is always active, so bits PSR.FER0/FER1 can be set independently of PCR.FEIEN.
Page 453 IMC300A iMOTION Controller with additional microcontroller 18 Universal Serial Interface Channel (USIC) (continued) Field Bits Type Description MCLK Master Clock Enable This bit enables the generation of the master clock MCLK. The MCLK generation is disabled and the MCLK signal is 0. The MCLK generation is enabled.
Page 454 IMC300A iMOTION Controller with additional microcontroller 18 Universal Serial Interface Channel (USIC) (continued) Field Bits Type Description SELINV Select Inversion This bit defines if the polarity of the SELO[7:0] outputs in relation to the master slave select signal MSLS. The SELO outputs have the same polarity as the MSLS signal (active high).
Page 455 IMC300A iMOTION Controller with additional microcontroller 18 Universal Serial Interface Channel (USIC) (continued) Field Bits Type Description MSLSIEN MSLS Interrupt Enable This bit enables/disables the generation of a protocol interrupt if the state of the MSLS signal changes (indicated by PSR.MSLSEV = 1).
Page 456 IMC300A iMOTION Controller with additional microcontroller 18 Universal Serial Interface Channel (USIC) Address: Protocol Control Register [IIC Mode] Reset Value: 0000 0000 ACKI SACK ERRI SRRI ARLI PCRI SCRI ACK0 MCLK HDEL STIM KIEN RIEN SLAD Field Bits Type Description SLAD 15:0 Slave Address...
Page 457 IMC300A iMOTION Controller with additional microcontroller 18 Universal Serial Interface Channel (USIC) (continued) Field Bits Type Description NACKIEN Non-Acknowledge Interrupt Enable This bit enables the generation of a protocol interrupt if a non- acknowledge is detected by a master. The non-acknowledge interrupt is disabled. The non-acknowledge interrupt is enabled.
Page 458 IMC300A iMOTION Controller with additional microcontroller 18 Universal Serial Interface Channel (USIC) (continued) Field Bits Type Description MCLK Master Clock Enable This bit enables generation of the master clock MCLK (not directly used for IIC protocol, can be used as general frequency output). The MCLK generation is disabled and MCLK is 0.
Page 459 IMC300A iMOTION Controller with additional microcontroller 18 Universal Serial Interface Channel (USIC) (continued) Field Bits Type Description Receive Indication Flag A receive event has not occurred. A receive event has occurred. Alternative Receive Indication Flag An alternative receive event has not occurred. An alternative receive event has occurred.
Page 460 IMC300A iMOTION Controller with additional microcontroller 18 Universal Serial Interface Channel (USIC) (continued) Field Bits Type Description Synchronization Break Detected This bit is set if a programmed number of consecutive bit values with level 0 has been detected (called synchronization break, e.g. in a LIN bus system).
Page 461 IMC300A iMOTION Controller with additional microcontroller 18 Universal Serial Interface Channel (USIC) (continued) Field Bits Type Description RSIF Receiver Start Indication Flag A receiver start event has not occurred. A receiver start event has occurred. DLIF Data Lost Indication Flag A data lost event has not occurred.
Page 462 IMC300A iMOTION Controller with additional microcontroller 18 Universal Serial Interface Channel (USIC) Field Bits Type Description MSLS MSLS Status This bit indicates the current status of the MSLS signal. It must be cleared by software to stop a running frame. The internal signal MSLS is inactive (0).
Page 463 IMC300A iMOTION Controller with additional microcontroller 18 Universal Serial Interface Channel (USIC) (continued) Field Bits Type Description Receive Indication Flag A receive event has not occurred. A receive event has occurred. Alternative Receive Indication Flag An alternative receive event has not occurred. An alternative receive event has occurred.
Page 464 IMC300A iMOTION Controller with additional microcontroller 18 Universal Serial Interface Channel (USIC) (continued) Field Bits Type Description Start Condition Received This bit indicates that a start condition has been detected on the IIC bus lines.A protocol interrupt can be generated if PCR.SCRIEN = 1.
Page 465 IMC300A iMOTION Controller with additional microcontroller 18 Universal Serial Interface Channel (USIC) (continued) Field Bits Type Description Error This bit indicates that an IIC error (frame format or TDF code) has been detected. A protocol interrupt can be generated if PCR.ERRIEN = 1.
Page 466 IMC300A iMOTION Controller with additional microcontroller 18 Universal Serial Interface Channel (USIC) PSCR Address: Protocol Status Clear Register Reset Value: 0000 0000 CTBI CTSI CDLI CRSI CAIF CRIF CST9 CST8 CST7 CST6 CST5 CST4 CST3 CST2 CST1 CST0 Field Bits Type Description CSTx (x=0-9)
Page 467 IMC300A iMOTION Controller with additional microcontroller 18 Universal Serial Interface Channel (USIC) 18.10.5 Input Stage Register 18.10.5.1 Input Control Registers The input control registers contain the bits to define the characteristics of the input stages (input stage DX0 is controlled by register DX0CR, etc.). 18.10.5.1.1 Register DX0CR, DX2CR, DX3CR, DX4CR, DX5CR DX0CR...
Page 468 IMC300A iMOTION Controller with additional microcontroller 18 Universal Serial Interface Channel (USIC) (continued) Field Bits Type Description INSW Input Switch This bit defines if the data shift unit input is derived from the input data path DXn or from the selected protocol pre-processors. The input of the data shift unit is controlled by the protocol pre-processor.
Page 469 IMC300A iMOTION Controller with additional microcontroller 18 Universal Serial Interface Channel (USIC) (continued) Field Bits Type Description 3, 7, Reserved 14:12, Read as 0; should be written with 0. 31:16 18.10.5.1.2 Register DX1CR DX1CR Address: Input Control Register 1 Reset Value: 0000 0000 SFSE DSEL...
Page 470 IMC300A iMOTION Controller with additional microcontroller 18 Universal Serial Interface Channel (USIC) (continued) Field Bits Type Description INSW Input Switch This bit defines if the data shift unit input is derived from the input data path DX1 or from the selected protocol pre-processors. The input of the data shift unit is controlled by the protocol pre-processor.
Page 471 IMC300A iMOTION Controller with additional microcontroller 18 Universal Serial Interface Channel (USIC) (continued) Field Bits Type Description 7, 14:12, Reserved 31:16 Read as 0; should be written with 0. 18.10.6 Baud Rate Generator Registers 18.10.6.1 Register FDR The fractional divider register FDR allows the generation of the internal frequency f , that is derived from the system clock f PERIPH...
Page 472 IMC300A iMOTION Controller with additional microcontroller 18 Universal Serial Interface Channel (USIC) (continued) Field Bits Type Description 13:10, Reserved 29:26 Read as 0; should be written with 0. 18.10.6.2 Register BRG The protocol-related counters for baud rate generation and timing measurement are controlled by the register BRG.
Page 473 IMC300A iMOTION Controller with additional microcontroller 18 Universal Serial Interface Channel (USIC) (continued) Field Bits Type Description CTQSEL Input Selection for CTQ This bit defines the length of a time quantum for the protocol pre-processor. CTQIN PDIV CTQIN CTQIN SCLK CTQIN MCLK PCTQ...
Page 474 IMC300A iMOTION Controller with additional microcontroller 18 Universal Serial Interface Channel (USIC) 18.10.6.3 Register CMTR The captured timer value is provided by the register CMTR. CMTR Address: Capture Mode Timer Register Reset Value: 0000 0000 Field Bits Type Description Captured Timer Value The value of the counter is captured into this bit field if one of the trigger signals DX0T or DX1T are activated by the corresponding input stage.
Page 475 IMC300A iMOTION Controller with additional microcontroller 18 Universal Serial Interface Channel (USIC) Field Bits Type Description SDIR Shift Direction This bit defines the shift direction of the data words for transmission and reception. Shift LSB first. The first data bit of a data word is located at bit position 0.
Page 476 IMC300A iMOTION Controller with additional microcontroller 18 Universal Serial Interface Channel (USIC) (continued) Field Bits Type Description Transmission Mode This bit field describes how the shift control signal is interpreted by the DSU. Data transfers are only possible while the shift control signal is active.
Page 477 IMC300A iMOTION Controller with additional microcontroller 18 Universal Serial Interface Channel (USIC) TSOF TDVT TDSS TDEN Field Bits Type Description WLEMD WLE Mode This bit enables the data handler to automatically update the bit field SCTR.WLE by the transmit control information TCI[3:0] and bit TCSR.EOF by TCI[4] (see page 346).
Page 478 IMC300A iMOTION Controller with additional microcontroller 18 Universal Serial Interface Channel (USIC) (continued) Field Bits Type Description HPCMD Hardware Port Control Mode This bit can be used mainly for the dual and quad SSC protocol. It enables the data handler to automatically update bit SCTR.DSM by the transmit control information TCI[1:0] and bit SCTR.HPCDIR by TCI[2] (see page 346).
Page 479 IMC300A iMOTION Controller with additional microcontroller 18 Universal Serial Interface Channel (USIC) (continued) Field Bits Type Description TDSSM TBUF Data Single Shot Mode This bit defines if the data word TBUF data is considered as permanently valid or if the data should only be transferred once. The data word in TBUF is not considered as invalid after it has been loaded into the transmit shift register.
Page 480 IMC300A iMOTION Controller with additional microcontroller 18 Universal Serial Interface Channel (USIC) (continued) Field Bits Type Description TSOF Transmitted Start Of Frame This bit indicates if the latest start of a data word transmission has taken place for the first data word of a new data frame. This bit is updated with the transmission start of each data word.
Page 481 IMC300A iMOTION Controller with additional microcontroller 18 Universal Serial Interface Channel (USIC) Address: Flag Modification Register Reset Value: 0000 0000 SIO5 SIO4 SIO3 SIO2 SIO1 SIO0 CRDV ATVC MTDV Field Bits Type Description MTDV Modify Transmit Data Valid Writing to this bit field can modify bits TCSR.TDV and TCSR.TE to control the start of a data word transmission by software.
Page 482 IMC300A iMOTION Controller with additional microcontroller 18 Universal Serial Interface Channel (USIC) 18.10.8 Data Buffer Registers 18.10.8.1 Transmit Buffer Locations The 32 independent data input locations TBUF00 to TBUF31 are address locations that can be used as data entry locations for the transmit buffer. Data written to one of these locations will appear in a common register TBUF.
Page 483 IMC300A iMOTION Controller with additional microcontroller 18 Universal Serial Interface Channel (USIC) DSR0 Field Bits Type Description DSR0 15:0 Data of Shift Registers 0[3:0] 31:16 Reserved Read as 0; should be written with 0. 18.10.8.2.2 Register RBUF1 The receive buffer register RBUF1 contains the data received from RSR1[3:0]. A read action does not change the status of the receive data from “not yet read = valid”...
Page 484 IMC300A iMOTION Controller with additional microcontroller 18 Universal Serial Interface Channel (USIC) RDV1 RDV1 PAR1 SOF1 WLEN1 RDV0 RDV0 PAR0 SOF0 WLEN0 Field Bits Type Description WLEN0 Received Data Word Length in RBUF0 This bit field indicates how many bits have been received within the last data word stored in RBUF0.
Page 485 IMC300A iMOTION Controller with additional microcontroller 18 Universal Serial Interface Channel (USIC) (continued) Field Bits Type Description PERR0 Protocol-related Error in RBUF0 This bit indicates if the value of the protocol-related argument meets an expected value. This value is elaborated depending on the selected protocol and adds additional information to the data word in RBUF0.
Page 486 IMC300A iMOTION Controller with additional microcontroller 18 Universal Serial Interface Channel (USIC) (continued) Field Bits Type Description WLEN1 19:16 Received Data Word Length in RBUF1 This bit field indicates how many bits have been received within the last data word stored in RBUF1. This number indicates how many data bits have to be considered as receive data, whereas the other bits in RBUF1 have been cleared automatically.
Page 487 IMC300A iMOTION Controller with additional microcontroller 18 Universal Serial Interface Channel (USIC) (continued) Field Bits Type Description RDV11 Receive Data Valid in RBUF1 This bit indicates the status of the data content of register RBUF1. This bit is identical to bit RBUF01SR.RDV01 and allows consisting reading of information for the receive buffer registers.
Page 488 IMC300A iMOTION Controller with additional microcontroller 18 Universal Serial Interface Channel (USIC) Field Bits Type Description 15:0 Received Data This bit field monitors the content of either RBUF0 or RBUF1, depending on the reception sequence. 31:16 Reserved Read as 0; should be written with 0. 18.10.8.3.2 Register RBUFD If a debugger should be used to monitor the received data, the automatic update mechanism has to be de-...
Page 489 IMC300A iMOTION Controller with additional microcontroller 18 Universal Serial Interface Channel (USIC) RDV1 RDV0 WLEN Field Bits Type Description WLEN Received Data Word Length in RBUF or RBUFD Description see RBUF01SR.WLEN0 or RBUF01SR.WLEN1. Start of Frame in RBUF or RBUFD Description see RBUF01SR.SOF0 or RBUF01SR.SOF1.
Page 490 IMC300A iMOTION Controller with additional microcontroller 18 Universal Serial Interface Channel (USIC) BDATA Field Bits Type Description BDATA 15:0 Bypass Data This bit field contains the bypass data. 31:16 Reserved Read as 0; should be written with 0. 18.10.9.1.2 Register BYPCR BYPCR Address: Bypass Control Register...
Page 491 IMC300A iMOTION Controller with additional microcontroller 18 Universal Serial Interface Channel (USIC) (continued) Field Bits Type Description BDEN 11:10 Bypass Data Enable This bit field defines if and how the transfer of bypass data to TBUF is enabled. The transfer of bypass data is disabled. The transfer of bypass data to TBUF is possible.
Page 492 IMC300A iMOTION Controller with additional microcontroller 18 Universal Serial Interface Channel (USIC) 18.10.9.2 General FIFO Buffer Control Registers The transmit and receive FIFO status information of USICx_CHy is given in registers USICx_CHy.TRBSR. The bits related to the transmitter buffer in this register can only by written if the transmit buffer functionality is enabled by CCFG.TB = 1, otherwise write accesses are ignored.
Page 493 IMC300A iMOTION Controller with additional microcontroller 18 Universal Serial Interface Channel (USIC) (continued) Field Bits Type Description ARBI Alternative Receive Buffer Event This bit indicates that an alternative receive buffer event has been detected. It is cleared by writing TRBSCR.CARBI = 1. If enabled by RBCTR.ARBIEN, the service request output SRx selected by RBCTR.ARBINP becomes activated if an alternative receive buffer event is detected.
Page 494 IMC300A iMOTION Controller with additional microcontroller 18 Universal Serial Interface Channel (USIC) (continued) Field Bits Type Description TBERI Transmit Buffer Error Event This bit indicates that a transmit buffer error event has been detected. It is cleared by writing TRBSCR.CTBERI = 1. If enabled by TBCTR.TBERIEN, the service request output SRx selected by TBCTR.ATBINP becomes activated if a transmit buffer error event is detected.
Page 495 IMC300A iMOTION Controller with additional microcontroller 18 Universal Serial Interface Channel (USIC) 18.10.9.2.2 Register TRBSCR The bits in register TRBSCR are used to clear the notification bits in register TRBSR or to clear the FIFO mechanism for the transmit or receive buffer. A read action always delivers 0. TRBSCR Address: Transmit/Receive Buffer Status Clear Register...
Page 496 IMC300A iMOTION Controller with additional microcontroller 18 Universal Serial Interface Channel (USIC) (continued) Field Bits Type Description FLUSHTB Flush Transmit Buffer No effect. The transmit FIFO buffer is cleared (filling level is cleared and output pointer is set to input pointer value). Should only be used while the FIFO buffer is not taking part in data traffic.
Page 497 IMC300A iMOTION Controller with additional microcontroller 18 Universal Serial Interface Channel (USIC) (continued) Field Bits Type Description STBTM Standard Transmit Buffer Trigger Mode This bit selects the standard transmit buffer event trigger mode. Trigger mode 0: While TRBSR.STBT=1, a standard transmit buffer event will be generated whenever there is a data transfer to TBUF or data write to INx (depending on TBCTR.LOF setting).
Page 498 IMC300A iMOTION Controller with additional microcontroller 18 Universal Serial Interface Channel (USIC) (continued) Field Bits Type Description SIZE 26:24 Buffer Size This bit field defines the number of FIFO entries assigned to the transmit FIFO buffer. The FIFO mechanism is disabled. The buffer does not accept any request for data.
Page 499 IMC300A iMOTION Controller with additional microcontroller 18 Universal Serial Interface Channel (USIC) RBCTR Address: Receiver Buffer Control Register Reset Value: 0000 0000 RBER SRBI ARBI LOF RNM SIZE RCIM ARBINP SRBINP SRBT LIMIT DPTR Field Bits Type Description DPTR Data Pointer This bit field defines the start value for the receive buffer pointers when assigning the FIFO entries to the receive FIFO buffer.
Page 500 IMC300A iMOTION Controller with additional microcontroller 18 Universal Serial Interface Channel (USIC) (continued) Field Bits Type Description SRBINP 18:16 Standard Receive Buffer Interrupt Node Pointer This bit field defines which service request output SRx becomes activated in case of a standard receive buffer event. Output SR0 becomes activated.
Page 501 IMC300A iMOTION Controller with additional microcontroller 18 Universal Serial Interface Channel (USIC) (continued) Field Bits Type Description Receiver Notification Mode This bit defines the receive buffer event mode. The receive buffer error event is not affected by RNM. Filling level mode: A standard receive buffer event occurs when the filling level equals the limit value and changes, either due to a read access from OUTR (LOF = 0) or due to a new received data word (LOF = 1).
Page 502 IMC300A iMOTION Controller with additional microcontroller 18 Universal Serial Interface Channel (USIC) 18.10.9.5 FIFO Buffer Data Registers 18.10.9.5.1 Register INx The 32 independent data input locations IN00 to IN31 are addresses that can be used as data entry locations for the transmit FIFO buffer.
Page 503 IMC300A iMOTION Controller with additional microcontroller 18 Universal Serial Interface Channel (USIC) Field Bits Type Description 15:0 Received Data This bit field monitors the content of the oldest data word in the receive FIFO. Reading at least the low byte releases the buffer entry currently shown in DSR.
Page 504 IMC300A iMOTION Controller with additional microcontroller 18 Universal Serial Interface Channel (USIC) 18.10.9.6.1 Register TRBPTR TRBPTR Address: Transmit/Receive Buffer Pointer Register Reset Value: 0000 0000 RDOPTR RDIPTR TDOPTR TDIPTR Field Bits Type Description TDIPTR Transmitter Data Input Pointer This bit field indicates the buffer entry that will be used for the next transmit data coming from the INx addresses.
Page 505 IMC300A iMOTION Controller with additional microcontroller 18 Universal Serial Interface Channel (USIC) Port Lines Port Lines USIC0 USIC1 Bus Interface Bus Interface AHB-Lite Bus Figure 118 USIC Module Structure in IMC300A The next sections define the pin assignments and internal connections of each USIC module and channel in the IMC300A device.
Page 506 IMC300A iMOTION Controller with additional microcontroller 18 Universal Serial Interface Channel (USIC) Table 220 USIC0 Channel 0 Interconnects (continued) Input/Output Connected To Description USIC0_CH0.HWIN0 P1.0 HW controlled shift data input Clock Inputs USIC0_CH0.DX1A P0.14 Shift clock input; used for: • SSC Slave SCLKIN USIC0_CH0.DX1B P0.8...
Page 507 IMC300A iMOTION Controller with additional microcontroller 18 Universal Serial Interface Channel (USIC) Table 220 USIC0 Channel 0 Interconnects (continued) Input/Output Connected To Description USIC0_CH0.HWIN2 HW controlled shift data input Data Inputs (DX5) USIC0_CH0.DX5A Shift data input; used for: • Quad SSC MTSR3/MRST3 USIC0_CH0.DX5B •...
Page 508 IMC300A iMOTION Controller with additional microcontroller 18 Universal Serial Interface Channel (USIC) Table 220 USIC0 Channel 0 Interconnects (continued) Input/Output Connected To Description USIC0_CH0.SELO0 P0.9; Shift control output; used for: USIC0_CH0.DX5G • SSC Master SELO • Can be ignored for all other protocols USIC0_CH0.SELO1 P0.10;...
Page 509 IMC300A iMOTION Controller with additional microcontroller 18 Universal Serial Interface Channel (USIC) Table 221 USIC0 Channel 1 Interconnects (continued) Input/Output Connected To Description USIC0_CH1.DX1A Shift clock input; used for: • SSC Slave SCLKIN USIC0_CH1.DX1B P0.8 • IIC SCL USIC0_CH1.DX1C • Optional for ASC, SSC Master USIC0_CH1.DX1D USIC0_CH1.DX1E...
Page 510 IMC300A iMOTION Controller with additional microcontroller 18 Universal Serial Interface Channel (USIC) Table 221 USIC0 Channel 1 Interconnects (continued) Input/Output Connected To Description USIC0_CH1.DX5A P2.2 Shift data input; used for: • Quad SSC MTSR3/MRST3 USIC0_CH1.DX5B • Can be ignored for all other protocols USIC0_CH1.DX5C P2.8 USIC0_CH1.DX5D...
Page 511 IMC300A iMOTION Controller with additional microcontroller 18 Universal Serial Interface Channel (USIC) Table 221 USIC0 Channel 1 Interconnects (continued) Input/Output Connected To Description USIC0_CH1.SELO4 not connected USIC0_CH1.SELO5 not connected USIC0_CH1.SELO6 not connected USIC0_CH1.SELO7 not connected System Related Outputs USIC0_CH1.DX0INS USIC0_CH1.DX1F Selected DX0 input signal USIC0_CH1.DX1INS not connected...
Page 512 IMC300A iMOTION Controller with additional microcontroller 18 Universal Serial Interface Channel (USIC) Table 223 USIC1 Channel 0 Interconnects Input/Output Connected To Description Data Inputs (DX0) USIC1_CH0.DX0A Shift data input; used for: • ASC RXD USIC1_CH0.DX0B • SSC MTSR/MRST USIC1_CH0.DX0C P4.4 •...
Page 513 IMC300A iMOTION Controller with additional microcontroller 18 Universal Serial Interface Channel (USIC) Table 223 USIC1 Channel 0 Interconnects (continued) Input/Output Connected To Description Data Inputs (DX4) USIC1_CH0.DX4A Shift data input; used for: • Quad SSC MTSR2/MRST2 USIC1_CH0.DX4B • Can be ignored for all other protocols USIC1_CH0.DX4C USIC1_CH0.DX4D P4.0...
Page 514 IMC300A iMOTION Controller with additional microcontroller 18 Universal Serial Interface Channel (USIC) Table 223 USIC1 Channel 0 Interconnects (continued) Input/Output Connected To Description USIC1_CH0.SCLKOUT Shift clock output; used for: P4.3; • Master SCLKOUT in SSC P4.5; • IIC SCL P4.6; •...
Page 515 IMC300A iMOTION Controller with additional microcontroller 18 Universal Serial Interface Channel (USIC) DX0(A) Input Stage P 0.2 DX0(B) P 0.3 DX0(C) (Data) P 4.4 DX0(D) P 4.5 DX0(E) DX0INS P 3.3 DX0(F) P 3.4 DX3INS DX0(G) P3.4 HWIN0 Input Stage P0.2 DX1(A) DX1(B)
Page 516 IMC300A iMOTION Controller with additional microcontroller 18 Universal Serial Interface Channel (USIC) Table 224 USIC1 Channel 1 Interconnects Input/Output Connected To Description Data Inputs (DX0) USIC1_CH1.DX0A Shift data input; used for: • ASC RXD USIC1_CH1.DX0B • SSC MTSR/MRST USIC1_CH1.DX0C • IIC SDA USIC1_CH1.DX0D USIC1_CH1.DX0E...
Page 517 IMC300A iMOTION Controller with additional microcontroller 18 Universal Serial Interface Channel (USIC) Table 224 USIC1 Channel 1 Interconnects (continued) Input/Output Connected To Description Data Inputs (DX4) USIC1_CH1.DX4A Shift data input; used for: • Quad SSC MTSR2/MRST2 USIC1_CH1.DX4B P0.15 • Can be ignored for all other protocols USIC1_CH1.DX4C USIC1_CH1.DX4D USIC1_CH1.DX4E...
Page 518 IMC300A iMOTION Controller with additional microcontroller 18 Universal Serial Interface Channel (USIC) Table 224 USIC1 Channel 1 Interconnects (continued) Input/Output Connected To Description USIC1_CH1.SCLKOUT Shift clock output; used for: • Master SCLKOUT in SSC USIC1_CH1.DX4G; • IIC SCL • Can be ignored in ASC Control Outputs USIC1_CH1.SELO0 Shift control output;...
Page 519 IMC300A iMOTION Controller with additional microcontroller 18 Universal Serial Interface Channel (USIC) DX0(A) Input Stage P0.0 DX0(B) P0.1 DX0(C) (Data) P 2.12 DX0(D) P 2.13 DX0(E) DX0INS P3.0 DX0(F) P3.1 DX3INS DX0(G) ERU1. HWIN0 PDOUT0 Input Stage P0.1 DX1(A) P 2.12 DX1(B) DX1(C) (Clock)
Page 520 IMC300A iMOTION Controller with additional microcontroller 18 Universal Serial Interface Channel (USIC) Table 225 USIC1 Global Interconnects Input/Output Connected To Description USIC1_SR0 NVIC; Service request Output 0 USIC1_CH1.DX2F USIC1_SR1 NVIC Service request Output 1 USIC1_SR2 NVIC Service request Output 2 USIC1_SR3 NVIC Service request Output 3...
Page 521 IMC300A iMOTION Controller with additional microcontroller 19 Controller Area Network Controller (MulticanCAN+) Controller Area Network Controller (MulticanCAN+) This chapter describes the MulticanCAN+ controller of the IMC300A. It contains the following sections: • CAN basics (see page 521) • Overview of the CAN Module in the IMC300A (see page 526) •...
Page 522 IMC300A iMOTION Controller with additional microcontroller 19 Controller Area Network Controller (MulticanCAN+) other nodes switch to receive mode during the first transmitted bit (Start-Of-Frame bit). After correct reception of the message (acknowledged by each node), each bus node checks the message identifier and stores the message, if required.
Page 523 IMC300A iMOTION Controller with additional microcontroller 19 Controller Area Network Controller (MulticanCAN+) Seven recessive End-of-Frame (EOF) bits finish the Data Frame. Between any two consecutive frames, the bus must remain in the recessive state for at least 3 bit times (called Inter Frame Space). If after the Inter Frame Space, no other nodes attempt to transmit the bus remains in idle state with a recessive level.
Page 524 IMC300A iMOTION Controller with additional microcontroller 19 Controller Area Network Controller (MulticanCAN+) • The RTR bit is in the recessive state in a Remote Frame. • There is no Data Field in a Remote Frame. If a Data Frame and a Remote Frame with the same identifier are transmitted at the same time, the Data Frame wins arbitration due to the dominant RTR bit following the identifier.
Page 525 IMC300A iMOTION Controller with additional microcontroller 19 Controller Area Network Controller (MulticanCAN+) Nominal Bit Time Synchronisation Propagation Phase Buffer Phase Buffer Segment Segment Segment 1 Segment 2 (SYNC_SEG) (PROP_SEG) (PHASE_SEG1) (PHASE_SEG2) Sample Point MCA06261 Figure 124 Partition of Nominal Bit Time The Synchronization Segment (SYNC_SEG) is used to synchronize the various bus nodes.
Page 526 IMC300A iMOTION Controller with additional microcontroller 19 Controller Area Network Controller (MulticanCAN+) the just transmitted bit. In case b), no error occurs during the Arbitration Field (ID, RTR, IDE) and the Acknowledge Slot. Stuff Error If between Start of Frame and CRC Delimiter, six consecutive bits with the same polarity are detected, the bit-stuffing rule has been violated.
Page 527 IMC300A iMOTION Controller with additional microcontroller 19 Controller Area Network Controller (MulticanCAN+) MCLK MultiCAN+ Module Kernel Baud Rate Clock Block Pin x.y Clock MCLK Control TXDCn Node n RXDCn Message (DMA Line Object Linked Router) Buffer List Port Control Control INT_O CCU4 Objects...
Page 528 IMC300A iMOTION Controller with additional microcontroller 19 Controller Area Network Controller (MulticanCAN+) Low-jitter E-Ray PLL clock Direct oscillator clock (e.g. from ceramic resonator) • Frequency jitter calibration based on external CAN messages during runtime • Flexible and powerful message transfer control and error handling capabilities •...
Page 529 IMC300A iMOTION Controller with additional microcontroller 19 Controller Area Network Controller (MulticanCAN+) 19.3.1 Module Structure Figure 126 shows the general structure of the MulticanCAN+ module. CAN Bus 0 CAN Bus 1 . . . CAN Bus x-1 Node Bitstream Processor Control Unit Error...
Page 530 IMC300A iMOTION Controller with additional microcontroller 19 Controller Area Network Controller (MulticanCAN+) • Enable/disable and generate node-specific events that lead to an interrupt request (CAN bus errors, successful frame transfers etc.) • Administration of the frame counter Interrupt Control Unit The Interrupt Control Unit in the CAN node controls the interrupt generation for the different conditions that can occur in the CAN node.
Page 531 IMC300A iMOTION Controller with additional microcontroller 19 Controller Area Network Controller (MulticanCAN+) 19.3.2 Clock Control The CAN module timer clock f of the functional blocks of the MulticanCAN+ module is derived from the synchronous clock source. The Fractional Divider is used to generate f used for bit timing calculation, The frequency of f is identical for all CAN nodes.
Page 532 IMC300A iMOTION Controller with additional microcontroller 19 Controller Area Network Controller (MulticanCAN+) = 8 × T + 8 × T + 4 × No. of active CAN nodes × T Baudrate also NBTR.SJW < NBTR.TSEG1 Equation 24 As an example, when f = 10 MHz, f = 20 MHz, No of active CAN nodes = 2, Baudrate...
Page 533 IMC300A iMOTION Controller with additional microcontroller 19 Controller Area Network Controller (MulticanCAN+) CAN Analyzer Mode CAN Analyzer Mode is activated when bit NCRx.CALM is set to 1. In this operation mode, Data And Remote Frames are monitored without active participation in any CAN transfer (CAN transmit pin is held on recessive level).
Page 534 IMC300A iMOTION Controller with additional microcontroller 19 Controller Area Network Controller (MulticanCAN+) account the physical propagation delay in the transmitter output driver on the CAN bus line and in the transceiver circuit. For a working collision detection mechanism, T must be two times the sum of all Prop propagation delay quantities rounded up to a multiple of t .
Page 535 IMC300A iMOTION Controller with additional microcontroller 19 Controller Area Network Controller (MulticanCAN+) The data consistency of an incoming frame is verified by checking the associated CRC field. When an error has been detected, a CAN LEC error interrupt request is generated and the associated error code is presented in the Node x Status Register NSRx.
Page 536 IMC300A iMOTION Controller with additional microcontroller 19 Controller Area Network Controller (MulticanCAN+) 19.3.4.5 CAN Node Interrupts Each CAN node has four hardware triggered interrupt request types that are able to generate an interrupt request upon: • The successful transmission or reception of a frame •...
Page 537 IMC300A iMOTION Controller with additional microcontroller 19 Controller Area Network Controller (MulticanCAN+) NSRx NCRx Correct Message Object Transfer TXOK TRIE NIPRx ≥1 Transmit TRINP Receive RXOK NSRx NSRx NCRx LECIE NIPRx CAN Error LECINP NCRx NSRx ALIE ≥1 EWRN NIPRx BOFF ALINP List Length Error...
Page 538 IMC300A iMOTION Controller with additional microcontroller 19 Controller Area Network Controller (MulticanCAN+) 19.3.5.1 Basics The message objects of the MulticanCAN+ module are organized in double-chained lists, where each message object has a pointer to the previous message object in the list as well as a pointer to the next message object in the list.
Page 539 IMC300A iMOTION Controller with additional microcontroller 19 Controller Area Network Controller (MulticanCAN+) 19.3.5.3 Connection to the CAN Nodes Each CAN node is linked to one unique list of message objects. A CAN node performs message transfer only with the message objects that are allocated to the list of the CAN node. This is illustrated in Figure 132.
Page 540 IMC300A iMOTION Controller with additional microcontroller 19 Controller Area Network Controller (MulticanCAN+) The list controller and the associated command panel allows the programmer to concentrate on the final properties of the list, which are characterized by the allocation of message objects to a CAN node, and the ordering relation between objects that are allocated to the same list.
Page 541 IMC300A iMOTION Controller with additional microcontroller 19 Controller Area Network Controller (MulticanCAN+) The results of a dynamic allocation command are written before the list controller starts the actual allocation process. As soon as the results are available, RBUSY becomes inactive (RBUSY = 0) again, while BUSY still remains active until completion of the command.
Page 542 IMC300A iMOTION Controller with additional microcontroller 19 Controller Area Network Controller (MulticanCAN+) internal CAN bus NPCR0.LBM CAN Bus 0 CAN node 0 NPCR1.LBM CAN Bus 1 CAN node 1 NPCRx.LBM CAN Bus x-1 CAN node x MultiCAN_loop_back_x.vsd Figure 133 Loop-Back Mode 19.3.6.3 Bit Timing Analysis Detailed analysis of the bit timing can be performed for each CAN node using the analysis modes of the CAN...
Page 543 IMC300A iMOTION Controller with additional microcontroller 19 Controller Area Network Controller (MulticanCAN+) may be derived from this time as the first edge after the sample point triggers synchronization and there is only one synchronization between consecutive sample points. Synchronization analysis can be used, for example, for fine tuning of the baud rate during reception of the first CAN frame with the measured baud rate.
Page 544 IMC300A iMOTION Controller with additional microcontroller 19 Controller Area Network Controller (MulticanCAN+) Identifier of 0 = Bit match Received Frame Bitwise 1 = No match Identifier of Message Object Acceptance Mask of Bitwise match Message Object = 0: ID of the received frame fits to message object match >...
Page 545 IMC300A iMOTION Controller with additional microcontroller 19 Controller Area Network Controller (MulticanCAN+) & MSGVAL TXRQ 0 = Object will not be transmitted 1 = Object is requested for transmission TXEN0 TXEN1 MCA06272 Figure 135 Effective Transmit Request of Message Object 19.3.8 Message Postprocessing After a message object has successfully received or transmitted a frame, the CPU can be notified to perform a...
Page 546 IMC300A iMOTION Controller with additional microcontroller 19 Controller Area Network Controller (MulticanCAN+) MOSTATn MOFCRn TXPND RXPND OVIE TXIE RXIE = 0010 MOIPRn = 0001 Message n ≥1 transmitted TXINP & Message n & FIFO full MOIPRn ≥1 Message n RXINP received MMC = 0001 : Message object n is a Receive FIFO Base Object...
Page 547 IMC300A iMOTION Controller with additional microcontroller 19 Controller Area Network Controller (MulticanCAN+) Message Object n Interrupt Pointer Register MOIPRn[15:0] TXINP RXINP 0 = Transmit Event 1 = Receive Event Message Pending Registers MSPND7 MSPND6 MSPND5 MSPND4 MSPND3 MSPND2 MSPND1 MSPND0 .
Page 548 IMC300A iMOTION Controller with additional microcontroller 19 Controller Area Network Controller (MulticanCAN+) • At a transmit event, the upper 3 bits of TXINP determine the number k of a Message Pending Register MSPNDk in which the pending bit will be set. At a receive event, the upper 3 bits of RXINP determine the number k.
Page 549 IMC300A iMOTION Controller with additional microcontroller 19 Controller Area Network Controller (MulticanCAN+) frame that belongs to the old context of the message object. Therefore, a message object re-configuration should consist of the following steps: Clear MSGVAL bit Re-configure the message object while MSGVAL = 0 Clear RTSEL bit and set MSGVAL again RXEN Bit MOSTATn.RXEN enables a message object for frame reception.
Page 550 IMC300A iMOTION Controller with additional microcontroller 19 Controller Area Network Controller (MulticanCAN+) Start receiving Get data from CAN frame gateway/FIFO source Object wins acc. Filtering ? Time Milestones RTSEL := 1 CAN rec. successful ? MSGVAL & MSGVAL = 1? RTSEL = 1? RXUPD := 1 RXUPD := 1...
Page 551 IMC300A iMOTION Controller with additional microcontroller 19 Controller Area Network Controller (MulticanCAN+) The transmission process of a message object starting after the transmit acceptance filtering is identical for Remote and Data Frames. MSGVAL, TXRQ, TXEN0, TXEN1 A message can only be transmitted if all four bits in registers MOSTATn, MSGVAL (Message Valid), TXRQ (Transmit Request), TXEN0 (Transmit Enable 0), TXEN1 (Transmit Enable 1) are set as shown in Figure 135.
Page 552 IMC300A iMOTION Controller with additional microcontroller 19 Controller Area Network Controller (MulticanCAN+) NEWDAT When the contents of a message object have been transferred to the internal transmit buffer of the CAN node, bit MOSTATn.NEWDAT (New Data) is cleared by hardware to indicate that the transmit message object data is no longer new.
Page 553 IMC300A iMOTION Controller with additional microcontroller 19 Controller Area Network Controller (MulticanCAN+) Object wins transmit acc. filtering Time Milestones RTSEL := 1 Copy Message to internal transmit buffer MSGVAL & TXRQ & TXEN0 & TXEN1 = 1 continuously valid RTSEL = 1? Request transmission of internal buffer on CAN bus...
Page 554 IMC300A iMOTION Controller with additional microcontroller 19 Controller Area Network Controller (MulticanCAN+) 19.3.10 Message Object Functionality This chapter describes the functionality of the Message Objects in the MulticanCAN+ module. 19.3.10.1 Standard Message Object A message object is selected as standard message object when bit field MOFCRn.MMC = 0000 (see page 583).
Page 555 IMC300A iMOTION Controller with additional microcontroller 19 Controller Area Network Controller (MulticanCAN+) object is slave object, too (not possible for gateways). The absolute object numbers of the message objects have no impact on the operation of the FIFO. The base object does not need to be allocated to the same list as the slave objects. Only the slave object must be allocated to a common list (as they are chained together).
Page 556 IMC300A iMOTION Controller with additional microcontroller 19 Controller Area Network Controller (MulticanCAN+) PPREV = f[n-1] PNEXT Slave Object fn PPREV PPREV = f[i-1] PNEXT PNEXT = f[i+1] TOP = fn Slave Object fi CUR = fi BOT = f1 PPREV = f1 Base Object PNEXT = f3 Slave Object f2...
Page 557 IMC300A iMOTION Controller with additional microcontroller 19 Controller Area Network Controller (MulticanCAN+) If bit field MOFCRn.OVIE (“Overflow Interrupt Enable”) of the FIFO base object is set and the current pointer MOFGPRn.CUR becomes equal to MOFGPRn.SEL, a FIFO overflow interrupt request is generated. This interrupt request is generated on interrupt node TXINP of the base object immediately after the storage of the received frame in the slave object.
Page 558 IMC300A iMOTION Controller with additional microcontroller 19 Controller Area Network Controller (MulticanCAN+) If bit MOFCRs.DLCC is set, the data length code MOFCRs.DLC is copied from the gateway source object to the gateway destination object. If bit MOFCRs.IDC is set, the identifier MOARs.ID and the identifier extension MOARs.IDE are copied from the gateway source object to the gateway destination object.
Page 559 IMC300A iMOTION Controller with additional microcontroller 19 Controller Area Network Controller (MulticanCAN+) 19.3.10.8 Foreign Remote Requests When a Remote Frame has been received on a CAN node and is stored in a message object, a transmit request is set to trigger the answer (transmission of a Data Frame) to the request or to automatically issue a secondary request.
Page 560 IMC300A iMOTION Controller with additional microcontroller 19 Controller Area Network Controller (MulticanCAN+) Initialize the CAN nodes Allocate the message objects to the CAN nodes Initialize the message objects Start the CAN nodes Start transmit request for CAN message from node 0 to node 1. Receive message at node 1, Rx interrupt occurs.
Page 561 IMC300A iMOTION Controller with additional microcontroller 19 Controller Area Network Controller (MulticanCAN+) Initialize MO 0 in the message object register MOCTR(CAN_MOCTRz (z = 0-30)) as transmit MO by setting bits [27:25]. Set also MSGVAL[21], that’s the main switch bit of the MO. (Line 18) this line sets the message data length of MO 0 to 8 bytes.(see also message object function control register MOFCR...
Page 562 IMC300A iMOTION Controller with additional microcontroller 19 Controller Area Network Controller (MulticanCAN+) Note: Line 1 does not apply for ARM products, therefore this line does not exist. Initialization of the MultiCAN+ module: // Load global MultiCAN+ registers: CAN_CLC = 0x000; // enable module control dummy = CAN_CLC;...
Page 563 IMC300A iMOTION Controller with additional microcontroller 19 Controller Area Network Controller (MulticanCAN+) MulticanCAN+ Kernel Register Overview The MulticanCAN+ Kernel include three blocks of registers: • Global Module Registers • Node Registers, for each CAN node x • Message Object Registers, for each message object n Global Module CAN Node Message Object...
Page 564 IMC300A iMOTION Controller with additional microcontroller 19 Controller Area Network Controller (MulticanCAN+) Table 232 Registers Overview - MulticanCAN+ Kernel Registers (continued) Short Name Description Offset Addr Access Mode Reset Description Read Write MSPNDk Message Pending 0140 + k × 4 U, PV U, PV Application...
Page 565 IMC300A iMOTION Controller with additional microcontroller 19 Controller Area Network Controller (MulticanCAN+) Table 232 Registers Overview - MulticanCAN+ Kernel Registers (continued) Short Name Description Offset Addr Access Mode Reset Description Read Write MOIPRn Message Object n 1008 + n × 20 U, PV U, PV Application...
Page 566 IMC300A iMOTION Controller with additional microcontroller 19 Controller Area Network Controller (MulticanCAN+) Figure 143 MO = Message Object; n = 0 to (Number of Message Objects -1) = 1000 + n * 20 BASE address + 1C MO n Control Register BASE + 18 MO n Arbitration Reg.
Page 567 IMC300A iMOTION Controller with additional microcontroller 19 Controller Area Network Controller (MulticanCAN+) 19.5.1 Global Module Registers All list operations such as allocation, de-allocation and relocation of message objects within the list structure are performed via the Command Panel. It is not possible to modify the list structure directly by software by writing to the message objects and the LIST registers.
Page 568 IMC300A iMOTION Controller with additional microcontroller 19 Controller Area Network Controller (MulticanCAN+) Field Bits Type Description PANCMD Panel Command This bit field is used to start a new command by writing a panel command code into it. At the end of a panel command, the NOP (no operation) command code is automatically written into PANCMD.
Page 569 IMC300A iMOTION Controller with additional microcontroller 19 Controller Area Network Controller (MulticanCAN+) Table 233 Panel Commands (continued) PANCMD PANAR2 PANAR1 Command Description Result: – Initialize Lists Bit 7: ERR Run the initialization sequence to reset the CTRL and LIST fields of all message objects. List registers Bit 6-0: undefined LIST[7:0] are set to their reset values.
Page 570 IMC300A iMOTION Controller with additional microcontroller 19 Controller Area Network Controller (MulticanCAN+) Table 233 Panel Commands (continued) PANCMD PANAR2 PANAR1 Command Description Argument: Result: Dynamic Insert Before Destination Object Object Number Insert a new message object before a given Number of inserted destination object.
Page 571 IMC300A iMOTION Controller with additional microcontroller 19 Controller Area Network Controller (MulticanCAN+) Address: Module Control Register Reset Value: 0000 0000 MPSEL CLKSEL Field Bits Type Description CLKSEL Baud Rate Logic Clock Select 0000 No clock supplied 0001 MCLK 0010 OSC_HP 0100 hard wired to 0 1000...
Page 572 IMC300A iMOTION Controller with additional microcontroller 19 Controller Area Network Controller (MulticanCAN+) Field Bits Type Description Interrupt Trigger Writing a 1 to IT[m] (m = 0-7) generates an interrupt request on interrupt output line INT_O[m]. Writing a 0 to IT[m] has no effect. Bit field IT is always read as 0.
Page 573 IMC300A iMOTION Controller with additional microcontroller 19 Controller Area Network Controller (MulticanCAN+) (continued) Field Bits Type Description SIZE 23:16 List Size SIZE indicates the number of elements in the list i. SIZE = number of list elements - 1 SIZE = 0 indicates that list i is empty. EMPTY List Empty Indication At least one message object is allocated to list i.
Page 574 IMC300A iMOTION Controller with additional microcontroller 19 Controller Area Network Controller (MulticanCAN+) 19.5.1.6.2 Register MSIDk Each Message Pending Register has a Message Index Register MSIDk associated with it. The Message Index Register shows the active (set) pending bit with lowest bit position within groups of pending bits. MSIDk (k = 0-7) Address: +k*4...
Page 575 IMC300A iMOTION Controller with additional microcontroller 19 Controller Area Network Controller (MulticanCAN+) Field Bits Type Description 31:0 Message Index Mask Only those bits in MSPNDk for which the corresponding Index Mask bits are set contribute to the calculation of the Message Index.
Page 576 IMC300A iMOTION Controller with additional microcontroller 19 Controller Area Network Controller (MulticanCAN+) (continued) Field Bits Type Description TRIE Transfer Interrupt Enable TRIE enables the transfer interrupt of CAN node x. This interrupt is generated after the successful reception or transmission of a CAN frame in node x.
Page 577 IMC300A iMOTION Controller with additional microcontroller 19 Controller Area Network Controller (MulticanCAN+) (continued) Field Bits Type Description CALM CAN Analyzer Mode If this bit is set, then the CAN node operates in Analyzer Mode. This means that messages may be received, but not transmitted. No acknowledge is sent on the CAN bus upon frame reception.
Page 578 IMC300A iMOTION Controller with additional microcontroller 19 Controller Area Network Controller (MulticanCAN+) (continued) Field Bits Type Description ALERT Alert Warning The ALERT bit is set upon the occurrence of one of the following events (the same events which also trigger an alert interrupt if ALIE is set): •...
Page 579 IMC300A iMOTION Controller with additional microcontroller 19 Controller Area Network Controller (MulticanCAN+) Table 234 Encoding of the LEC Bit field (continued) LEC Value Signification Form Error: A fixed format part of a received frame has the wrong format. Ack Error: The transmitted message was not acknowledged by another node.
Page 580 IMC300A iMOTION Controller with additional microcontroller 19 Controller Area Network Controller (MulticanCAN+) Field Bits Type Description ALINP Alert Interrupt Node Pointer ALINP selects the interrupt output line INT_Om (m = 0-7) for an alert interrupt of CAN Node x. 0000 Interrupt output line INT_O0 is selected.
Page 581 IMC300A iMOTION Controller with additional microcontroller 19 Controller Area Network Controller (MulticanCAN+) RXSEL Field Bits Type Description RXSEL Receive Select RXSEL selects one out of 8 possible receive inputs. The CAN receive signal is performed only through the selected input. Note: In IMC300A, only specific combinations of RXSEL are available (see also...
Page 582 IMC300A iMOTION Controller with additional microcontroller 19 Controller Area Network Controller (MulticanCAN+) Field Bits Type Description Baud Rate Prescaler The duration of one time quantum is given by (BRP + 1) clock cycles if DIV8 = 0. The duration of one time quantum is given by 8 × (BRP + 1) clock cycles if DIV8 = 1.
Page 583 IMC300A iMOTION Controller with additional microcontroller 19 Controller Area Network Controller (MulticanCAN+) Field Bits Type Description Receive Error Counter Bit field REC contains the value of the receive error counter of CAN node x. 15:8 Transmit Error Counter Bit field TEC contains the value of the transmit error counter of CAN node x.
Page 584 IMC300A iMOTION Controller with additional microcontroller 19 Controller Area Network Controller (MulticanCAN+) Field Bits Type Description 15:0 CAN Frame Counter In Frame Count Mode (CFMOD = 00 ), this bit field contains the frame count value. In Time Stamp Mode (CFMOD = 01 ), this bit field contains the captured bit time count value, captured with the start of a new frame.
Page 585 IMC300A iMOTION Controller with additional microcontroller 19 Controller Area Network Controller (MulticanCAN+) (continued) Field Bits Type Description CFMOD 20:19 CAN Frame Counter Mode This bit field determines the operation mode of the frame counter. Frame Count Mode: The frame counter is incremented upon the reception and transmission of frames.
Page 586 IMC300A iMOTION Controller with additional microcontroller 19 Controller Area Network Controller (MulticanCAN+) Table 235 Bit Timing Analysis Modes (CFMOD = 10) (continued) CFSEL Measurement With each sample point, the time (measured in clock cycles) between the start of the new bit time and the start of the previous bit time is stored in CFC[11:0].
Page 587 IMC300A iMOTION Controller with additional microcontroller 19 Controller Area Network Controller (MulticanCAN+) SETN SETR SETT SETR SETD SETT SETT SETT SETR SETR XEN1 XEN0 TSEL REST REST REST REST RTSE XEN1 XEN0 Field Bits Type Description RESRXPND Reset Receive Pending This bit controls the reset condition for RXPND (see Table 237).
Page 588 IMC300A iMOTION Controller with additional microcontroller 19 Controller Area Network Controller (MulticanCAN+) (continued) Field Bits Type Description SETNEWDAT Set New Data This bit controls the set condition for NEWDAT (see Table 237). SETMSGLST Set Message Lost This bit controls the set condition for MSGLST (see Table 237).
Page 589 IMC300A iMOTION Controller with additional microcontroller 19 Controller Area Network Controller (MulticanCAN+) CAN_MOSTAT0 Address: 101C Message Object 0 Status Register Reset Value: 0100 0000 CAN_MOSTATn (n = 1-30) Address: (101C +n*20 Message Object n Status Register Reset Value: ((n+1)*01000000 ((n-1)*00010000 CAN_MOSTAT31 Address: 13FC...
Page 590 IMC300A iMOTION Controller with additional microcontroller 19 Controller Area Network Controller (MulticanCAN+) (continued) Field Bits Type Description MSGVAL Message Valid Message object n is not valid. Message object n is valid. Only a valid message object takes part in CAN transfers. RTSEL Receive/Transmit Selected Message object n is not selected for receive or transmit...
Page 591 IMC300A iMOTION Controller with additional microcontroller 19 Controller Area Network Controller (MulticanCAN+) (continued) Field Bits Type Description TXEN0 Transmit Enable 0 Message object n is not enabled for frame transmission. Message object n is enabled for frame transmission. Message object n can be transmitted only if both bits, TXEN0 and TXEN1, are set.
Page 592 IMC300A iMOTION Controller with additional microcontroller 19 Controller Area Network Controller (MulticanCAN+) 19.5.3.3 Register CAN_MOIPRn The Message Object Interrupt Pointer Register MOIPRn holds the message interrupt pointers, the message pending number, and the frame counter value of message object n. CAN_MOIPRn (n = 0-31) Address: 1008...
Page 593 IMC300A iMOTION Controller with additional microcontroller 19 Controller Area Network Controller (MulticanCAN+) CAN_MOFCRn (n = 0-31) Address: 1000 +n*20 Message Object n Function Control Register Reset Value: 0000 0000 FRRE SDT RMM OVIE TXIE RXIE DATC DLCC IDC Field Bits Type Description Message Mode Control...
Page 594 IMC300A iMOTION Controller with additional microcontroller 19 Controller Area Network Controller (MulticanCAN+) (continued) Field Bits Type Description DLCC Data Length Code Copy Data length code is not copied. Data length code of the gateway source object (after storing the received frame in the source) is copied to the gateway destination object.
Page 595 IMC300A iMOTION Controller with additional microcontroller 19 Controller Area Network Controller (MulticanCAN+) (continued) Field Bits Type Description FRREN Foreign Remote Request Enable Specifies whether the TXRQ bit is set in message object n or in a foreign message object referenced by the pointer CUR. TXRQ of message object n is set on reception of a matching Remote Frame.
Page 596 IMC300A iMOTION Controller with additional microcontroller 19 Controller Area Network Controller (MulticanCAN+) Field Bits Type Description Bottom Pointer Bit field BOT points to the first element in a FIFO structure. 15:8 Top Pointer Bit field TOP points to the last element in a FIFO structure. 23:16 Current Object Pointer Bit field CUR points to the actual target object within a FIFO/...
Page 597 IMC300A iMOTION Controller with additional microcontroller 19 Controller Area Network Controller (MulticanCAN+) Field Bits Type Description 28:0 Acceptance Mask for Message Identifier Bit field AM is the 29-bit mask for filtering incoming messages with standard identifiers (AM[28:18]) or extended identifiers (AM[28:0]).
Page 598 IMC300A iMOTION Controller with additional microcontroller 19 Controller Area Network Controller (MulticanCAN+) (continued) Field Bits Type Description 31:30 Priority Class PRI assigns one of the four priority classes 0, 1, 2, 3 to message object n. A lower PRI number defines a higher priority. Message objects with lower PRI value always win acceptance filtering for frame reception and transmission over message objects with higher PRI value.
Page 599 IMC300A iMOTION Controller with additional microcontroller 19 Controller Area Network Controller (MulticanCAN+) Table 239 Transmit Priority of Msg. Objects Based on CAN Arbitration Rules (continued) Settings of Arbitrarily Chosen Message Objects A Comment and B, (A has higher transmit priority than B) A.MOAR[28:0] <...
Page 600 IMC300A iMOTION Controller with additional microcontroller 19 Controller Area Network Controller (MulticanCAN+) Field Bits Type Description Data Byte 4 of Message Object n 15:8 Data Byte 5 of Message Object n 23:16 Data Byte 6 of Message Object n 31:24 Data Byte 7 of Message Object n 19.6 MulticanCAN+ Module Implementation...
Page 601 IMC300A iMOTION Controller with additional microcontroller 19 Controller Area Network Controller (MulticanCAN+) MCLK MultiCAN+ Module Kernel Baud Rate Clock Block Pin x.y Clock MCLK Control TXDCn Node n RXDCn Message (DMA Line Object Linked Router) Buffer List Port Control Control INT_O CCU4 Objects...
Page 602 IMC300A iMOTION Controller with additional microcontroller 19 Controller Area Network Controller (MulticanCAN+) 19.6.3 Module Clock Generation This chapter describes the way the module get’s its clock. 19.6.3.1 Clock Selection The bit timing machine and the rest of the MulticanCAN+ module are separate frequency domains and can be driven by separate independent frequencies.
Page 603 IMC300A iMOTION Controller with additional microcontroller 19 Controller Area Network Controller (MulticanCAN+) × with n = 0‐1023 1024 Equation 26 Equation 25 applies to normal divider mode (CAN_FDR.DM = 01 ) of the fractional divider. Equation 26 applies to fractional divider mode (CAN_FDR.DM = 10 Note: The CAN module is disabled after reset.
Page 604 IMC300A iMOTION Controller with additional microcontroller 19 Controller Area Network Controller (MulticanCAN+) Address: CAN Fractional Divider Register Reset Value: 0000 0000 STEP Field Bits Type Description STEP Step Value Reload or addition value for the result. 15:14 Divider Mode This bit field selects normal divider mode, fractional divider mode, and off-state.
Page 605 IMC300A iMOTION Controller with additional microcontroller 19 Controller Area Network Controller (MulticanCAN+) Table 241 MulticanCAN+ I/O Control Selection and Setup (continued) Node NPCRx.RXSEL P2.0 / RXDE P2.1 / TXD P2.1 / RXDF P2.0 / TXD P1.0 / RXDG P1.1 / TXD P1.1 / RXDH P1.0 / TXD CAN1...
Page 606 IMC300A iMOTION Controller with additional microcontroller 19 Controller Area Network Controller (MulticanCAN+) Table 242 Interrupt Router Inputs Interrupt Router Input Connected to CAN Interrupt Output SRC_CANINT0 INT_O0 SRC_CANINT1 INT_O1 SRC_CANINT2 INT_O2 SRC_CANINT3 INT_O3 SRC_CANINT4 INT_O4 SRC_CANINT5 INT_O5 SRC_CANINT6 INT_O6 SRC_CANINT7 INT_O7 19.6.4.4 Connections to ERU...
Page 607 IMC300A iMOTION Controller with additional microcontroller 19 Controller Area Network Controller (MulticanCAN+) • Each output of the 4-bit interrupt pointer demultiplexer is connected to exactly one OR-gate input of the INT_Om line. The number “m” of the corresponding selected INT_Om interrupt output line is defined by the interrupt pointer value.
Page 608 IMC300A iMOTION Controller with additional microcontroller 19 Controller Area Network Controller (MulticanCAN+) MO = Message Object; n = 0 to (Number of Message Objects -1) = 1000 + n * 20 BASE address + 1C MO n Control Register BASE + 18 MO n Arbitration Reg.
Page 609 IMC300A iMOTION Controller with additional microcontroller 20 Capture/Compare Unit 4 (CCU4) Capture/Compare Unit 4 (CCU4) The CCU4 peripheral is a major component for systems that need general purpose timers for signal monitoring/ conditioning and Pulse Width Modulation (PWM) signal generation. Power electronic control systems like switched mode power supplies or uninterruptible power supplies, can easily be implemented with the functions inside the CCU4 peripheral.
Page 610 IMC300A iMOTION Controller with additional microcontroller 20 Capture/Compare Unit 4 (CCU4) • capture and compare mode for each timer slice four capture registers in capture mode one compare channel in compare mode • programmable low pass filter for the inputs •...
Page 611 IMC300A iMOTION Controller with additional microcontroller 20 Capture/Compare Unit 4 (CCU4) Table 245 Applications summary (continued) Feature Applications Dithering PWM Generating a fractional PWM frequency or duty cycle: • To avoid big steps on frequency or duty cycle adjustment in slow control loop applications •...
Page 612 IMC300A iMOTION Controller with additional microcontroller 20 Capture/Compare Unit 4 (CCU4) CCU4x Module System CCU4x.MCLK clock Prescaler control CCU4x.CLK[C:A] CC40 CCU4x.MCSS Capture Register 3 Output Capture Register 2 (CC40C0V) Functions CCU4x.OUT0 Capture Register 1 (CC40C0V) Capture Register 0 (CC40C0V) Input CCU4x.ST0 (CC40C0V) Address...
Page 613 IMC300A iMOTION Controller with additional microcontroller 20 Capture/Compare Unit 4 (CCU4) CC4yINS.EV0IS · Register GCSS GCSS · Field SyFF from register GCSS GCSS.SyFF · y indicates that multiple fields like this exist, e.g. S0FF, S1FF, etc · Field EV0IS of register CC4yINS controls the multiplexer ·...
Page 614 IMC300A iMOTION Controller with additional microcontroller 20 Capture/Compare Unit 4 (CCU4) Figure 152 CCU4 slice block diagram For more information to the functional blocks see the following links: • Clock Prescaler • Service Request Generation • Timer Slice Input Selector •...
Page 615 IMC300A iMOTION Controller with additional microcontroller 20 Capture/Compare Unit 4 (CCU4) Table 246 CCU4 slice pin description (continued) Description CCU4x.INy[BV:AA] Slice functional inputs (used to control the functionality throughout slice external events) CCU4x.MCIy Multi-Channel mode input CCU4x.MCSS Multi-Channel shadow transfer trigger CC4y.SR[3...0] Slice service request lines CCU4x.GPy[2...0]...
Page 616 IMC300A iMOTION Controller with additional microcontroller 20 Capture/Compare Unit 4 (CCU4) Event 2 Event 1 Event 0 CC4yINS2.EV0EM CC4yINS1.EV0IS for trigger functions CCU4x.INy[AA] CCU4x.INy[AB] Edge Detection Connection Matrix CCU4x.INy[BV] for level functions Level Selection CCU4x.GPy0 CC4yINS2.LPF0M CC4yINS2.EV0LM Figure 153 Slice input selector diagram 20.2.3 Timer Slice Connection Matrix The connection matrix maps the events coming from the input selector to several user configured functions,...
Page 617 IMC300A iMOTION Controller with additional microcontroller 20 Capture/Compare Unit 4 (CCU4) CC4yCMC Override Trigger Override Value Modulation CCyoset TRAP1 CCyoval Start CCymod Count CCytrap1 to Timer Stop Core Logic CCystrt Count Direction CCycnt Load CCystp Gating Function controlled by CCyupd a level Capture 1 CCyload...
Page 618 IMC300A iMOTION Controller with additional microcontroller 20 Capture/Compare Unit 4 (CCU4) Configures how the external start is used CC4yTC.STRM Writing a 1 to this bit will set the CC4yTCST.TRB CC4yTCSET.TRBS Run bit Set CC4yTIMER Control CCystrt CC4yTCST.TRB Stop/Run External start trigger STOP Writing a 1 to this bit will...
Page 619 IMC300A iMOTION Controller with additional microcontroller 20 Capture/Compare Unit 4 (CCU4) CCU4x CC40 CCystrt Common Signal CC41 CCystrt CC42 Other Modules CC43 Figure 156 Starting multiple timers synchronously 20.2.4.2 Counting Modes Introduction Each CC4y timer slice can be programmed into three different counting schemes: •...
Page 620 IMC300A iMOTION Controller with additional microcontroller 20 Capture/Compare Unit 4 (CCU4) 20.2.4.3 Edge Aligned Mode Edge aligned mode is the default counting scheme. In this mode, the timer is incremented until it matches the value programmed in the period register, CC4yPR. When period match is detected the timer is cleared to 0000 and continues to be incremented - Figure 158.
Page 621 IMC300A iMOTION Controller with additional microcontroller 20 Capture/Compare Unit 4 (CCU4) Period value Period value Period value Compare value Zero CC4yPRS value value value CC4yPR value value value CC4yST Figure 160 Edge aligned mode, immediate period value update 20.2.4.4 Center Aligned Mode In center aligned mode, the timer is counting up or down with respect to the following rules: •...
Page 622 IMC300A iMOTION Controller with additional microcontroller 20 Capture/Compare Unit 4 (CCU4) • Within the next clock cycle after the counter reaches the period value, while counting up (CC4yTCST.CDIR = • Within the next clock cycle after the counter reaches 0001 , while counting down (CC4yTCST.CDIR = 1 It is also possible to select in which instant the update is done.
Page 623 IMC300A iMOTION Controller with additional microcontroller 20 Capture/Compare Unit 4 (CCU4) Period value Period value Period value Compare value Zero CC4yPRS value value value CC4yPR value value value CC4yST Figure 163 Center aligned mode, immediate period value update 20.2.4.5 Single Shot Mode In single shot mode, the timer is stopped after the current timer period is finished.
Page 624 IMC300A iMOTION Controller with additional microcontroller 20 Capture/Compare Unit 4 (CCU4) CCTclk Period match Period value CCTimer Compare value One match Zero CDIR CC4yST TSSM Figure 165 Single shot center aligned - CC4yTC.TSSM = 1, CC4yTC.TCM = 1 20.2.4.6 Calculating the PWM Period and Duty Cycle The period of the timer is determined by the value in the period register, CC4yPR and by the timer mode.
Page 625 IMC300A iMOTION Controller with additional microcontroller 20 Capture/Compare Unit 4 (CCU4) Besides these parameters, each timer slice also permits the user to update on-the-fly the floating prescaler, dither and even the passivel level of the PWM signal. The following text descriptions, will give an overview of the registers/parameters that can be updated on-the-fly, and also the options available to control this update.
Page 626 IMC300A iMOTION Controller with additional microcontroller 20 Capture/Compare Unit 4 (CCU4) IDLE GCST.SySS SW/HW request Clear the GCST.SyDSS Enable GCST.SyPSS bit(s) GCST.SySS Set the GCST.SyDSS Enable GCST.SyPSS bit(s) CC4yCR CC4yPR Do the transfer Load Waiting for PWM sync value Wait for CC4yPRS PWM sync CC4yCRS...
Page 627 IMC300A iMOTION Controller with additional microcontroller 20 Capture/Compare Unit 4 (CCU4) Shadow transfer trigger (sync with PWM) & Transfer new values into the CC4yPR CC4ySTC.IRPC Software triggers GCST.SySS Write into & GCSS.SySE Done Transfer new values into the Write into CC4yCR CC4ySTC.IRCC GCSS.SyDSE...
Page 628 IMC300A iMOTION Controller with additional microcontroller 20 Capture/Compare Unit 4 (CCU4) - in the next clock cycle after a Period Match while counting up - center aligned - in the next clock cycle after an One Match while counting down - center aligned and edge aligned - immediately, if the timer is stopped and the shadow transfer enable bit(s) is set - center aligned and edge aligned.
Page 629 IMC300A iMOTION Controller with additional microcontroller 20 Capture/Compare Unit 4 (CCU4) register to perform an immediate update, after the GCSS.SySE is written with 1 , the hardware will automatically load and use the new values. The request bit - SySS - is then cleared when the transfer is done. One should notice that all the depicted CC4ySTC configuration fields need to be set to 1 for the request bit (SySS) to be cleared immediately.
Page 630 IMC300A iMOTION Controller with additional microcontroller 20 Capture/Compare Unit 4 (CCU4) SW writes new values into SW writes new values into CC4yPRS CC4yPRS SW writes new values into SW writes new values into CC4yCRS CC4yCRS CC4yTIMER Value Value Value CC4yCRS Value Value Value...
Page 631 IMC300A iMOTION Controller with additional microcontroller 20 Capture/Compare Unit 4 (CCU4) SW writes new values into CC4yPRS SW writes new values into SW writes new values into SW writes new values into CC4yCRS CC4yCRS CC4yCRS CC4yTIMER Value Value Value Value CC4yCRS Value Value...
Page 632 IMC300A iMOTION Controller with additional microcontroller 20 Capture/Compare Unit 4 (CCU4) CCU4x CC40 Shadow transfer done Shadow CC40 Logic transfer control Shadow transfer enable cc40_trf_enable CC41 Shadow transfer done Shadow Cascaded CC41 Logic transfer control control Shadow transfer enable cc41_trf_enable CC42 Shadow transfer done Shadow...
Page 633 IMC300A iMOTION Controller with additional microcontroller 20 Capture/Compare Unit 4 (CCU4) SW writes new values into SW writes new values into CC40CRS CC40CRS Timer 0 S0SS Shadow trf pulse The end of the previous shadow transfer enables the immediatly next slice shadow transfer SW writes new values into CC41CRS Timer 1...
Page 634 IMC300A iMOTION Controller with additional microcontroller 20 Capture/Compare Unit 4 (CCU4) The general rules that set or clear the associated timer slice status bit (CC4yST), can be generalized independently of the timer counting mode. The following events set the Status bit (CC4yST) to Active: •...
Page 635 IMC300A iMOTION Controller with additional microcontroller 20 Capture/Compare Unit 4 (CCU4) External Multi-Channel TRAP State modulation Mode control control control port port port Set/Clear Control Sync with multi-channel From Active/Passive Rules Set Status bit delay CC4yST CCU4x.OUTy Clear Status bit From External Functions CC4yTC.MCME CC4yPSL.PSL...
Page 636 IMC300A iMOTION Controller with additional microcontroller 20 Capture/Compare Unit 4 (CCU4) Notice that both start and stop functions are edge and not level active and therefore the active/passive configuration is set only by the CC4yINS2.EVxEM. The external stop by default just clears the run bit (CC4yTCST.TRB), while the start functions does the opposite. Nevertheless one can select an extended subset of functions for the external start and stop.
Page 637 IMC300A iMOTION Controller with additional microcontroller 20 Capture/Compare Unit 4 (CCU4) CCyStrt CCyStp CCTclk Period match Period value CCTimer Compare value Zero CC4yST Figure 178 Start (as flush and start)/ stop (as stop) - CC4yTC.STRM = 1, CC4yTC.ENDM = 00 External Signal(1) External...
Page 638 IMC300A iMOTION Controller with additional microcontroller 20 Capture/Compare Unit 4 (CCU4) Note: For a signal that should impose an increment when LOW and a decrement when HIGH, the user needs to set the CC4yINS2.EVxLM = 0 . When the operation is switched, then the user should set CC4yINS2.EVxLM = 1 Note: Using an external counting direction control, sets the slice in edge aligned mode.
Page 639 IMC300A iMOTION Controller with additional microcontroller 20 Capture/Compare Unit 4 (CCU4) External signal Period value CCTimer Compare value Zero CDIR CC4yST Figure 181 External gating For any type of usage of the external gating function, the specific run bit of the Timer Slice, CC4yTCST.TRB, needs to be set.
Page 640 IMC300A iMOTION Controller with additional microcontroller 20 Capture/Compare Unit 4 (CCU4) signal on the CC4yINS2.EVxEM register. This event should be then mapped to the load functionality by setting the CC4yCMC.LDS with the proper value. Notice that the load function is edge active and therefore the active/passive configuration is set only by the CC4yINS2 .EVxEM.
Page 641 IMC300A iMOTION Controller with additional microcontroller 20 Capture/Compare Unit 4 (CCU4) Different Capture Events (SCE = 0 Every time that a capture trigger 1 occurs, CCcapt1, the actual value of the timer is captured into the capture register 3 and the previous value stored in this register is transferred into capture register 2. Every time that a capture trigger 0 occurs, CCcapt0, the actual value of the timer is captured into the capture register 1 and the previous value stored in this register is transferred into capture register 0.
Page 642 IMC300A iMOTION Controller with additional microcontroller 20 Capture/Compare Unit 4 (CCU4) External signal(1) External signal(2) Capture into Capture into Capture into CC4C1V CC4C1V CC4C1V CCycapt0 Capture into Capture into CC4C3V CC4C3V CCycapt1 Full scale as Period CCTimer Zero CC4yC1V CValue CValue CValue CC4yC0V...
Page 643 IMC300A iMOTION Controller with additional microcontroller 20 Capture/Compare Unit 4 (CCU4) CC4yC3V = NOT CC4yC3V AND CC4yC2V AND CC4yC2V AND CC4yC1V capt full_flag full_flag full_flag full_flag Equation 32 CC4yC2V = CC4yC3V AND NOT CC4yC2V AND CC4yC1V AND CC4yC0V capt full_flag full_flag full_flag full_flag...
Page 644 IMC300A iMOTION Controller with additional microcontroller 20 Capture/Compare Unit 4 (CCU4) 20.2.5.7 TRAP Function The TRAP functionality allows the PWM outputs to react on the state of an input pin. This functionality can be used to switch off the power devices if the TRAP input becomes active. To select the TRAP functionality, one should map one of the input signals to event number 2, by setting the required value in the CC4yINS1.EV2IS register and indicating the active level of the signal on the CC4yINS2.EV2LM register.
Page 645 IMC300A iMOTION Controller with additional microcontroller 20 Capture/Compare Unit 4 (CCU4) Timer Compare Value CCytrap TRPS/ If TRPSW = 0 E2AS TRPS/ If TRPSW = 1 E2AS TRPF CCU4x.OUTy TRAP state is automatically exit via HW if TRPSW = 0 SW writes 1 to RE2A clear the TRAP state...
Page 646 IMC300A iMOTION Controller with additional microcontroller 20 Capture/Compare Unit 4 (CCU4) The signal that carries the value to be set on the status bit, needs to be mapped to the event number 2, by setting the required value in the CC4yINS1.EV2IS register. The CC4yINS2.EV2LM register should be set to 0 if no inversion on the signal is needed and to 1 otherwise.
Page 647 IMC300A iMOTION Controller with additional microcontroller 20 Capture/Compare Unit 4 (CCU4) External signal Period value CCTimer Compare value Zero CC4yST/ CCU4x.OUTy Figure 193 External modulation clearing the ST bit - CC4yTC.EMT = 0 External signal Period value CCTimer Compare value Zero Waiting for the CC4yST to go...
Page 648 IMC300A iMOTION Controller with additional microcontroller 20 Capture/Compare Unit 4 (CCU4) 20.2.6 Timer Slice Advanced Functions In the following sub sections several advanced functions present in each CC4y slice are described. One should notice that each of the functions is present and works in the same manner for every CCU4 timer slice. 20.2.6.1 Multi-Channel Control The Multi-Channel control mode is selected individually in each slice by setting the CC4yTC.MCME = 1...
Page 649 IMC300A iMOTION Controller with additional microcontroller 20 Capture/Compare Unit 4 (CCU4) CCU4x.OUT0 CCU4x.OUT2 CCU4x.OUT3 CCU4x.OUT4 Multi channel pattern 1001 1100 0110 Figure 197 Multi-Channel mode for multiple Timer Slices The synchronization between the CCU4 and the module controlling the Multi-Channel pattern is achieved, by adding a 3 cycle delay on the output path of each Timer Slice (between the status bit, CC4yST and the direct control of the output pin).
Page 650 IMC300A iMOTION Controller with additional microcontroller 20 Capture/Compare Unit 4 (CCU4) CC4yCMC.UDS CC4yTC.CDIR CC4yTC.EMT CC4yTC.MCME CC4yTC.EMS Multi-Channel External CC4yMCMI Mode control Timer = 0000 modulation control Timer = Period CCmod Timer = 0001 port port TRAP CC4yINTS.E2AS Set/Clear ccu4 Control CC4yST Set Status bit CCU4x.OUTy...
Page 651 IMC300A iMOTION Controller with additional microcontroller 20 Capture/Compare Unit 4 (CCU4) • one 64 bit timer • one 48 bit timer plus a 16 timer • two 32 bit timers • one 32 bit timer plus two 16 bit timers 05.05.2014 - 12.05.2014 32 bits CC40...
Page 652 IMC300A iMOTION Controller with additional microcontroller 20 Capture/Compare Unit 4 (CCU4) CC4(y-1) Connection Timer Timer Timer logic matrix concat concat Timer link Timer link CC4(y-1) CC4y Timer link Connection Timer Timer CC4y Timer logic matrix concat concat Timer link CC4(y+1) Timer link Timer link CC4(y+1)
Page 653 IMC300A iMOTION Controller with additional microcontroller 20 Capture/Compare Unit 4 (CCU4) CC4(y-1) capture Connection Timer Timer Timer logic matrix concat concat load Timer link 05.05.2014 - 12.05.2014 48 bits CC4y Connection Timer Timer MSBs LSBs Timer logic matrix concat concat CC4(y+1) CC4y CC4(y-1)
Page 654 IMC300A iMOTION Controller with additional microcontroller 20 Capture/Compare Unit 4 (CCU4) period Timer0 compare CC40PM CM40CM period Timer1 compare CC41PM CC41CM Output period match CC41PM is AND gated (concat) Output compare is CC41CM AND gated (concat) CC40.OUT CC41.OUT Figure 203 32 bit concatenation timing diagram Note: The counting direction of the concatenated timer needs to be fixed.
Page 655 IMC300A iMOTION Controller with additional microcontroller 20 Capture/Compare Unit 4 (CCU4) CC4(y-1) capture Connection Timer Timer direction Timer logic matrix concat concat load CC4y CC4yPR & CCcapt1 Comp CCgate & CC4yTIMER Comp Conn. Matrix CCcapt0 Comp & CCload CC4yCR Timer Concat Timer Logic Timer Concat CC4yCMC.TCE = 1...
Page 656 IMC300A iMOTION Controller with additional microcontroller 20 Capture/Compare Unit 4 (CCU4) CC40 Dither control Period match Dither Shadow transfer enable CC40 Dither counter enable Counting enable Dither compare Counting enable CC41 Dither control Dither CC41 Period match enable Dither counter Shadow transfer enable Dither compare Counting enable...
Page 657 IMC300A iMOTION Controller with additional microcontroller 20 Capture/Compare Unit 4 (CCU4) Table 248 Dither bit reverse counter (continued) counter[3] counter[2] counter[1] counter[0] The counter is then compared against a programmed value, CC4yDIT.DCV. If the counter value is smaller than the programmed value, a gating signal is generated that can be used to extend the period, to delay the compare or both (controlled by the CC4yTC.DITHE field, see Table 249 for one clock cycle.
Page 658 IMC300A iMOTION Controller with additional microcontroller 20 Capture/Compare Unit 4 (CCU4) Timer Compare CC4yST Dither counter Figure 207 Dither timing diagram in edge aligned - CC4yTC.DITHE = 01 Timer Compare CC4yST Dither counter Figure 208 Dither timing diagram in edge aligned - CC4yTC.DITHE = 10 Timer Compare CC4yST...
Page 659 IMC300A iMOTION Controller with additional microcontroller 20 Capture/Compare Unit 4 (CCU4) Timer Compare CC4yST Dither counter Figure 210 Dither timing diagram in center aligned - CC4yTC.DITHE = 01 Timer Compare CC4yST Dither counter Figure 211 Dither timing diagram in center aligned - CC4yTC.DITHE = 10 Timer Compare CC4yST...
Page 660 IMC300A iMOTION Controller with additional microcontroller 20 Capture/Compare Unit 4 (CCU4) linked with capture trigger 1). This read back will always return the oldest captured value, enabling an easy software routine implementation for reconstructing the capture data. This function allows the usage of a FIFO structure for each capturing trigger. This relaxes the software read back routine when multiple capture triggers are present, and the software is not fast enough to perform a read operation in each capture event.
Page 661 IMC300A iMOTION Controller with additional microcontroller 20 Capture/Compare Unit 4 (CCU4) After Read Back Capture Event Capture Event CC4yC0V CC4yC0V CC4yC0V Empty Empty Empty CC4yC1V CC4yC1V CC4yC1V Empty Empty Empty CC4yC2V CC4yC2V CC4yC2V 5790 Empty Empty Full CC4yC3V 8845 CC4yC3V 5790 CC4yC3V 8845...
Page 662 IMC300A iMOTION Controller with additional microcontroller 20 Capture/Compare Unit 4 (CCU4) 05.05.2014 - 12.05.2014 Depth-2 FIFO x 2 CCycapt1 shift empty empty full full Capture register 3 Capture register 2 CC4yC3V CC4yC2V capture Oldest Captured Value from CC4yC3v, CC4yC2V CC4yECRD1 FIFO CC4yTIMER State Machine...
Page 663 IMC300A iMOTION Controller with additional microcontroller 20 Capture/Compare Unit 4 (CCU4) the prescaler is cleared one clock cycle after the clear of the run bit of the selected slice. To select which slice can perform this action, one should program the GCTRL.PRBC register. 20.2.7.1 Normal Prescaler Mode In Normal prescaler mode the clock fed to the CC4y counter is a normal fixed division by N, accordingly to the...
Page 664 IMC300A iMOTION Controller with additional microcontroller 20 Capture/Compare Unit 4 (CCU4) The shadow transfer of the floating prescaler compare value, CC4yFPC.PCMP, is done following the same rules described on Chapter 20.2.4.7. input CCU4 TCLK prescaler clock prescaler mode next prescaler factor counter control first...
Page 665 IMC300A iMOTION Controller with additional microcontroller 20 Capture/Compare Unit 4 (CCU4) 20.2.8 CCU4 Usage 20.2.8.1 PWM Signal Generation The CCU4 offers a very flexible range in duty cycle configurations. This range is comprised between 0 to 100%. To generate a PWM signal with a 100% duty cycle in Edge Aligned Mode, one should program the compare value, CC4yCR.CR, to 0000 , see Figure...
Page 666 IMC300A iMOTION Controller with additional microcontroller 20 Capture/Compare Unit 4 (CCU4) CCTclk Period Value = Compare (FS) Compare = Period+1 Period Value CCTimer Zero CDIR CC4yST 0% duty cycle Duty cycle = 1/Period Figure 221 PWM with 0% duty cycle - Edge Aligned Mode CCTclk Compare Period value...
Page 667 IMC300A iMOTION Controller with additional microcontroller 20 Capture/Compare Unit 4 (CCU4) tclk Capture event Capture event CCTimer CCPM Increments Increments Increments Increments PVAL PSIV PSIV + 1 PSIV + 2 PSIV PSIV + 1 PSIV + 2 PSIV T x 2 <Timer_value>...
Page 668 IMC300A iMOTION Controller with additional microcontroller 20 Capture/Compare Unit 4 (CCU4) tclk CCTimer CCCMU Compare Correct match Compare match CCZM Increments Sets the PSIV Increments PVAL PSIV PSIV + 1 PSIV PSIV + 1 PSIV + 1 PCMP T x 2 Figure 225 Floating Prescaler compare mode usage - Center Aligned 20.2.8.3...
Page 669 IMC300A iMOTION Controller with additional microcontroller 20 Capture/Compare Unit 4 (CCU4) Table 251 Bit reverse distribution (continued) Dither counter 0 The bit reverse distribution versus the programmed CC4yDIT.DCV value results in the following values for the Period and duty cycle: DITHE = 01 Period = 16 −...
Page 670 IMC300A iMOTION Controller with additional microcontroller 20 Capture/Compare Unit 4 (CCU4) Period = T; in Center Aligned Mode Equation 43 Duty cycle = 16 − DCV × d/T + DCV × d − 1 /T /16; in Center Aligned Mode Equation 44 DITHE = 11 Period = 16 −...
Page 671 IMC300A iMOTION Controller with additional microcontroller 20 Capture/Compare Unit 4 (CCU4) In the case that the Floating Prescaler Mode is being used, the actual value of the clock division is also stored in the capture register (CC4yCxV). Figure 226 shows an example of how the capture/transfer may be used in a Timer Slice that is using a external signal as count function (to measure the velocity of a rotating device), and an equidistant capture trigger that is used to dictate the timestamp for the velocity calculation (two Timer waveforms are plotted, one that exemplifies the clearing of the timer in each capture event and another without the clearing function active).
Page 672 IMC300A iMOTION Controller with additional microcontroller 20 Capture/Compare Unit 4 (CCU4) Profile read window 1 ms 500 us 500 us CC40Timer CC40ST CC41Timer CC41C3V CC41C3V full SW read SW read CC41C2V CC41C2V full SW read SW read CC41C1V CC41C1V full SW read SW read CC41C0V...
Page 673 IMC300A iMOTION Controller with additional microcontroller 20 Capture/Compare Unit 4 (CCU4) CCU4x data CC40 Channel X CMP 1 - capture for CMP 1 Extended read register ECRD CMP 1 buffer CC41 - timestamp read back for SW Figure 228 High dynamics capturing with software controlled timestamp In this scenario, the software/CPU will read back the complete set of capture registers (2 or 4 depending on the chosen configuration), every time that an interrupt is triggered from the timestamp timer (the periodicity of this timer can also be adjusted on-the-fly).
Page 674 IMC300A iMOTION Controller with additional microcontroller 20 Capture/Compare Unit 4 (CCU4) CCU4x CMP 1 buffer CMP 1 CC40 ECRD1 - capture for CMP 1 CMP 2 buffer OSC 1 buffer CC41 ECRD1 -capture for CMP 2 CMP 2 CC42 ECRD1 -capture for OSC 1 Channel X CC43...
Page 675 IMC300A iMOTION Controller with additional microcontroller 20 Capture/Compare Unit 4 (CCU4) Read Back Read Back Read Back Timer 2 previous data Timer 2 previous data Timer 2 previous data Previous Previous Previous Timer 2 previous data Timer 2 previous data Timer 2 previous data Previous Previous...
Page 676 IMC300A iMOTION Controller with additional microcontroller 20 Capture/Compare Unit 4 (CCU4) The interrupt sources for the external events are directly linked with the configuration set on the CC4yINS2.EVxEM. If an event is programmed to be active on both edges, that means that service request pulse is going to be generated when any transition on the external signal is detected.
Page 677 IMC300A iMOTION Controller with additional microcontroller 20 Capture/Compare Unit 4 (CCU4) Node pointer 1 Service request source 1 CC4ySR0 From other 1 sources Service request source 2 CC4ySR1 From other 1 Service request sources source 3 CC4ySR2 Service request 1 From other sources source 4...
Page 678 IMC300A iMOTION Controller with additional microcontroller 20 Capture/Compare Unit 4 (CCU4) 20.5 Power, Reset and Clock The following sections describe the operating conditions, characteristics and timing requirements for the CCU4. All the timing information is related to the module clock, f ccu4 20.5.1 Clocks...
Page 679 IMC300A iMOTION Controller with additional microcontroller 20 Capture/Compare Unit 4 (CCU4) Step: Enable the CCU4 clock via the specific SCU register, CGATCLR0. Step: Enable the prescaler block, by writing 1 to the GIDLC.SPRB field. Step: Configure the global CCU4 register GCTRL Step: Configure all the registers related to the required Timer Slice(s) functions, including the interrupt/service...
Page 680 IMC300A iMOTION Controller with additional microcontroller 20 Capture/Compare Unit 4 (CCU4) Table 254 Registers Address Space (continued) Module Base Address End Address Note CCU41 48044000 48047FFF CCU4x CC43 Global registers GCTRL CC42 GSTAT CC41 GIDLS GIDLC CC40 GCSS Control registers Data registers Interrupt registers GCSC...
Page 681 IMC300A iMOTION Controller with additional microcontroller 20 Capture/Compare Unit 4 (CCU4) Table 255 Register Overview of CCU4 (continued) Short Name Description Offset Access Mode Description see Addr. Read Write MIDR Module Identification Register 0080 U, PV Page CC4y Registers, y = 0...3, n = y + 1 CC4yINS1 Input Selector Unit Configuration 0nD8...
Page 682 IMC300A iMOTION Controller with additional microcontroller 20 Capture/Compare Unit 4 (CCU4) 20.7.1 Global Registers 20.7.1.1 Register GCTRL The register contains the global configuration fields that affect all the timer slices inside CCU4. GCTRL Address: 0000 Global Control Register Reset Value: 00000000 MSDE SUSCFG...
Page 683 IMC300A iMOTION Controller with additional microcontroller 20 Capture/Compare Unit 4 (CCU4) (continued) Field Bits Type Description MSE0 Slice 0 Multi-Channel shadow transfer enable When this field is set, a shadow transfer of slice 0 can be requested not only by SW but also via the CCU4x.MCSS input. Shadow transfer can only be requested by SW Shadow transfer can be requested via SW and via the CCU4x.MCSS input.
Page 684 IMC300A iMOTION Controller with additional microcontroller 20 Capture/Compare Unit 4 (CCU4) Field Bits Type Description CC40 IDLE status This bit indicates if the CC40 slice is in IDLE mode or not. In IDLE mode the clocks for the CC40 slice are stopped. Running Idle CC41 IDLE status...
Page 685 IMC300A iMOTION Controller with additional microcontroller 20 Capture/Compare Unit 4 (CCU4) PSIC SS3I SS2I SS1I SS0I Field Bits Type Description SS0I CC40 IDLE mode set Writing a 1 to this bit sets the CC40 slice in IDLE mode. The clocks for the slice are stopped when in IDLE mode. When entering IDLE, the internal slice registers are not cleared.
Page 686 IMC300A iMOTION Controller with additional microcontroller 20 Capture/Compare Unit 4 (CCU4) GIDLC Address: 000C Global Idle Clear Reset Value: 00000000 CS3I CS2I CS1I CS0I Field Bits Type Description CS0I CC40 IDLE mode clear Writing a 1 to this bit removes the CC40 from IDLE mode. A read access always returns 0.
Page 687 IMC300A iMOTION Controller with additional microcontroller 20 Capture/Compare Unit 4 (CCU4) S3ST S2ST S1ST S0ST S3PS S3DS S2PS S2DS S1PS S1DS S0PS S0DS S3SE S2SE S1SE S0SE Field Bits Type Description S0SE Slice 0 shadow transfer set enable Writing a 1 to this bit will set the GCST.S0SS field, enabling then a shadow transfer for the Period, Compare and Passive level values.
Page 688 IMC300A iMOTION Controller with additional microcontroller 20 Capture/Compare Unit 4 (CCU4) (continued) Field Bits Type Description S2PSE Slice 2 Prescaler shadow transfer set enable Writing a 1 to this bit will set the GCST.S2PSS field, enabling then a shadow transfer for the prescaler compare value. A read always returns 0.
Page 689 IMC300A iMOTION Controller with additional microcontroller 20 Capture/Compare Unit 4 (CCU4) S3ST S2ST S1ST S0ST S3PS S3DS S2PS S2DS S1PS S1DS S0PS S0DS S3SC S2SC S1SC S0SC Field Bits Type Description S0SC Slice 0 shadow transfer clear Writing a 1 to this bit will clear the GCST.S0SS field, canceling any pending shadow transfer for the Period, Compare and Passive level values.
Page 690 IMC300A iMOTION Controller with additional microcontroller 20 Capture/Compare Unit 4 (CCU4) (continued) Field Bits Type Description S2PSC Slice 2 Prescaler shadow transfer clear Writing a 1 to this bit will clear the GCST.S2PSS field, canceling any pending shadow transfer for the prescaler compare value. A read always returns 0.
Page 691 IMC300A iMOTION Controller with additional microcontroller 20 Capture/Compare Unit 4 (CCU4) CC43 CC42 CC41 CC40 S3PS S3DS S2PS S2DS S1PS S1DS S0PS S0DS S3SS S2SS S1SS S0SS Field Bits Type Description S0SS Slice 0 shadow transfer status Shadow transfer has not been requested Shadow transfer has been requested This field is cleared by HW after the requested shadow transfer has been executed.
Page 692 IMC300A iMOTION Controller with additional microcontroller 20 Capture/Compare Unit 4 (CCU4) (continued) Field Bits Type Description S2SS Slice 2 shadow transfer status Shadow transfer has not been requested Shadow transfer has been requested This field is cleared by HW after the requested shadow transfer has been executed.
Page 693 IMC300A iMOTION Controller with additional microcontroller 20 Capture/Compare Unit 4 (CCU4) MODN MODT MODR Field Bits Type Description MODR Module Revision This bit field indicates the revision number of the module implementation (depending on the design step). The given value of 00 is a placeholder for the actual number.
Page 694 IMC300A iMOTION Controller with additional microcontroller 20 Capture/Compare Unit 4 (CCU4) Field Bits Type Description EV0IS Event 0 signal selection This field selects which pins is used for the event 0. 000000 CCU4x.INyAA 000001 CCU4x.INyAB 000010 CCU4x.INyAC 000011 CCU4x.INyAD 011001 CCU4x.INyAZ 011010 CCU4x.INyBA...
Page 695 IMC300A iMOTION Controller with additional microcontroller 20 Capture/Compare Unit 4 (CCU4) (continued) Field Bits Type Description EV0LM Event 0 Level Selection Active on HIGH level Active on LOW level EV1EM Event 1 Edge Selection Same as EV0EM description EV1LM Event 1 Level Selection Same as EV0LM description EV2EM Event 2 Edge Selection...
Page 696 IMC300A iMOTION Controller with additional microcontroller 20 Capture/Compare Unit 4 (CCU4) Field Bits Type Description STRTS External Start Functionality Selector Selects the Event that is going to be linked with the external start functionality. External Start Function deactivated External Start Function triggered by Event 0 External Start Function triggered by Event 1 External Start Function triggered by Event 2 ENDS...
Page 697 IMC300A iMOTION Controller with additional microcontroller 20 Capture/Compare Unit 4 (CCU4) (continued) Field Bits Type Description 13:12 External Timer Load Functionality Selector Selects the Event that is going to be linked with the timer load function. - External Load Function deactivated - External Load Function triggered by Event 0 - External Load Function triggered by Event 1 - External Load Function triggered by Event 2...
Page 698 IMC300A iMOTION Controller with additional microcontroller 20 Capture/Compare Unit 4 (CCU4) 20.7.2.4 Register CC4yTCST The register holds the status of the timer (running/stopped) and the information about the counting direction (up/down). CC4yTCST (y=0-3) Address: 0108 + 0100 Slice Timer Status Reset Value: 00000000 CDIR TRB...
Page 699 IMC300A iMOTION Controller with additional microcontroller 20 Capture/Compare Unit 4 (CCU4) Field Bits Type Description TRBS Timer Run Bit set Writing a 1 into this field sets the run bit of the timer. Read always returns 0. 31:1 Reserved Read always returns 0 20.7.2.6 Register CC4yTCCLR Through this register it is possible to stop and clear the timer, and clearing also the dither counter.
Page 700 IMC300A iMOTION Controller with additional microcontroller 20 Capture/Compare Unit 4 (CCU4) TRPS TRPS EMT EMS DITHE ENDM CAPC CLST Field Bits Type Description Timer Counting Mode This field controls the actual counting scheme of the timer. Edge aligned mode Center aligned mode Note: When using an external signal to control the counting direction, the counting scheme is always edge...
Page 701 IMC300A iMOTION Controller with additional microcontroller 20 Capture/Compare Unit 4 (CCU4) (continued) Field Bits Type Description CAPC Clear on Capture Control Timer is never cleared on a capture event Timer is cleared on a capture event into capture registers 2 and 3.
Page 702 IMC300A iMOTION Controller with additional microcontroller 20 Capture/Compare Unit 4 (CCU4) (continued) Field Bits Type Description DITHE 14:13 Dither Enable This field controls the dither mode for the slice. See Chapter 20.2.6.3. Dither is disabled Dither is applied to the Period Dither is applied to the Compare Dither is applied to the Period and Compare Dither input selector...
Page 703 IMC300A iMOTION Controller with additional microcontroller 20 Capture/Compare Unit 4 (CCU4) (continued) Field Bits Type Description External Modulation Type This field selects if the external modulation event is clearing the CC4yST bit or if is gating the outputs. External Modulation functionality is clearing the CC4yST bit. External Modulation functionality is gating the outputs.
Page 704 IMC300A iMOTION Controller with additional microcontroller 20 Capture/Compare Unit 4 (CCU4) DCNT Field Bits Type Description Dither compare Value This field contains the value used for the dither comparison. This value is updated when a shadow transfer occurs with the CC4yDITS.DCVS.
Page 705 IMC300A iMOTION Controller with additional microcontroller 20 Capture/Compare Unit 4 (CCU4) PSIV Field Bits Type Description PSIV Prescaler Initial Value This field contains the value that is applied to the Prescaler at startup. When floating prescaler mode is used, this value is applied when a timer compare match AND prescaler compare match occurs or when a capture event is triggered.
Page 706 IMC300A iMOTION Controller with additional microcontroller 20 Capture/Compare Unit 4 (CCU4) 20.7.2.13 Register CC4yFPCS This register contains the value that is going to be transferred to the CC4yFPC. PCMP field within the next shadow transfer update. CC4yFPCS (y=0-3) Address: 012C + 0100 Floating Prescaler Shadow Reset Value:...
Page 707 IMC300A iMOTION Controller with additional microcontroller 20 Capture/Compare Unit 4 (CCU4) (continued) Field Bits Type Description 31:16 Reserved A read always returns 0. 20.7.2.15 Register CC4yPRS This register contains the value for the timer period that is going to be transferred into the CC4yPR.PR field when the next shadow transfer occurs.
Page 708 IMC300A iMOTION Controller with additional microcontroller 20 Capture/Compare Unit 4 (CCU4) Field Bits Type Description 15:0 Compare Register Contains the value for the timer comparison. Note: In Capture Mode when a external signal is selected for capturing the timer value into the capture registers 0 and 1, a read always returns 0.
Page 709 IMC300A iMOTION Controller with additional microcontroller 20 Capture/Compare Unit 4 (CCU4) TVAL Field Bits Type Description TVAL 15:0 Timer Value This field contains the actual value of the timer. A write access is only possible when the timer is stopped. 31:16 Reserved A read access always returns 0...
Page 710 IMC300A iMOTION Controller with additional microcontroller 20 Capture/Compare Unit 4 (CCU4) (continued) Field Bits Type Description 31:21 Reserved A read always returns 0 20.7.2.20 Register CC4yC1V This register contains the values associated with the Capture 1 field. CC4yC1V (y=0-3) Address: 0178 + 0100 Capture Register 1...
Page 711 IMC300A iMOTION Controller with additional microcontroller 20 Capture/Compare Unit 4 (CCU4) FPCV CAPTV Field Bits Type Description CAPTV 15:0 Capture Value This field contains the capture register 2 value. See Figure 188. In compare mode a read access always returns 0. FPCV 19:16 Prescaler Value...
Page 712 IMC300A iMOTION Controller with additional microcontroller 20 Capture/Compare Unit 4 (CCU4) (continued) Field Bits Type Description FPCV 19:16 Prescaler Value This field contains the prescaler value at the time of the capture event into the capture register 3. In compare mode a read access always returns 0. Full Flag This bit indicates if a new value was capture into the capture register 3 after the last read access.
Page 713 IMC300A iMOTION Controller with additional microcontroller 20 Capture/Compare Unit 4 (CCU4) (continued) Field Bits Type Description E0AS Event 0 Detection Status Depending on the user selection on the CC4yINS2.EV0EM, this bit can be set when a rising, falling or both transitions are detected. Event 0 not detected Event 0 detected E1AS...
Page 714 IMC300A iMOTION Controller with additional microcontroller 20 Capture/Compare Unit 4 (CCU4) Field Bits Type Description Period match while counting up enable Setting this bit to 1 enables the generation of an interrupt pulse every time a period match while counting up occurs. Period Match interrupt is disabled Period Match interrupt is enabled One match while counting down enable...
Page 715 IMC300A iMOTION Controller with additional microcontroller 20 Capture/Compare Unit 4 (CCU4) E2SR E1SR E0SR CMSR POSR Field Bits Type Description POSR Period/One match Service request selector This field selects to which slice Service request line, the interrupt(s) generated by the Period match while counting up and One match while counting down are going to be forward.
Page 716 IMC300A iMOTION Controller with additional microcontroller 20 Capture/Compare Unit 4 (CCU4) (continued) Field Bits Type Description E2SR 13:12 Event 2 Service request selector This field selects to which slice Service request line, the interrupt generated by the Event 2 detection is going to be forward. Forward to CC4ySR0 Forward to CC4ySR1 Forward to CC4ySR2...
Page 717 IMC300A iMOTION Controller with additional microcontroller 20 Capture/Compare Unit 4 (CCU4) (continued) Field Bits Type Description SE0A Event 0 detection set Writing a 1 into this bit sets the CC4yINTS.E0AS bit. An interrupt pulse is generated if the source is enabled. A read always returns SE1A Event 1 detection set Writing a 1...
Page 718 IMC300A iMOTION Controller with additional microcontroller 20 Capture/Compare Unit 4 (CCU4) (continued) Field Bits Type Description RCMD Compare match while counting down clear Writing a 1 into this bit clears the CC4yINTS.CMDS bit. A read always returns 0. RE0A Event 0 detection clear Writing a 1 into this bit clears the CC4yINTS.E0AS bit.
Page 719 IMC300A iMOTION Controller with additional microcontroller 20 Capture/Compare Unit 4 (CCU4) (continued) Field Bits Type Description Shadow transfer mode Shadow transfer is done in Period Match and One match. Shadow transfer is done only in Period Match. Shadow transfer is done only in One Match. Reserved Note: This field only has effect if the timer is in Center...
Page 720 IMC300A iMOTION Controller with additional microcontroller 20 Capture/Compare Unit 4 (CCU4) (continued) Field Bits Type Description ASCC Automatic Shadow transfer request when writing into Compare Shadow Register Writing into Compare Shadow register does not automatically requests a shadow transfer Writing into Compare Shadow register automatically requests a shadow transfer Note: When enabled, the request is going to be triggered for...
Page 721 IMC300A iMOTION Controller with additional microcontroller 20 Capture/Compare Unit 4 (CCU4) CC4yECRD0 (y=0-3) Address: 01B8 + 0100 Extended Read Back 0 Reset Value: 00000000 VPTR SPTR FPCV CAPV Field Bits Type Description CAPV 15:0 Timer Capture Value This field contains the timer captured value FPCV 19:16 Prescaler Capture value...
Page 722 IMC300A iMOTION Controller with additional microcontroller 20 Capture/Compare Unit 4 (CCU4) (continued) Field Bits Type Description 31:26 Reserved Read always returns 0 20.7.2.30 Register CC4yECRD1 Through this register it is possible to read back the FIFO structure of the capture function that is linked with the capture trigger 1.
Page 723 IMC300A iMOTION Controller with additional microcontroller 20 Capture/Compare Unit 4 (CCU4) (continued) Field Bits Type Description Lost Capture Value This field indicates if between two reads of the ECRD0 a capture trigger occured while the FIFO structure was full. If a capture trigger occured between two reads than a capture value was lost.
Page 724 IMC300A iMOTION Controller with additional microcontroller 20 Capture/Compare Unit 4 (CCU4) Table 257 CCU40 - CC40 Pin Connections (continued) Input/Output Connected To Description CCU40.IN0AC General purpose function CCU40.IN0AD ERU0.PDOUT1 General purpose function CCU40.IN0AE General purpose function CCU40.IN0AF General purpose function CCU40.IN0AG General purpose function CCU40.IN0AH...
Page 725 IMC300A iMOTION Controller with additional microcontroller 20 Capture/Compare Unit 4 (CCU4) Table 257 CCU40 - CC40 Pin Connections (continued) Input/Output Connected To Description CCU40.IN0BK Reserved CCU40.IN0BL Reserved CCU40.IN0BM Reserved CCU40.IN0BN Reserved CCU40.IN0BO Reserved CCU40.IN0BP Reserved CCU40.IN0BQ Reserved CCU40.IN0BR Reserved CCU40.IN0BS Reserved CCU40.IN0BT Reserved...
Page 726 IMC300A iMOTION Controller with additional microcontroller 20 Capture/Compare Unit 4 (CCU4) Table 258 CCU40 - CC41 Pin Connections (continued) Input/Output Connected To Description CCU40.IN1AJ ERU0.PDOUT1 General purpose function CCU40.IN1AK ERU0.IOUT1 General purpose function CCU40.IN1AL USIC0_CH1.DX2INS General purpose function CCU40.IN1AM CCU40.GP20 General purpose function CCU40.IN1AN CCU40.ST0...
Page 727 IMC300A iMOTION Controller with additional microcontroller 20 Capture/Compare Unit 4 (CCU4) Table 258 CCU40 - CC41 Pin Connections (continued) Input/Output Connected To Description CCU40.IN1BR Reserved CCU40.IN1BS Reserved CCU40.IN1BT Reserved CCU40.IN1BU Reserved CCU40.IN1BV Reserved CCU40.MCI1 DAC0.OUT3 Multi Channel pattern input CCU40.OUT1 P1.1;...
Page 728 IMC300A iMOTION Controller with additional microcontroller 20 Capture/Compare Unit 4 (CCU4) Table 259 CCU40 - CC42 Pin Connections (continued) Input/Output Connected To Description CCU40.IN2AQ DAC0.OUT4 General purpose function CCU40.IN2AR ACMP2.OUT General purpose function CCU40.IN2AS ACMP1.OUT General purpose function CCU40.IN2AT CCU40.SR1 General purpose function CCU40.IN2AU CCU40.ST2...
Page 729 IMC300A iMOTION Controller with additional microcontroller 20 Capture/Compare Unit 4 (CCU4) Table 259 CCU40 - CC42 Pin Connections (continued) Input/Output Connected To Description CCU40.OUT2 P0.8; P2.10; P4.2; P2.8.HW1 Slice compare output pull control; P2.10.HW1 direction control; CCU40.GP20 CCU40.IN1AM Selected signal for event 0 CCU40.GP21 not connected Selected signal for event 1...
Page 730 IMC300A iMOTION Controller with additional microcontroller 20 Capture/Compare Unit 4 (CCU4) Table 260 CCU40 - CC43 Pin Connections (continued) Input/Output Connected To Description CCU40.IN3AV General purpose function CCU40.IN3AW ERU1.PDOUT3 General purpose function CCU40.IN3AX ERU1.IOUT3 General purpose function CCU40.IN3AY ERU1.PDOUT2 General purpose function CCU40.IN3AZ DAC0.OUT1 General purpose function...
Page 731 IMC300A iMOTION Controller with additional microcontroller 20 Capture/Compare Unit 4 (CCU4) Table 260 CCU40 - CC43 Pin Connections (continued) Input/Output Connected To Description CCU40.ST3 CCU40.IN0AP; CCU40.IN1AP; Slice status bit CCU40.IN2AP; CCU40.IN3AU; CCU41.IN3AL; ; ERU1.3B0; CCU40.PS3 not connected Multi channel pattern sync trigger: PM when counting UP (edge aligned) or OM when counting DOWN (center aligned) 20.8.2...
Page 732 IMC300A iMOTION Controller with additional microcontroller 20 Capture/Compare Unit 4 (CCU4) Table 262 CCU41 - CC40 Pin Connections (continued) Input/Output Connected To Description CCU41.IN0AJ ERU0.PDOUT0 General purpose function CCU41.IN0AK ERU0.IOUT0 General purpose function CCU41.IN0AL CCU40.ST0 General purpose function CCU41.IN0AM CCU41.GP10 General purpose function CCU41.IN0AN CCU41.ST1...
Page 733 IMC300A iMOTION Controller with additional microcontroller 20 Capture/Compare Unit 4 (CCU4) Table 262 CCU41 - CC40 Pin Connections (continued) Input/Output Connected To Description CCU41.IN0BR Reserved CCU41.IN0BS Reserved CCU41.IN0BT Reserved CCU41.IN0BU Reserved CCU41.IN0BV Reserved CCU41.MCI0 DAC0.OUT0 Multi Channel pattern input CCU41.OUT0 P4.0;...
Page 734 IMC300A iMOTION Controller with additional microcontroller 20 Capture/Compare Unit 4 (CCU4) Table 263 CCU41 - CC41 Pin Connections (continued) Input/Output Connected To Description CCU41.IN1AQ DAC0.OUT1 General purpose function CCU41.IN1AR ACMP3.>ACMP3.OUT General purpose function CCU41.IN1AS ACMP2.OUT General purpose function CCU41.IN1AT CCU41.SR2 General purpose function CCU41.IN1AU CCU41.ST1...
Page 735 IMC300A iMOTION Controller with additional microcontroller 20 Capture/Compare Unit 4 (CCU4) Table 263 CCU41 - CC41 Pin Connections (continued) Input/Output Connected To Description CCU41.GP10 CCU41.IN0AM Selected signal for event 0 CCU41.GP11 not connected Selected signal for event 1 CCU41.GP12 Selected signal for event 2 CCU41.ST1 CCU41.IN0AN;...
Page 736 IMC300A iMOTION Controller with additional microcontroller 20 Capture/Compare Unit 4 (CCU4) Table 264 CCU41 - CC42 Pin Connections (continued) Input/Output Connected To Description CCU41.IN2AX ERU1.IOUT2 General purpose function CCU41.IN2AY ERU1.PDOUT3 General purpose function CCU41.IN2AZ DAC0.OUT7 General purpose function CCU41.IN2BA General purpose function CCU41.IN2BB CCU41.SR2 General purpose function...
Page 737 IMC300A iMOTION Controller with additional microcontroller 20 Capture/Compare Unit 4 (CCU4) Table 264 CCU41 - CC42 Pin Connections (continued) Input/Output Connected To Description CCU41.PS0 not connected Multi channel pattern sync trigger: PM when counting UP (edge aligned) or OM when counting DOWN (center aligned) Table 265 CCU41 - CC43 Pin Connections Input/Output...
Page 738 IMC300A iMOTION Controller with additional microcontroller 20 Capture/Compare Unit 4 (CCU4) Table 265 CCU41 - CC43 Pin Connections (continued) Input/Output Connected To Description CCU41.IN3BD POSIF1.OUT1 General purpose function CCU41.IN3BE Reserved CCU41.IN3BF Reserved CCU41.IN3BG Reserved CCU41.IN3BH Reserved CCU41.IN3BI Reserved CCU41.IN3BJ Reserved CCU41.IN3BK Reserved CCU41.IN3BL...
Page 739 IMC300A iMOTION Controller with additional microcontroller 21 Position Interface Unit (POSIF) Position Interface Unit (POSIF) The POSIF unit is a flexible and powerful component for motor control systems that use Rotary Encoders or Hall Sensors as feedback loop. The several configuration schemes of the module, target a very large universe of motor control application requirements.
Page 740 IMC300A iMOTION Controller with additional microcontroller 21 Position Interface Unit (POSIF) • Hall Sensor Mode Simple build-in mode for brushless DC motor control Shadow register for the multi-channel pattern Complete synchronization with the PWM signals and the multi-channel pattern update interrupt sources for Correct Hall Event detection, Wrong Hall Event Detection •...
Page 741 IMC300A iMOTION Controller with additional microcontroller 21 Position Interface Unit (POSIF) 21.1.2 Block Diagram Each POSIF module can operate in three different modes, Quadrature Decoder, Hall Sensor and stand-alone Multi-channel Mode. To complete the control/measurement loop of all these three modes, the POSIF needs to be linked with a CCU4/CCU8 module.
Page 742 IMC300A iMOTION Controller with additional microcontroller 21 Position Interface Unit (POSIF) 21.2.1 Overview The POSIF module contains a function selector unit, that is used in parallel by both Quadrature Decoder and Hall Sensor Control units. This block selects which input signals should be decoded for each control unit. The function selector is also decoding the outputs coming from these two modes (Quadrature and Hall Sensor Mode).
Page 743 IMC300A iMOTION Controller with additional microcontroller 21 Position Interface Unit (POSIF) Table 268 POSIF slice pin description (continued) Hall Sensor Mode Quadrature Decoder Multi-Channel Mode Mode (stand-alone) POSIFx.OUT6 Multi Pattern sync Not used Multi Pattern sync trigger trigger POSIFx.MOUT[15:0] Multi-Channel pattern Not used Multi-Channel pattern POSIFx.SR0 Service request line 0...
Page 744 IMC300A iMOTION Controller with additional microcontroller 21 Position Interface Unit (POSIF) PCONF.INSEL2 PCONF.INSEL1 PCONF.INSEL0 PCONF.FSEL POSIFx.IN0A Phase A/ & Clock POSIFx.IN0B QCLK POSI0 Quadrature decoder POSIFx.IN0C Direction Phase B/ control PCLK & POSIFx.IN0D Direction POSIFx.OUT0 Clear/Capt POSIFx.IN1A Index Index POSIFx.OUT1 &...
Page 745 IMC300A iMOTION Controller with additional microcontroller 21 Position Interface Unit (POSIF) Transition on the Hall Inputs Hall input 1 PIFHI_E POSIFx.OUT0 Hall input 2 Hall input 3 HALPS.HCPS HALPS.HEPS PCONF.DSEL POSIFx.HSDA PIFHSDLY PIFHSP HALP.HCP HALP.HEP Sample POSIFx.HSDB Correct Hall Event Delay between the transition PCONF.SPES PIFHSPAT...
Page 746 IMC300A iMOTION Controller with additional microcontroller 21 Position Interface Unit (POSIF) PCONF.HIDG Idle output Can be used to stop the PWM generation unit PIFHP_WHE & PIF_IDLE POSIFx.OUT2 PCONF.EWIS POSIFx.EWHEA 1 PIF_WHE POSIFx.EWHEB Level & Wrong Hall Event Selector POSIFx.EWHEC POSIFx.EWHED PCONF.EWIL PCONF.EWIE Figure 241...
Page 747 IMC300A iMOTION Controller with additional microcontroller 21 Position Interface Unit (POSIF) Figure 243 shows all the previous described steps in the Hall Sensor Mode. Every time that a transition on a Hall input is detected, the pin POSIFx.OUT0 is asserted. This signal is used to start the timing delay between the transition detection and the sampling of the hall inputs.
Page 748 IMC300A iMOTION Controller with additional microcontroller 21 Position Interface Unit (POSIF) 21.2.4 Quadrature Decoder Control The Quadrature Decoder Mode is selected by setting PCONF.FSEL = 01 or PCONF.FSEL = 11 (in this case the Multi-Channel mode is also enabled). Inside the Quadrature Decoder Mode, two different subsets are available: •...
Page 749 IMC300A iMOTION Controller with additional microcontroller 21 Position Interface Unit (POSIF) Standard Quadrature Mode The Quadrature Decoder unit offers a very flexible PhaseA/PhaseB configuration stage. Normally for a clockwise motor shaft rotation, Phase A should precede Phase B but nevertheless, the user can configure the leading phase as well the specific active state for each signal, Figure 245.
Page 750 IMC300A iMOTION Controller with additional microcontroller 21 Position Interface Unit (POSIF) PRUNC.CSM Current Previous State State PIFQA_RISE PIFQD_QA PIFQD_QCLK PIFQA_FALE Direction PIFQD_PCLK & Clock PIFQD_QDIR decoder PIFQD_ERR PIFQB_RISE PIFQD_QB PIFQB_FALE Decoder SM Valid transition Invalid transition Figure 247 Quadrature Decoder States Direction Count Mode Some position encoders do not have the phase signals as outputs, instead, they provide two signals that contain the clock and direction information.
Page 751 IMC300A iMOTION Controller with additional microcontroller 21 Position Interface Unit (POSIF) PIFQD_PHA PIFQD_PHB PIFQD_QCLK PIFQD_PCLK PIFQD_QDIR +1/-1 Generated if the counting direction is maintained PIFQD_PHA PIFQD_PHB PIFQD_QCLK PIFQD_PCLK PIFQD_QDIR +1/-1 +1 Figure 248 Quadrature clock and direction timings PIFQD_PHA PIFQD_PHB PIFQD_QCLK PIFQD_PCLK PIFQD_QDIR...
Page 752 IMC300A iMOTION Controller with additional microcontroller 21 Position Interface Unit (POSIF) signal, then the index signals are going to be generated in the next index event with the rising edge of the Phase B signal if the direction is kept or with the falling edge of Phase B signal if the direction has changed. Figure 250 shows the timing diagram for the generation of the index signals.
Page 753 IMC300A iMOTION Controller with additional microcontroller 21 Position Interface Unit (POSIF) To operate the POSIF in the Quadrature Decoder Mode, one CCU4 module is needed. The Hall Sensor Mode, needs a CCU8 (at least 3 slices are need to control a brushless DC motor) and also (at least) two CCU4 or CCU8 slices.
Page 754 IMC300A iMOTION Controller with additional microcontroller 21 Position Interface Unit (POSIF) POSIFx Clear & Start CCU4x Slice 0 POSIFx.OUT0 Config: edge aligned, single shot Function: Delay between the edge detection of the Hall inputs and the sample; Delay between the CHE and the pattern update PIFHDLY POSIFx.HSD[B...A] PIFMSET...
Page 755 IMC300A iMOTION Controller with additional microcontroller 21 Position Interface Unit (POSIF) POSIFx Clear & Start CCU4x Slice 0 POSIFx.OUT0 Config: edge aligned, single shot Function: Delay between the edge detection of the Hall inputs and the sample PIFHDLY POSIFx.HSD[B...A] Capture (ris) Clear (fall) CCU4x Slice 1...
Page 756 IMC300A iMOTION Controller with additional microcontroller 21 Position Interface Unit (POSIF) Slice 0 is connected to the POSIFx.OUT0 and POSIFx.OUT1 outputs, which means that one has to configure POSIFx.OUT0 as counting functionality and POSIFx.OUT1 as Up/Down counting function. This slice is then used to track the actual position of the system and the compare channel can be configured to trigger the required actions, when the position reaches a certain value.
Page 757 IMC300A iMOTION Controller with additional microcontroller 21 Position Interface Unit (POSIF) CCU4x POSIFx Count POSIFx.OUT0 Slice 0 Config: QCLK as Counting event QDIR as Up/Down selector Function: Position counter. Up/Down Compare interrupt or OUT used as POSIFx.OUT1 position tracker position x Slice 1 Config: QCLK as Counting event QDIR as Up/Down selector...
Page 758 IMC300A iMOTION Controller with additional microcontroller 21 Position Interface Unit (POSIF) CCU4x POSIFx Count Slice 0 POSIFx.OUT0 Config: QCLK as Counting event QDIR as Up/Down selector Function: Position counter. Compare Up/Down interrupt or OUT used as position POSIFx.OUT1 tracker position x Slice 1 Count Config: INDXCNT as count event...
Page 759 IMC300A iMOTION Controller with additional microcontroller 21 Position Interface Unit (POSIF) error error tick ISR time stamp velocity ISR Figure 256 Slow rotating system example It is possible to built a profile with the POSIF and one CCU4 module to perform a control loop that is immune to this slow velocity calculation pitfalls.
Page 760 IMC300A iMOTION Controller with additional microcontroller 21 Position Interface Unit (POSIF) CCU4x POSIFx Count POSIFx.OUT0 Slice 0 Config: QCLK as Counting event Up/Down QDIR as Up/Down selector POSIFx.OUT1 Function: Position counter. Compare interrupt or OUT used as position tracker position x Capture &...
Page 761 IMC300A iMOTION Controller with additional microcontroller 21 Position Interface Unit (POSIF) One output can then be chosen from the CCU4/CCU8 unit that is generating the PWM signals, to act as synchronization trigger between the generated signal and the update of the Multi-Channel pattern (CCU4x.PSy in case of CCU4 and CCU8x.PSy in case of CCU8).
Page 762 IMC300A iMOTION Controller with additional microcontroller 21 Position Interface Unit (POSIF) • Transition at the Hall Inputs (PFLG.HIES) • occurrence of a correct hall event (PFLG.CHES) • occurrence of a wrong hall event (PFLG.WHES) • shadow transfer of the Multi-Channel pattern (PFLG.MSTS) The last one is triggered every time the Multi-Channel pattern is updated (PIFMST), which means that the POSIFx.MOUT[15:0] output was updated with a new value (see also Figure...
Page 763 IMC300A iMOTION Controller with additional microcontroller 21 Position Interface Unit (POSIF) 21.3.2 Quadrature Decoder Flags The Quadrature Decoder Mode has five flags that can be enabled individually as interrupt sources (besides these five flags, the ones that are linked to the usage of Multi-Channel mode are also available: Multi-Channel Pattern update (PFLG.MSTS) and Wrong Hall event (PFLG.WHES).
Page 764 IMC300A iMOTION Controller with additional microcontroller 21 Position Interface Unit (POSIF) PFLGE.INDXE SINDX PFLG.INDXS 1 PIFQD_INDXCNT RINDX PFLGE.ERRE SERR PFLG.ERRS 1 PIFQD_ERR RERR PFLGE.CNTE SCNT PFLG.CNTS 1 PIFQD_QCLK POSIFx.SR0 RCNT PFLGE.DIRE SDIR PFLG.DIRS Node 1 Pointer PIFQD_QDIR RDIR POSIFx.SR1 PFLGE.PCLKE SPCLK PFLG.PCLKS 1...
Page 765 IMC300A iMOTION Controller with additional microcontroller 21 Position Interface Unit (POSIF) Source 1 selector Service request source 1 POSIFx.SR0 Service request From other 1 source 2 sources Service request source 3 Service request source 4 Service request source 5 Service request source 6 POSIFx.SR1 From other...
Page 766 IMC300A iMOTION Controller with additional microcontroller 21 Position Interface Unit (POSIF) Table 269 External Hall/Rotary signals operating conditions Parameter Symbol Values Unit Note/Test Condition Min. Typ. Max. Frequency – – esig posif ON time – – esig posif OFF time toff –...
Page 767 IMC300A iMOTION Controller with additional microcontroller 21 Position Interface Unit (POSIF) Table 270 Registers Address Space Module Base Address End Address Note POSIF0 50010000 50013FFF POSIF1 50014000 50017FFF POSIFx Hall Sensor Mode registers Global registers HALP PCONF HALPS PSUS PRUNC Multi Channel PRUNS Mode registers...
Page 768 IMC300A iMOTION Controller with additional microcontroller 21 Position Interface Unit (POSIF) Table 271 Register Overview of POSIF (continued) Short Name Description Offset Access Mode Description see Addr. Read Write MCSM Multi-Channel Mode shadow Pattern 0044 U, PV U, PV Page MCMS Multi-Channel Mode Control set 0048...
Page 769 IMC300A iMOTION Controller with additional microcontroller 21 Position Interface Unit (POSIF) Field Bits Type Description FSEL Function Selector Hall Sensor Mode enabled Quadrature Decoder Mode enabled stand-alone Multi-Channel Mode enabled Quadrature Decoder and stand-alone Multi-Channel Mode enabled QDCM Position Decoder Mode selection This field selects if the Position Decoder block is in Quadrature Mode or Direction Count Mode.
Page 770 IMC300A iMOTION Controller with additional microcontroller 21 Position Interface Unit (POSIF) (continued) Field Bits Type Description DSEL Delay Pin selector This field selects which input is used to trigger the end of the delay between the detection of an edge in the Hall inputs and the actual sample of the Hall inputs.
Page 771 IMC300A iMOTION Controller with additional microcontroller 21 Position Interface Unit (POSIF) (continued) Field Bits Type Description EWIL External Wrong Hall Event active level POSIFx.EWHE[D...A] signal is active HIGH POSIFx.EWHE[D...A] signal is active LOW 30:28 Low Pass Filters Configuration Low pass filter disabled Low pass of 1 clock cycle Low pass of 2 clock cycles Low pass of 4 clock cycles...
Page 772 IMC300A iMOTION Controller with additional microcontroller 21 Position Interface Unit (POSIF) (continued) Field Bits Type Description MSUS Multi-Channel Mode Suspend Config This field controls the entering in suspend for the Multi-Channel mode. The Hall sensor mode is also covered by this configuration. Suspend request ignored Stop immediately.
Page 773 IMC300A iMOTION Controller with additional microcontroller 21 Position Interface Unit (POSIF) Field Bits Type Description Clear Run bit Writing an 1 into this bit clears the run bit of the module. The module is stopped. Read always returns 0. Clear Current internal status Writing an 1 into this bit resets the state machine of the quadrature decoder and the current status of the Hall sensor and...
Page 774 IMC300A iMOTION Controller with additional microcontroller 21 Position Interface Unit (POSIF) 21.7.1.6 Register PDBG Debug register for current state of the POSIF state machines and Hall Sampled values. PDBG Address: 0100 POSIF Debug register Reset Value: 00000000 LPP2 LPP1 LPP0 IVAL QPSV QCSV...
Page 775 IMC300A iMOTION Controller with additional microcontroller 21 Position Interface Unit (POSIF) MODN MODT MODR Field Bits Type Description MODR Module Revision This bit field indicates the revision number of the module implementation (depending on the design step). MODT 15:8 Module Type MODN 31:16 Module Number...
Page 776 IMC300A iMOTION Controller with additional microcontroller 21 Position Interface Unit (POSIF) (continued) Field Bits Type Description Hall Expected Pattern This field contains the Hall Expected pattern. This field is updated with the HALPS.HEPS values every time that a correct hall event occurs.
Page 777 IMC300A iMOTION Controller with additional microcontroller 21 Position Interface Unit (POSIF) 21.7.3 Multi-Channel Mode Registers 21.7.3.1 Register MCM The register contains the value of the Multi-Channel pattern that is applied to the outputs POSIFx.OUT[15:0]. Address: 0040 Multi-Channel Pattern Reset Value: 00000000 MCMP Field...
Page 778 IMC300A iMOTION Controller with additional microcontroller 21 Position Interface Unit (POSIF) (continued) Field Bits Type Description 31:16 Reserved Read always returns 0 21.7.3.3 Register MCMS Through this register it is possible to request a Multi-Channel pattern update. It is also possible through this register to request an immediate update of the Multi-Channel and Hall Sensor patterns without waiting for the hardware trigger.
Page 779 IMC300A iMOTION Controller with additional microcontroller 21 Position Interface Unit (POSIF) Field Bits Type Description MNPC Multi-Channel Pattern Update Enable Clear Writing a 1 into this field clears the MCMF.MSS bit. A read always returns 0. Multi-Channel Pattern clear Writing a 1 into this field clears the Multi-Channel Pattern value to 0000 A read always returns 0.
Page 780 IMC300A iMOTION Controller with additional microcontroller 21 Position Interface Unit (POSIF) 21.7.4 Quadrature Decoder Registers 21.7.4.1 Register QDC The register contains the configuration for the operation of the Quadrature Decoder Mode. Address: 0060 Quadrature Decoder Control Reset Value: 00000000 DVAL PHS PBLS PALS Field Bits...
Page 781 IMC300A iMOTION Controller with additional microcontroller 21 Position Interface Unit (POSIF) PFLG Address: 0070 POSIF Interrupt Flags Reset Value: 00000000 PCLK INDX DIRS HIES Field Bits Type Description CHES Correct Hall Event Status Correct Hall Event not detected Correct Hall Event detected WHES Wrong Hall Event Status Wrong Hall Event not detected...
Page 782 IMC300A iMOTION Controller with additional microcontroller 21 Position Interface Unit (POSIF) 21.7.5.2 Register PFLGE Through this register it is possible to enable or disable each of the available interrupt sources. It is also possible to select to which service request line an interrupt is forward. PFLGE Address: 0074...
Page 783 IMC300A iMOTION Controller with additional microcontroller 21 Position Interface Unit (POSIF) (continued) Field Bits Type Description EPCLK Quadrature Period CLK interrupt Enable Quadrature Period CLK event interrupt disabled Quadrature Period CLK event interrupt enabled CHESEL Correct Hall Event Service Request Selector Correct Hall Event interrupt forward to POSIFx.SR0 Correct Hall Event interrupt forward to POSIFx.SR1 WHESEL...
Page 784 IMC300A iMOTION Controller with additional microcontroller 21 Position Interface Unit (POSIF) 21.7.5.3 Register SPFLG Through this register it is possible for the SW to set a specific interrupt status flag. SPFLG Address: 0078 POSIF Interrupt Set Reset Value: 00000000 SPCL SIND SDIR SHIE...
Page 785 IMC300A iMOTION Controller with additional microcontroller 21 Position Interface Unit (POSIF) (continued) Field Bits Type Description SDIR Quadrature Direction flag set Writing a 1 to this field sets the PFLG.DIRS bit field. An interrupt pulse is generated. A read always returns 0. SPCLK Quadrature period clock flag set Writing a 1...
Page 786 IMC300A iMOTION Controller with additional microcontroller 21 Position Interface Unit (POSIF) (continued) Field Bits Type Description RERR Quadrature Phase Error flag clear Writing a 1 to this field clears the PFLG.ERRS bit field. A read always returns 0. RCNT Quadrature CLK flag clear Writing a 1 to this field clears the PFLG.CNTS bit field.
Page 787 IMC300A iMOTION Controller with additional microcontroller 21 Position Interface Unit (POSIF) Table 272 POSIF0 Pin Connections (continued) Global Input/Output Connected To Description POSIF0.IN1D ERU0.PDOUT1 Shared connection for rotary encoder and hall sensor POSIF0.IN2A P1.0 Shared connection for rotary encoder and hall sensor POSIF0.IN2B P0.15...
Page 788 IMC300A iMOTION Controller with additional microcontroller 21 Position Interface Unit (POSIF) Table 272 POSIF0 Pin Connections (continued) Global Input/Output Connected To Description POSIF0.MSYNCC CCU40.PS1 Sync for updating the multi channel pattern with the shadow transfer POSIF0.MSYNCD POSIF0.OUT6 Sync for updating the multi channel pattern with the shadow transfer POSIF0.OUT0 CCU40.IN0AE;...
Page 789 IMC300A iMOTION Controller with additional microcontroller 21 Position Interface Unit (POSIF) Table 272 POSIF0 Pin Connections (continued) Global Input/Output Connected To Description POSIF0.MOUT[15] CCU80.MCI33; Multi channel pattern POSIF0.SR0 NVIC Service request line 0 POSIF0.SR1 NVIC; VADC0.BGREQTRO; Service request line 1 VADC0.G0REQTRO;...
Page 790 IMC300A iMOTION Controller with additional microcontroller 21 Position Interface Unit (POSIF) Table 273 POSIF1 Pin Connections (continued) Global Input/Output Connected To Description POSIF1.HSDB POSIF1.OUT0 Used for the Hall pattern sample delay. Like the dead time counter in capcom6 POSIF1.EWHEA VADC0.CBFLOUT3 Wrong Hall event emulation, Trap, etc POSIF1.EWHEB ERU1.IOUT0...
Page 791 IMC300A iMOTION Controller with additional microcontroller 22 Analog-to-Digital Converter (ADC) Table 273 POSIF1 Pin Connections (continued) Global Input/Output Connected To Description POSIF1.OUT3 CCU41.IN0AG; CCU41.IN1AG; Quadrature mode: Index event used for CCU41.IN2AG; CCU41.IN3AE; Clear/capt; Hall sensor mode: stop in Hall sensor mode POSIF1.OUT4 CCU41.IN1AH;...
Page 792 IMC300A iMOTION Controller with additional microcontroller 22 Analog-to-Digital Converter (ADC) CCU4 Conversion Request Control P2.6 P2.8 Conversion P2.9 Result Handling Analog to Digital P2.10 Converter P2.11 NVIC Service Request P2.0 Generation P2.1 P2.2 Configuration Internal analog reference voltage Reference Calibration analog reference gnd Voltage Figure 264...
Page 793 IMC300A iMOTION Controller with additional microcontroller 22 Analog-to-Digital Converter (ADC) 22.1 Analog Module Activation and Control The analog converter of the ADC is the functional block that generates the digital result values from the selected input voltage. It draws a permanent current during its operation and can be deactivated between conversions to reduce the consumed overall energy.
Page 794 IMC300A iMOTION Controller with additional microcontroller 22 Analog-to-Digital Converter (ADC) 22.2 Conversion Request Generation The conversion request unit of a group autonomously handles the generation of conversion requests. • Software triggers directly activate the request source and request a conversion •...
Page 795 IMC300A iMOTION Controller with additional microcontroller 22 Analog-to-Digital Converter (ADC) converted in an ongoing scan sequence. Each conversion start that was triggered by the scan request source, automatically clears the corresponding pending bit. If the last conversion triggered by the scan source is finished and all pending bits are cleared, the current scan sequence is considered finished and a request source event (REV) is generated.
Page 796 IMC300A iMOTION Controller with additional microcontroller 22 Analog-to-Digital Converter (ADC) The indication flags can be cleared by SW by writing 1 to the corresponding bit position in register GLOBEFLAG. 22.3 Analog Input Channel Configuration The analog input channels are assigned to one multiplexer. A number of parameters can be configured in register GLOBICLASS that control the conversion of the channels.
Page 797 IMC300A iMOTION Controller with additional microcontroller 22 Analog-to-Digital Converter (ADC) 22.3.2 Conversion Timing The total time required for a conversion comprises the time from the start of the sample phase until the availability of the result. The timing basis are the module clock f (derived from MCLK) and the converter clock f (typically 32 MHz).
Page 798 IMC300A iMOTION Controller with additional microcontroller 22 Analog-to-Digital Converter (ADC) 22.4 Conversion Result Handling The A/D converter can preprocess the conversion result data to a certain extent before storing them for retrieval by the CPU. This supports the subsequent handling of result data by the application software. Conversion result handling comprises the following functions: •...
Page 799 IMC300A iMOTION Controller with additional microcontroller 22 Analog-to-Digital Converter (ADC) 22.4.1.1 Data Alignment The position of a conversion result value within the selected result register depends on two configurations: • The selected result width (12/10/8 bits, see Chapter 22.3.1) • The selected data accumulation mode (data reduction, see Chapter 22.4.4)
Page 800 IMC300A iMOTION Controller with additional microcontroller 22 Analog-to-Digital Converter (ADC) Conversion Results r0 + r4 + r0 + r4 + r0 + r1 + r4 + r5 + Contents of r1 + r5 + r2 + r6 + Result Reg. MC_VADC_DRC Figure 267 Standard Data Reduction Filter...
Page 801 IMC300A iMOTION Controller with additional microcontroller 22 Analog-to-Digital Converter (ADC) 22.5 Service Request Generation The A/D Converter can activate service request output signals. 2 request signals can issue an interrupt, see Table 278 on page 820. Several events can be assigned to each service request output. Service requests can be generated by three types of events: •...
Page 802 IMC300A iMOTION Controller with additional microcontroller 22 Analog-to-Digital Converter (ADC) Table 275 Registers Overview (continued) Register Short Register Long Name Offset Access Mode Page Name Addr. Num. Read Write BRSPND Request Source Channel Pending Register 01C0 U, PV U, PV GLOBICLASS Input Class Register 00A0...
Page 803 IMC300A iMOTION Controller with additional microcontroller 22 Analog-to-Digital Converter (ADC) 22.6.1 Module Identification The module identification register indicates the version of the ADC module that is used in the IMC300A. 22.6.1.1 Register ID Address: 0008 Module Identification Register Reset Value: 00C5 C0XX SHS0_ID Address:...
Page 804 IMC300A iMOTION Controller with additional microcontroller 22 Analog-to-Digital Converter (ADC) 22.6.2 System Registers A set of standardized registers provides general access to the module and controls basic system functions. 22.6.2.1 Register CLC The Clock Control Register allows the programmer to adapt the functionality and power consumption of the module to the requirements of the application.
Page 805 IMC300A iMOTION Controller with additional microcontroller 22 Analog-to-Digital Converter (ADC) 22.6.2.2 Register OCS The OCDS control and status register OCS controls the module’s behavior in suspend mode (used for debugging). The OCDS Control and Status (OCS) register is cleared by Debug Reset. The OCS register can only be written when the OCDS is enabled.
Page 806 IMC300A iMOTION Controller with additional microcontroller 22 Analog-to-Digital Converter (ADC) 22.6.3 General Registers 22.6.3.1 Register GLOBCFG The global configuration register provides global control and configuration options that are valid for all converters of the cluster. GLOBCFG Address: 0080 Global Configuration Register Reset Value: 0000 0000 SUCA...
Page 807 IMC300A iMOTION Controller with additional microcontroller 22 Analog-to-Digital Converter (ADC) 22.6.3.2 Register SHS0_SHSCFG SHS0_SHSCFG Address: 4803 4040 SHS Configuration Register Reset Value: 0000 1000 STATE SCWC AREF Field Bits Type Description Reserved, write 0, read as 0 AREF 11:10 Analog Reference Voltage Selection External reference, upper supply range Reserved Internal reference, upper supply range...
Page 808 IMC300A iMOTION Controller with additional microcontroller 22 Analog-to-Digital Converter (ADC) 22.6.4 Conversion Request Source Registers 22.6.4.1 Register BRSCTRL The control register of the request source selects the external gate and/or trigger signals. Write control bits allow separate control of each function with a simple write access. BRSCTRL Address: 0200...
Page 809 IMC300A iMOTION Controller with additional microcontroller 22 Analog-to-Digital Converter (ADC) (continued) Field Bits Type Description GTWC Write Control for Gate Configuration No write access to gate configuration Bitfield GTSEL can be written 31:24 Reserved, write 0, read as 0 22.6.4.2 Register BRSMR The Conversion Request Mode Register configures the operating mode of the background request source.
Page 810 IMC300A iMOTION Controller with additional microcontroller 22 Analog-to-Digital Converter (ADC) (continued) Field Bits Type Description SCAN Autoscan Enable No autoscan Autoscan functionality enabled: a request source event automatically generates a load event Autoscan Source Load Event Mode Overwrite mode: Copy all bits from the select registers to the pending registers upon a load event Combine mode: Set all pending bits that are set in the select registers upon a load event (logic OR)
Page 811 IMC300A iMOTION Controller with additional microcontroller 22 Analog-to-Digital Converter (ADC) Field Bits Type Description CHSELGy (y=0-7) Channel Selection Each bit (when set) enables the corresponding input channel to take part in the background scan sequence. Ignore this channel This channel is part of the scan sequence 31:8 Reserved, write 0, read as 0 22.6.4.4...
Page 812 IMC300A iMOTION Controller with additional microcontroller 22 Analog-to-Digital Converter (ADC) 22.6.5 Channel Control Registers 22.6.5.1 Register GLOBICLASS GLOBICLASS Address: 00A0 Input Class Register Reset Value: 0000 0000 STCS Field Bits Type Description STCS Sample Time Control for Standard Conversions Number of additional clock cycles to be added to the minimum sample phase of 2 analog clock cycles: Coding and resulting sample time see Table...
Page 813 IMC300A iMOTION Controller with additional microcontroller 22 Analog-to-Digital Converter (ADC) 22.6.6 Result Register 22.6.6.1 Register GLOBRCR The result control register selects the behavior of the result register. GLOBRCR Address: 0280 Result Control Register Reset Value: 0100 0000 SRGE DRCTR Field Bits Type Description...
Page 814 IMC300A iMOTION Controller with additional microcontroller 22 Analog-to-Digital Converter (ADC) CHNR RESULT Field Bits Type Description RESULT 15:0 Result of most recent conversion The position of the result bits within this bitfield depends on the configured operating mode. Please, refer to Chapter 22.4.1.1.
Page 815 IMC300A iMOTION Controller with additional microcontroller 22 Analog-to-Digital Converter (ADC) GAIN7 GAIN6 GAIN5 GAIN4 GAIN3 GAIN2 GAIN1 GAIN0 Field Bits Type Description GAINx (x=0-7) x*4+3:x*4 rw Gain Control Channel x 0000 Gain factor = 1 0001 Gain factor = 3 0010 Gain factor = 6 0011...
Page 816 IMC300A iMOTION Controller with additional microcontroller 22 Analog-to-Digital Converter (ADC) 22.6.8 Miscellaneous Registers 22.6.8.1 Register SHS0_LOOP The sigma-delta-loop control register LOOP configures the functionality of the sigma-delta-loop(s). SHS0_LOOP Address: 4803 4050 Loop Control Register Reset Value: 0000 0000 LPEN LPCH1 LPEN LPCH0 Field...
Page 817 IMC300A iMOTION Controller with additional microcontroller 22 Analog-to-Digital Converter (ADC) 22.6.9 Service Request Registers 22.6.9.1 Register GLOBEFLAG GLOBEFLAG Address: 00E0 Event Flag Register Reset Value: 0000 0000 SEVG LBCL SEVG Field Bits Type Description SEVGLB Source Event No source event A source event has occurred Reserved, write 0, read as 0 REVGLB...
Page 818 IMC300A iMOTION Controller with additional microcontroller 22 Analog-to-Digital Converter (ADC) 22.6.9.2 Register GLOBEVNP GLOBEVNP Address: 0140 Event Node Pointer Register Reset Value: 0000 0000 REV0NP SEV0NP Field Bits Type Description SEV0NP Service Request Node Pointer Source Event Routes the corresponding event trigger to one of the service request lines (nodes).
Page 819 IMC300A iMOTION Controller with additional microcontroller 22 Analog-to-Digital Converter (ADC) 22.7 Interconnects This section describes the actual implementation of the VADC module into the IMC300A, i.e. the incorporation into the microcontroller system. 22.7.1 Product-Specific Configuration The functional description describes the features and operating modes of the A/D Converters in a general way. This section summarizes the configuration that is available in this product (IMC300A).
Page 820 IMC300A iMOTION Controller with additional microcontroller 22 Analog-to-Digital Converter (ADC) 22.7.3 Digital Module Connections in the IMC300A The VADC module accepts a number of digital input signals and generates a number of output signals. This section summarizes the connection of these signals to other on-chip modules or to external resources via port pins.
Page 821 IMC300A iMOTION Controller with additional microcontroller 22 Analog-to-Digital Converter (ADC) Table 278 Digital Connections in the IMC300A (continued) Signal Dir. Source/Destination Description BGREQTRI Trigger input I (XTSEL = 1000 BGREQTRJ Trigger input J (XTSEL = 1001 BGREQTRK Trigger input K (XTSEL = 1010 BGREQTRL Trigger input L (XTSEL = 1011 BGREQTRM...
Page 822 IMC300A iMOTION Controller with additional microcontroller 23 Analog Comparator (ACMP) and Out of Range Comparator (ORC) Analog Comparator (ACMP) and Out of Range Comparator (ORC) This chapter describes the controls for analog comparator (ACMP) and out of range comparator (ORC). 23.1 Overview This section gives an overview about the feature set of the Analog comparator and the Out of Range...
Page 823 IMC300A iMOTION Controller with additional microcontroller 23 Analog Comparator (ACMP) and Out of Range Comparator (ORC) blanking time is in a range of few usec. With the help of bit ANACMPx.CMP_INV_OUT, the comparator output is inverted. The output of the comparator could be used to wake-up the system from power save mode. It can also be observed from a pin.
Page 824 IMC300A iMOTION Controller with additional microcontroller 23 Analog Comparator (ACMP) and Out of Range Comparator (ORC) Low Power Mode A low power state helps to reduce the total power consumption e.g. during sleep mode. It can be enabled by setting ANACMPx.LPWR to HIGH. In this mode, the analog comparators may shows a reduced performance. When switching back to normal mode, the blanking time applies to ensure a stable output.
Page 825 IMC300A iMOTION Controller with additional microcontroller 23 Analog Comparator (ACMP) and Out of Range Comparator (ORC) • Read or write access to undefined address • Write access to read-only registers Table 279 Registers Address Space Module Base Address End Address Note COMPARATOR 4001 0000...
Page 826 IMC300A iMOTION Controller with additional microcontroller 23 Analog Comparator (ACMP) and Out of Range Comparator (ORC) Field Bits Type Description ENORCx (x=0,4,6,7) Enable Out of Range Comparator x This bit defines if the out of range comparator is enabled in the corresponding analog input channel.
Page 827 IMC300A iMOTION Controller with additional microcontroller 23 Analog Comparator (ACMP) and Out of Range Comparator (ORC) (continued) Field Bits Type Description CMP_HYST_ADJ Comparator hysteresis adjust To reduce noise sensitivity a hysteresis voltage can be chosen. It can be switched off with writing HYS_OFF, Comparator hysteresis is switched off HYS1, Hysteresis_typ = 10mV HYS2, Hysteresis_typ = 15mV...
Page 828 IMC300A iMOTION Controller with additional microcontroller 23 Analog Comparator (ACMP) and Out of Range Comparator (ORC) Field Bits Type Description CMP_EN Comparator enable CMP_DIS, Comparator is disabled CMP_EN, Comparator is enabled CMP_FLT_OFF Disables comparator filter If set, the comparator glitch-filter is switched off FIL_ON, filter is active FIL_OFF, filter is switched off (to prevent a filter delay) CMP_INV_OUT...
Page 829 IMC300A iMOTION Controller with additional microcontroller 23 Analog Comparator (ACMP) and Out of Range Comparator (ORC) Field Bits Type Description CMP_EN Comparator enable CMP_DIS, Comparator is disabled CMP_EN, Comparator is enabled CMP_FLT_OFF Disables comparator filter If set, the comparator glitch-filter is switched off FIL_ON, filter is active FIL_OFF, filter is switched off (to prevent a filter delay) CMP_INV_OUT...
Page 830 IMC300A iMOTION Controller with additional microcontroller 23 Analog Comparator (ACMP) and Out of Range Comparator (ORC) CMP_ CMP_HYST _INV P3_S _FLT _ADJ _OFF Field Bits Type Description CMP_EN Comparator enable CMP_DIS, Comparator is disabled CMP_EN, Comparator is enabled CMP_FLT_OFF Disables comparator filter If set, the comparator glitch-filter is switched off FIL_ON, filter is active FIL_OFF, filter is switched off (to prevent a filter delay)
Page 831 IMC300A iMOTION Controller with additional microcontroller 23 Analog Comparator (ACMP) and Out of Range Comparator (ORC) Table 281 Analog Comparator Pin Connections Input/Output Connected To Description ACMP0.INN P2.8 “-” input of ACMP0 ACMP0.INP P2.9 “+” input of ACMP0 ACMP1.INN P2.6 “-”...
Page 832 IMC300A iMOTION Controller with additional microcontroller 23 Analog Comparator (ACMP) and Out of Range Comparator (ORC) Table 281 Analog Comparator Pin Connections (continued) Input/Output Connected To Description ACMP3.OUT P4.1 output of ACMP3 CCU40.IN1AR CCU40.IN3AS ERU1.1A0 CCU41.IN1AR CCU41.IN3AS Table 282 Out of Range Comparator Pin Connections Input/Output Connected To Description...
Page 833 IMC300A iMOTION Controller with additional microcontroller 24 Digital to Analog Converter (DAC) Digital to Analog Converter (DAC) The DAC of IMC300A is a sigma delta digital to analog converter that is capable of controlling multiple channels. A one-bit sigma-delta bit stream is provided for every channel that determines the output level. The module supports automatic control of the output level by adjusting the relative data value of selected channels using a linear ramp function.
Page 834 IMC300A iMOTION Controller with additional microcontroller 24 Digital to Analog Converter (DAC) 24.2.1 RC Low-Pass Filter Thesigma-delta bitstream must be averaged by an external low-pass filter. The DAC.OUTy signals of the port pins in push-pull configuration can directly drive the RC-filter. The output voltage can be used across the capacitor.
Page 835 IMC300A iMOTION Controller with additional microcontroller 24 Digital to Analog Converter (DAC) 24.2.3 Sigma-Delta Modulator The sigma-delta modulator oversamples the slowly changing 12-bit data signal and changes it into a high bitrate single-bit signal. The average analog value of the single-bit signal is directly proportional to the 12-bit data value.
Page 836 IMC300A iMOTION Controller with additional microcontroller 24 Digital to Analog Converter (DAC) FCLK_PS DAC_clk DAC_fclk channels DAC_bclk Figure 274 DAC clocks The clock frequencies in normal mode can be calculated with the following formulas: × f fclk FCLKPS Equation 51 ×...
Page 837 IMC300A iMOTION Controller with additional microcontroller 24 Digital to Analog Converter (DAC) 3. Set target data values and start ramp function • DAC_CHCONFIGy.RAMP_PS to set the ramp time • DAC_DATASy to set the target intensities • DAC_CHSTRCON to start ramp function •...
Page 838 IMC300A iMOTION Controller with additional microcontroller 24 Digital to Analog Converter (DAC) WDMBN SUSCFG Field Bits Type Description Reserved Read as 0; should be written with 0. SUSCFG Suspend Mode Configuration This bitfield determines how the DAC channels enter suspend mode.
Page 839 IMC300A iMOTION Controller with additional microcontroller 24 Digital to Analog Converter (DAC) Field Bits Type Description FCLK_PS 11:0 Fast Clock Prescaler Factor The constant clock input to the DAC is prescaled according to this value to generate DAC_fclk. DAC_bclk is generated from DAC_fclk by a division of 4.
Page 840 IMC300A iMOTION Controller with additional microcontroller 24 Digital to Analog Converter (DAC) CHEN Address: 000C Channel Enable Reset Value: 0000 0000 Field Bits Type Description ECHy (y=0-8) Channel y Enable Channel is disabled, the output level is passive; the ramp function and the Sigma-Delta Modulator are reset;...
Page 841 IMC300A iMOTION Controller with additional microcontroller 24 Digital to Analog Converter (DAC) (continued) Field Bits Type Description CHyA (y=0-8) y+16 Channel y Ramp Function Abort No action Abort ramp function; CHyS is cleared, channel y data value stops changing Always read as 0 31:25 Reserved Read as 0;...
Page 842 IMC300A iMOTION Controller with additional microcontroller 24 Digital to Analog Converter (DAC) CHDATA Field Bits Type Description CHDATA 11:0 Channel Data Value Actual channel intensity. 31:12 Reserved Read as 0; should be written with 0. 24.6.2.3 Register CHCONFIGy CHCONFIGy (y=0-8) Address: 0044 + y*0014...
Page 843 IMC300A iMOTION Controller with additional microcontroller 24 Digital to Analog Converter (DAC) (continued) Field Bits Type Description 15:10 Reserved Read as 0; should be written with 0. RAMP_PS 25:16 Ramp Clock Prescaler Determines how long it takes for the Channel Data Value to reach the Target Channel Data Value after shadow transfer (after CHSTRCON.CHyS is set).
Page 844 IMC300A iMOTION Controller with additional microcontroller 24 Digital to Analog Converter (DAC) Table 285 DAC0 Pin Connections (continued) Global Input/Output Connected To Description DAC0.OUT3 CCU40.MCI1; Output of channel 3 CCU40.IN1AZ; CCU41.IN1AZ; P1.1.HW0 pull control; DAC0.OUT4 P0.8; Output of channel 4 P4.2;...
Page 845 IMC300A iMOTION Controller with additional microcontroller 25 Temperature Sensor (DTS) Temperature Sensor (DTS) This chapter describes the controls for Temperature Sensor (DTS). 25.1 General Description The Temperature Sensor (DTS) generates a measurement result that represents the current temperature. The result of the measurement is displayed via bit field ANATSEMON.TSE_MON. The temperature sensor has to be enabled before it can be used via bit ANATSECTRL.TSE_EN.
Page 846 IMC300A iMOTION Controller with additional microcontroller 25 Temperature Sensor (DTS) Table 287 Registers Overview (continued) Short Name Description Offset Access Mode Description See Addr. Read Write ANATSEIH Temperature Sensor High 0030 U, PV U, PV Page Interrupt Register ANATSEIL Temperature Sensor Low 0034 U, PV U, PV...
Page 847 IMC300A iMOTION Controller with additional microcontroller 25 Temperature Sensor (DTS) Field Bits Type Description TSE_IH 15:0 Counter value for high temperature interrupt ANATSEIH value is compared with ANATSEMON (with the counter value) An high temperature interrupt is triggered if: ANATSE_MON < ANATSEIH The comparison result can be observed from SCU_SRRAW.TSE_HIGH 25.3.3...
Page 848 IMC300A iMOTION Controller with additional microcontroller 26 General Purpose I/O Ports (Ports) General Purpose I/O Ports (Ports) The IMC300A has up to 56 digital General Purpose Input/Output (GPIO) port lines which are connected to the on-chip peripheral units. 26.1 Overview The Ports provide a generic and very flexible software and hardware interface for all standard digital I/Os.
Page 849 IMC300A iMOTION Controller with additional microcontroller 26 General Purpose I/O Ports (Ports) 26.1.2 Block Diagram Below is a figure with the generic structure of a digital port pin, split into the port slice with the control logic and the pad with the pull devices and the input and output stages, Figure 275.
Page 850 IMC300A iMOTION Controller with additional microcontroller 26 General Purpose I/O Ports (Ports) A group of up to 16 Port Pins sharing the same generic register set (P0). Port Slice The “sum” of register bits and control logic used to control a port pin. Analog component containing the output driver, pull devices and input Schmitt-Trigger.
Page 851 IMC300A iMOTION Controller with additional microcontroller 26 General Purpose I/O Ports (Ports) Pad Hysteresis Control The pad hysteresis can be configured according to the application needs via the Pad Hysteresis Control register (Pn_PHCR, Chapter 26.8.2). Selecting the appropriate pad hysteresis allows optimized pad oscillation behaviour for touch-sensing applications.
Page 852 IMC300A iMOTION Controller with additional microcontroller 26 General Purpose I/O Ports (Ports) • Standard pad (without oscillator function) • High Current pad The assignment of each port pin to one of these pad types is listed in the Package Pin Summary table. Further details about pad properties are summarized in the Data Sheet.
Page 853 IMC300A iMOTION Controller with additional microcontroller 26 General Purpose I/O Ports (Ports) Port Slice Power-save control (Powersave active) Powersave Pad output tri-state, Pn_PPS Control Pull devices off, Schmitt-Trigger off Pn_IOCR pull devices Input value Pn_IN disconnected from pad Input stage Output register provides written or the last in Pn_OUT...
Page 854 IMC300A iMOTION Controller with additional microcontroller 26 General Purpose I/O Ports (Ports) Port Slice Digital Input enable/disable Pn_PDISC Powersave Power-save control Pn_PPS Control Pn_IOCR pull I/O Control for pull devices, devices input inverter Pn_OMR and power-save Pn_OUT General Purpose Input Pn_IN (Optionally inverted) Input...
Page 855 IMC300A iMOTION Controller with additional microcontroller 26 General Purpose I/O Ports (Ports) Input When a peripheral shall use a port pin as input, the actual pin levels may immediately trigger an unexpected peripheral event (e.g. clock edge at SPI). This can be avoided by forcing the "passive" level via pull-up/down programming.
Page 856 IMC300A iMOTION Controller with additional microcontroller 26 General Purpose I/O Ports (Ports) 26.8 Registers Registers Overview The absolute register address is calculated by adding: Module Base Address + Offset Address Table 289 Registers Address Space Module Base Address End Address Note 4004 0000 4004 00FF...
Page 857 IMC300A iMOTION Controller with additional microcontroller 26 General Purpose I/O Ports (Ports) Table 290 Register Overview (continued) Short Name Description Offset Access Mode Description See Addr. Read Write P3_PDISC Port n Pin Function Decision Control 0060 U, PV Page Register (non-ADC/ACMP ports) P4_PDISC –...
Page 858 IMC300A iMOTION Controller with additional microcontroller 26 General Purpose I/O Ports (Ports) Depending on the GPIO port functionality (number of GPIO lines of a port), not all of the port input/output control registers are implemented. The structure with one control bit field for each port pin located in different register bytes offers the possibility to configure the port pin functionality of a single pin with byte-oriented accesses without accessing the other PCx bit fields.
Page 859 IMC300A iMOTION Controller with additional microcontroller 26 General Purpose I/O Ports (Ports) Table 292 Standard PCx Coding (continued) PCx[5:0] Output Selected Pull-up / Pull-down / Characteristics Selected Output Function 110000 Output Open-drain General-purpose output (Direct 110001 Alternate output function 1 Input) 110010 Alternate output function 2...
Page 860 IMC300A iMOTION Controller with additional microcontroller 26 General Purpose I/O Ports (Ports) (continued) Field Bits Type Description 23:18 Port Control for Port n Pin 2 This bit field determines the Port n line x functionality (x = 2) according to the coding table (see Table 292).
Page 861 IMC300A iMOTION Controller with additional microcontroller 26 General Purpose I/O Ports (Ports) P3_IOCR4 Address: 0014 Port 3 Input/Output Control Register 4 Reset Value: 0000 0000 Field Bits Type Description Port Control for Port 3 Pin 4 This bit field determines the Port 3 line x functionality (x = 4) according to the coding table (see Table 292 1:0, 31:8...
Page 862 IMC300A iMOTION Controller with additional microcontroller 26 General Purpose I/O Ports (Ports) (continued) Field Bits Type Description PC10 23:18 Port Control for Port n Pin 10 This bit field determines the Port n line x functionality (x = 10) according to the coding table (see Table 292 PC11 31:26...
Page 863 IMC300A iMOTION Controller with additional microcontroller 26 General Purpose I/O Ports (Ports) PC15 PC14 PC13 PC12 Field Bits Type Description PC12 Port Control for Port 0 Pin 12 This bit field determines the Port 0 line x functionality (x = 12) according to the coding table (see Table 292).
Page 864 IMC300A iMOTION Controller with additional microcontroller 26 General Purpose I/O Ports (Ports) (continued) Field Bits Type Description PC13 15:10 Port Control for Port 2 Pin 13 This bit field determines the Port 2 line x functionality (x = 13) according to the coding table (see Table 292).
Page 865 IMC300A iMOTION Controller with additional microcontroller 26 General Purpose I/O Ports (Ports) (continued) Field Bits Type Description Pad Hysteresis for Pn.1 Pad Hysteresis for Pn.2 Pad Hysteresis for Pn.3 Pad Hysteresis for Pn.4 Pad Hysteresis for Pn.5 Pad Hysteresis for Pn.6 Pad Hysteresis for Pn.7 1:0, 5:3, Reserved...
Page 866 IMC300A iMOTION Controller with additional microcontroller 26 General Purpose I/O Ports (Ports) P0_PHCR1 Address: 0044 Port 0 Pad Hysteresis Control Register 1 Reset Value: 0000 0000 PH15 PH14 PH13 PH12 PH11 PH10 Field Bits Type Description Pad Hysteresis for P0.8 Pad Hysteresis for P0.9 PH10 Pad Hysteresis for P0.10...
Page 867 IMC300A iMOTION Controller with additional microcontroller 26 General Purpose I/O Ports (Ports) (continued) Field Bits Type Description 1:0, 31:3 Reserved Read as 0; should be written with 0. 26.8.2.5 Register P2_PHCR1 P2_PHCR1 Address: 0044 Port 2 Pad Hysteresis Control Register 1 Reset Value: 0000 0000 PH13...
Page 868 IMC300A iMOTION Controller with additional microcontroller 26 General Purpose I/O Ports (Ports) Field Bits Type Description Pad Hysteresis for P4.8 Pad Hysteresis for P4.9 PH10 Pad Hysteresis for P4.10 PH11 Pad Hysteresis for P4.11 1:0, 5:3, Reserved 9:7, Read as 0; should be written with 0. 13:11, 31:15 26.8.3...
Page 869 IMC300A iMOTION Controller with additional microcontroller 26 General Purpose I/O Ports (Ports) PDIS PDIS PDIS PDIS PDIS PDIS PDIS PDIS PDIS Field Bits Type Description PDISx (x=0-8) Pad Disable for Port 1 Pin x Pad P1.x is enabled. Pad P1.x is disabled. 31:9 Reserved Read as 0;...
Page 870 IMC300A iMOTION Controller with additional microcontroller 26 General Purpose I/O Ports (Ports) (continued) Field Bits Type Description PDISx (x=2-9) Pad Disable for Port 2 Pin 2 to 9 This bit disables or enables the digital pad function. Digital Pad input is enabled. Analog and digital input path active.
Page 871 IMC300A iMOTION Controller with additional microcontroller 26 General Purpose I/O Ports (Ports) PDIS PDIS PDIS PDIS PDIS PDIS PDIS PDIS PDIS PDIS PDIS PDIS Field Bits Type Description PDISx (x=0-11) Pad Disable for Port 4 Pin x Pad P4.x is enabled. Pad P4.x is disabled.
Page 872 IMC300A iMOTION Controller with additional microcontroller 26 General Purpose I/O Ports (Ports) Field Bits Type Description Px (x=0-15) Port 0 Output Bit x This bit determines the level at the output pin P0.x if the output is selected as GPIO output. The output level of P0.x is 0.
Page 873 IMC300A iMOTION Controller with additional microcontroller 26 General Purpose I/O Ports (Ports) Field Bits Type Description Px (x=0-13) Port 2 Output Bit x This bit determines the level at the output pin P2.x if the output is selected as GPIO output. The output level of P2.x is 0.
Page 874 IMC300A iMOTION Controller with additional microcontroller 26 General Purpose I/O Ports (Ports) P4_OUT Address: 0000 Port 4 Output Register Reset Value: 0000 0000 Field Bits Type Description Px (x=0-11) Port 4 Output Bit x This bit determines the level at the output pin P4.x if the output is selected as GPIO output.
Page 875 IMC300A iMOTION Controller with additional microcontroller 26 General Purpose I/O Ports (Ports) PR15 PR14 PR13 PR12 PR11 PR10 PR9 PS15 PS14 PS13 PS12 PS11 PS10 PS9 Field Bits Type Description PSx (x=0-15) Port 0 Set Bit x Setting this bit will set or toggle the corresponding bit in the port output register P0_OUT.
Page 876 IMC300A iMOTION Controller with additional microcontroller 26 General Purpose I/O Ports (Ports) P2_OMR Address: 0004 Port 2 Output Modification Register Reset Value: 0000 0000 PR13 PR12 PR11 PR10 PR9 PS13 PS12 PS11 PS10 PS9 Field Bits Type Description PSx (x=0-13) Port 2 Set Bit x Setting this bit will set or toggle the corresponding bit in the port output register P2_OUT.
Page 877 IMC300A iMOTION Controller with additional microcontroller 26 General Purpose I/O Ports (Ports) (continued) Field Bits Type Description PRx (x=0-4) x+16 Port 3 Reset Bit x Setting this bit will reset or toggle the corresponding bit in the port output register P3_OUT. The function of this bit is shown in Table 294.
Page 878 IMC300A iMOTION Controller with additional microcontroller 26 General Purpose I/O Ports (Ports) Field Bits Type Description Px (x=0-15) Port 0 Input Bit x This bit indicates the level at the input pin P0.x. The input level of P0.x is 0. The input level of P0.x is 1.
Page 879 IMC300A iMOTION Controller with additional microcontroller 26 General Purpose I/O Ports (Ports) Field Bits Type Description Px (x=0-13) Port 2 Input Bit x This bit indicates the level at the input pin P2.x. The input level of P2.x is 0. The input level of P2.x is 1.
Page 880 IMC300A iMOTION Controller with additional microcontroller 26 General Purpose I/O Ports (Ports) Field Bits Type Description Px (x=0-11) Port 4 Input Bit x This bit indicates the level at the input pin P4.x. The input level of P4.x is 0. The input level of P4.x is 1.
Page 881 IMC300A iMOTION Controller with additional microcontroller 26 General Purpose I/O Ports (Ports) Table 295 PCx Coding in Deep-Sleep mode (continued) PCx[5:0] Normal Operation or Deep-Sleep mode and PPSx=1 PPSx=0 no pull device active, Input value=Pn_OUTx 26.8.7.1 Register P0_PPS P0_PPS Address: 0070 Port 0 Pin Power Save Register Reset Value:...
Page 882 IMC300A iMOTION Controller with additional microcontroller 26 General Purpose I/O Ports (Ports) Field Bits Type Description PPSx (x=0-8) Port 1 Pin Power Save Bit x Pin Power Save of P1.x is disabled. Pin Power Save of P1.x is enabled. 31:9 Reserved Read as 0.
Page 883 IMC300A iMOTION Controller with additional microcontroller 26 General Purpose I/O Ports (Ports) Field Bits Type Description PPSx (x=0-4) Port 3 Pin Power Save Bit x Pin Power Save of P3.x is disabled. Pin Power Save of P3.x is enabled. 31:5 Reserved Read as 0.
Page 884 IMC300A iMOTION Controller with additional microcontroller 26 General Purpose I/O Ports (Ports) P0_HWSEL Address: 0074 Port 0 Pin Hardware Select Register Reset Value: 0000 0000 HW15 HW14 HW13 HW12 HW11 HW10 Field Bits Type Description HWx (x=0-15) 2*x+1:2*x rw Port 0 Pin Hardware Select Bit x Software control only.
Page 885 IMC300A iMOTION Controller with additional microcontroller 26 General Purpose I/O Ports (Ports) P2_HWSEL Address: 0074 Port 2 Pin Hardware Select Register Reset Value: 0000 0000 HW13 HW12 HW11 HW10 Field Bits Type Description HWx (x=0-13) 2*x+1:2*x rw Port 2 Pin Hardware Select Bit x Software control only.
Page 886 IMC300A iMOTION Controller with additional microcontroller 26 General Purpose I/O Ports (Ports) P4_HWSEL Address: 0074 Port 4 Pin Hardware Select Register Reset Value: 0000 0000 HW11 HW10 Field Bits Type Description HWx (x=0-11) 2*x+1:2*x rw Port 4 Pin Hardware Select Bit x Software control only.
Page 887 IMC300A iMOTION Controller with additional microcontroller 26 General Purpose I/O Ports (Ports) Table 296 Port Pin for Boot Modes (continued) Boot Boot Description CAN BSL mode DATA(I/O) SSC BSL mode Pin: P4.6 HWCON0 Boot Pins (Boot-from-pins mode must be selected) Pin: P4.7 HWCON1 Boot Pins...
Page 888 IMC300A iMOTION Controller with additional microcontroller 26 General Purpose I/O Ports (Ports) Pn.y is the port pin name, defining the control and data bits/registers associated with it. As GPIO, the port is under software control. Its input value is read via Pn_IN.y, Pn_OUT defines the output value. Up to nine alternate output functions (ALT1 to ALT9) can be mapped to a single port pin, selected by Pn_IOCR.PC.
Page 889 IMC300A iMOTION Controller with additional microcontroller 26 General Purpose I/O Ports (Ports) Table 299 Port Input Functions (continued) Func- Func- Func- Func- Func- Func- Func- Func- Func- Func- Func- Func- tions tions tions tions tions tions tions tions tions tions tions tions P2.1...
Page 890 IMC300A iMOTION Controller with additional microcontroller 26 General Purpose I/O Ports (Ports) Table 300 Port Output Functions Non-listed pins have no port output functions. ALT1 ALT2 ALT3 ALT4 ALT5 ALT6 ALT7 ALT8 ALT9 P0.8/ DAC0.OU CCU40.O USIC0_C USIC0_C CCU41.O H0.SCLKO H1.SCLKO RTC_X TAL1...
Page 891 IMC300A iMOTION Controller with additional microcontroller 26 General Purpose I/O Ports (Ports) Table 300 Port Output Functions (continued) Non-listed pins have no port output functions. ALT1 ALT2 ALT3 ALT4 ALT5 ALT6 ALT7 ALT8 ALT9 P4.0 DAC0.OU ERU1.PD ERU1.GO CCU40.O ACMP1.O CCU41.O OUT0 P4.1...
Page 892 IMC300A iMOTION Controller with additional microcontroller 26 General Purpose I/O Ports (Ports) Table 302 Hardware Controlled I/O Functions Non-listed pins have no hardware controlled I/O and pull control function. Outputs Inputs Pull Control HWO0 HWO1 HWI0 HWI1 HW0_PD HW0_PU HW1_PD HW1_PU P1.0 USIC0_CH0.
Page 893 IMC300A iMOTION Controller with additional microcontroller 26 General Purpose I/O Ports (Ports) + 0.5 -0.5 -0.5 Abs. max. input voltage V with V > 5.5 V Abs. max. input voltage V with V ≤ 5.5 V Figure 279 Absolute Maximum Input Voltage Ranges 26.10.2 Input Low and Input High Voltage Figure 280...
Page 894 IMC300A iMOTION Controller with additional microcontroller 26 General Purpose I/O Ports (Ports) 26.10.3 Output Low and Output High Voltage defines the maximum voltage level that will appear on a digital output set to ‘0’. V defines the minimum voltage level that will appear on a digital output set to ‘1’. The output parameters are usually given for a specified I , as the output levels are dependant on the load impedance applied to the logic output.
Page 895 IMC300A iMOTION Controller with additional microcontroller 26 General Purpose I/O Ports (Ports) ~Rdson /RL1 OH_L1 /RL2 OH_L2 Figure 282 Output High Voltage 26.10.4 Pin Reliability in Overload When receiving signals from higher voltage devices, low-voltage devices experience overload currents and voltages that go beyond their own IO power supplies specification.
Page 896 IMC300A iMOTION Controller with additional microcontroller 26 General Purpose I/O Ports (Ports) Note: A series resistor at the pin to limit the current to the maximum permitted overload current is sufficient to handle failure situations like short to battery. Figure 283 shows the path of the input currents during overload via the ESD protection structures.
Page 897 IMC300A iMOTION Controller with additional microcontroller 26 General Purpose I/O Ports (Ports) Valid High ≥ |I PDP,min IHPx, min ≤ |I PDP,max Invalid digital input ILPx, max Valid Low Pull-down active Valid High IHPx, min ≤ |I Invalid digital input PUP,max ILPx, max ≥...
Page 898 IMC300A iMOTION Controller with additional microcontroller 27 Boot and Startup Boot and Startup The startup sequence of the IMC300A is a process taking place before user application software takes control of the system and is comprising of two major phases (see Figure 285), split in several distinctive steps: Hardware Controlled Startup Phase...
Page 899 IMC300A iMOTION Controller with additional microcontroller 27 Boot and Startup 27.1.2 System Reset Release The internal power-on reset generation is based on the supply and core voltage validation. When V and V reaches a stable threshold level, the power-on reset is released. Next, after the on-chip oscillators generate a stable clock output, the system reset is released automatically and the SSW code starts to run.
Page 900 IMC300A iMOTION Controller with additional microcontroller 27 Boot and Startup configuration 3..48 MHz from initial 8MHz - i.e. MCLK frequency can be increased or decreased no more than 4 times (rounded, ignoring potential FDIV influence). In case CLK_VAL1 (refer to Table 305) contains IDIV value out of the 1..16 range: •...
Page 901 IMC300A iMOTION Controller with additional microcontroller 27 Boot and Startup peripheral clocks can be enable/disable via the SCU_CGATCLR0/SCU_CGATSET0 register respectively. It is also recommended to enable the oscillator watchdog for loss of clock detection. System Reset Configuration Several events such as Flash ECC error or SRAM parity error can be used to trigger a system reset using the SCU_RSTCON register.
Page 902 IMC300A iMOTION Controller with additional microcontroller 27 Boot and Startup SSW does not check either the target address is inside user Flash. Therefore HardFault will be generated if it’s outside and the execution will jump to exception handler in SRAM (upon master reset an endless loop is installed by SSW).
Page 903 IMC300A iMOTION Controller with additional microcontroller 27 Boot and Startup 27.2.1.6 Bootstrap Loader modes with time-out These modes are using the Standard BSL routines for downloading, but the functionality is different: • SSW first checks either an external device is connected/active, meaning SSW waits to receive Start and Header Bytes from the host - either via USIC channel 0 or 1 - for time-out which duration is taken from BMI.BLSTO (refer to Chapter...
Page 904 IMC300A iMOTION Controller with additional microcontroller 27 Boot and Startup Address: 1000'0E00 Boot Mode Index Delivery State: F8C3 PIND BSLTO DAPDIS HWCFG Field Bits Type Description HWCFG Start-up Mode Selection: 0000000 CAN Bootstrap Loader mode (CAN_BSL) 0010000 CAN BSL mode with time-out (CAN_BSLTO) 0100000 Secure Bootstrap Loader mode over CANopen (SBSL CANopen)
Page 905 IMC300A iMOTION Controller with additional microcontroller 27 Boot and Startup 27.2.3 Start-up mode selection The start-up modes in IMC300A are selected and handled according to Boot Mode Index (BMI) value read from Flash - refer to Chapter 27.2.1. The BMI evaluation can lead to: •...
Page 906 IMC300A iMOTION Controller with additional microcontroller 27 Boot and Startup • enable the debug interface • if start-up mode with Halt After Reset request (UMHAR) is selected in BMI upon master reset - enter an endless NOP (no operation) loop. From this point on, an external tool (debugger) can take over the control of the device, in particular: if/when a debugger connects to device, it can halt the CPU and check BMI and/or the core program counter (PC) register...
Page 907 IMC300A iMOTION Controller with additional microcontroller 27 Boot and Startup Table 305 Flash data for SSW and user SW in IMC300A (continued) Address Length Function Target location 1000’1014 Clock gating configuration value If bit[31]=0: CLK_VAL2 Installation of • bits[21:16] into SCU_CGATCLR0[21:16] •...
Page 908 IMC300A iMOTION Controller with additional microcontroller 28 Bootstrap Loaders (BSL) and User Routines Bootstrap Loaders (BSL) and User Routines This chapter describes the Bootstrap Loaders (BSL) and the user-accessible routines in the ROM memory. The ASC (UART) BSL (Chapter 28.1) and the SSC BSL (Chapter 28.2) is entered with the BMI settings as described in the Boot and Startup Chapter.
Page 909 IMC300A iMOTION Controller with additional microcontroller 28 Bootstrap Loaders (BSL) and User Routines enable and configure the both USIC0 communication channels 0 and 1 as follows: ASC mode, 8 data bits, 1 stop bit, no parity configure ASC clock-generation circuitry for measurement perform continuously the following sequence for both USIC0 channels one after another check either Start zero Byte has been received if yes - then:...
Page 910 IMC300A iMOTION Controller with additional microcontroller 28 Bootstrap Loaders (BSL) and User Routines Configure USIC baud rate generator accordingly Receive from host BSL_BR_OK to indicate that the communication channel has been successfully established • If no or wrong acknowledge value is received, a device software reset will be triggered Figure 286 shows the outline of the sequence to configure the baud rate.
Page 911 IMC300A iMOTION Controller with additional microcontroller 28 Bootstrap Loaders (BSL) and User Routines Listening 1-to-0 transition on RXD Starts BR detection (Receive zero byte) 0-to-1 transition on RXD Configure fractional divider Receive header byte Header byte = Header byte = BSL_ASC_F/H? BSL_ENC_F/H? Send BSL_ENC_ID and...
Page 912 IMC300A iMOTION Controller with additional microcontroller 28 Bootstrap Loaders (BSL) and User Routines 28.1.2.2 ASC BSL download sequence After the baud rate has been detected/configured and channel/mode (full/half duplex) selected, ASC BSL awaits 4 bytes describing the length of the application from the host (refer to Figure 287).
Page 913 IMC300A iMOTION Controller with additional microcontroller 28 Bootstrap Loaders (BSL) and User Routines Table 308 Handshake protocol data definitions in IMC300A ASC BSL Name Length, Value Description Byte Requests/data/acknowledge sent by the Host BSL_ASC_F Header requesting full duplex ASC mode with the current baud rate BSL_ASC_H Header requesting half duplex ASC mode with the current baud rate BSL_ENC_F...
Page 914 IMC300A iMOTION Controller with additional microcontroller 28 Bootstrap Loaders (BSL) and User Routines Handshake Protocol (based on ASC BSL) Host Zero byte Configures baud rate BSL_ASC_F/H BSL_ID Handshake Protocol (based on Enhanced ASC BSL) Host Zero byte Configures initial baud rate with fractional divider in normal mode BSL_ENC_F/H...
Page 915 IMC300A iMOTION Controller with additional microcontroller 28 Bootstrap Loaders (BSL) and User Routines 28.2 SSC Bootstrap loader This procedure downloads code from a SPI-compatible serial EEPROM into SRAM starting at address 2000 0200 up to the user-available SRAM size, using Channel 0 of USIC0 Module. IMC300A is the master SPI-device, following pins are used by the bootloader: •...
Page 916 IMC300A iMOTION Controller with additional microcontroller 28 Bootstrap Loaders (BSL) and User Routines Table 309 SSC BL: Determining the EEPROM Type and data-flow (continued) EEPROM with 8-bit addressing EEPROM with 16-bit EEPROM with 24-bit Frame connected addressing connected addressing connected N data IMC300A-send IMC300A- IMC300A-send IMC300A- IMC300A-send IMC300A-...
Page 917 IMC300A iMOTION Controller with additional microcontroller 28 Bootstrap Loaders (BSL) and User Routines send 2 address bytes (00 , 00 ) for data to be received send read response byte (FF Check the response based on the last received byte: if equal to the Identification Byte (5D ) - the EEPROM uses 16-bit addressing: •...
Page 918 IMC300A iMOTION Controller with additional microcontroller 28 Bootstrap Loaders (BSL) and User Routines CAN BSL BSL Mode Preparation Initialization Phase Acknowledgement Phase Data Transmission Phase Return Figure 289 CAN BSL Sequence 28.3.1 Initialization Phase SSW switches to the synchronous CAN clock source via internal oscillator or external oscillator, selected by BMI.CANCLK.
Page 919 IMC300A iMOTION Controller with additional microcontroller 28 Bootstrap Loaders (BSL) and User Routines 28.3.2 Acknowledgement Phase An acknowledgement frame is sent to the host indicating completion of initialization phase. After SSW computes the baud rate of the host and reconfigures the NBTR register of node-0, it waits until the initialization frame is correctly and fully received.
Page 920 IMC300A iMOTION Controller with additional microcontroller 28 Bootstrap Loaders (BSL) and User Routines NVM-related functions (see Chapter 28.4.1 Chapter 28.4.2) return status indication as shown in Table 311. Table 311 Status indicators returned by NVM routines in IMC300A ROM Status Indicator Description Symbolic name Value...
Page 921 IMC300A iMOTION Controller with additional microcontroller 28 Bootstrap Loaders (BSL) and User Routines 28.4.3 Request BMI installation This procedure initiates installation of a new BMI value. In particular, it can be used as well as to restore the state upon delivery for a device already in User Productive mode. •...
Page 922 IMC300A iMOTION Controller with additional microcontroller 28 Bootstrap Loaders (BSL) and User Routines invalid addresses (NVM_E_SRC_AREA_EXCEEDED, NVM_E_SRC_ ALIGNMENT, NVM_E_DST_AREA_EXCEEDED, NVM_E_DST_ALIGNMENT) operation failed (NVM_E_FAIL, NVM_E_NVM_FAIL, NVM_E_VERIFY) • Prototype NVM_STATUS NvmProgVerifyBlock (unsigned long srcAddr, unsigned long dstAddr) 28.5 Data in Flash used by the User Routines Table 312 shows the data in Flash which is used by the user routines in IMC300A.
Page 923 IMC300A iMOTION Controller with additional microcontroller 29 Debug System (DBG) Debug System (DBG) The debug system is an extension to the regular processor architecture. The IMC300A Series Microcontrollers provide a complete hardware debug solution, with hardware breakpoint and watchpoint options. This allows high system visibility of the processor, memory and available peripherals.
Page 924 IMC300A iMOTION Controller with additional microcontroller 29 Debug System (DBG) Data System Break- watch- control point point Space unit SWDCLK unit (SCS) (BPU) (DWT) SWDIO / SPDIO Cortex-M0 CPU Core Figure 292 Debug and Trace System block diagram 29.2 Debug System Operation The Debug System provides general debug options.
Page 925 IMC300A iMOTION Controller with additional microcontroller 29 Debug System (DBG) 29.2.3 Break Point Unit (BPU) The Breakpoint (BKPT) instruction provides software breakpoints. It can cause a running system to halt depending on the debug configuration. A BKPT is a synchronous debug event, caused by execution of a BKPT instruction or by a match in the BPU.
Page 926 IMC300A iMOTION Controller with additional microcontroller 29 Debug System (DBG) • WAIT response to read or write operation request (2 Phases: 8-bit read or write packet request, 3-bit WAIT ACK response) • FAULT response Read or Write operation (2-Phases: 8-bit read or write packet request, 3bit FAULT ACK response) •...
Page 927 IMC300A iMOTION Controller with additional microcontroller 29 Debug System (DBG) of the telegram, that tool to add at ‘0’ bit with a negative edge after 0.5 µs. This can be achieved by the tool transferring an odd number of bits. SWD has a clean request response protocol, where the tool is always the requestor and the device executes and sends a response.
Page 928 Halt after reset There are two possibilities to perform a halt after reset. The first possibility is Infineon specific an allows to perform a CPU halt after “power on”/”master” reset (HAR) at the very first instruction of the Application code.
Page 929 IMC300A iMOTION Controller with additional microcontroller 29 Debug System (DBG) 29.2.8.1 The BMI can be configured to allow a HAR (UMHAR) at the end of the SSW, which always requires a power on reset to be executed. A new BMI configuration to BMI.UMHAR (User Mode with debug enabled and HAR) requires to perform a master reset to boot in UMHAR mode.
Page 930 IMC300A iMOTION Controller with additional microcontroller 29 Debug System (DBG) Debug Flash Debugger System From Master_Reset Debug System DAPSA = "0" disabled (default) BMI=UMD OR Enable Debug DAPSA = "1" BMI=UMHAR System access Debugger CDBGPWRUPREQ = "1" Registration Debug System FROM_Master_Reset CDBGPWRUPACK = "1"...
Page 931 IMC300A iMOTION Controller with additional microcontroller 29 Debug System (DBG) Note: The CDBGPWRUPREQ and C_DEBUGEN does not have to be set after a system reset, if they have already been set before and the debugger remains registered. The bits are not affected by the system reset.
Page 932 IMC300A iMOTION Controller with additional microcontroller 29 Debug System (DBG) 29.2.9 Halting Debug and Peripheral Suspend The IMC300A device supports a suspend capability for peripherals, if the program execution of the CPU is stopped by the debugger, e.g. with a breakpoint, or with the C_HALT. This allows to debug critical states of the whole microcontroller.
Page 933 29.2.11 Debug Signals IMC300A MC product family provides debug capability using ARM M0 Debug port SWD or the Infineon proprietary SPD. The SWD Port has 2 interface signals (Clock + Bidirectional data). The SPD port has one interface signal (SPDIO - bidirectional data) with an overlay of SWD interface SWDIO pin.
Page 934 IMC300A iMOTION Controller with additional microcontroller 29 Debug System (DBG) 29.2.12 Reset The debug system register bits are reset by Power-on reset. Other reset in the system do not have an effect on the debug register, if the tool is registered. 29.3 Debug System Power Save Operation The Debug System is in the “always-on”...
Page 935 SW_DP 0BB1 1477 The ARM SW-DP ID 29.7.2 ROM Table To identify Infineon as manufacturer and IMC300A as device, the ROM table has to be read out. The format of the ROM table is illustrated in Table 316. Reference Manual V1.0...
Page 936 4KB count 4KB count [3:0] JEP106 continuation code DBGROMID [11:8] The ROM table values representing Infineon Part Number, JEP106 and Revision number can be checked in the SCU chapter. 29.8 Debug System Registers Registers Overview The absolute register address is calculated by adding: The DWT, BPU, ROM table, DCB and debug register in the SCS are accessible memory mapped by the debugger and also from the CPU.
Page 937 IMC300A iMOTION Controller with additional microcontroller 29 Debug System (DBG) Table 318 Register Overview (continued) Short Name Description Offset Access Mode Description See Addr. Read Write SCS_DEMCR Debug Exception and Monitor Page Control Register DWT_CTRL DWT Control Register Page DWT_PCSR DWT program Counter Sample Page Register...
Page 938 IMC300A iMOTION Controller with additional microcontroller 29 Debug System (DBG) Field Bits Type Description HALTED HALTED Indicates a debug event generated by a C_HALT or C_STEP request, triggered by a write to the DHCSR. no active halt request debug event. halt request debug event active.
Page 939 IMC300A iMOTION Controller with additional microcontroller 29 Debug System (DBG) S_RE S_RE S_LO S_RE S_SL S_HA SET_ TIRE C_DE C_ST ASKI Field Bits Type Description C_DEBUGEN Halting debug enable bit Halting debug disabled. Halting debug enabled. Note: If a debugger writes to DHCSR to change the value of this bit from 0 to 1, it must also write 0 to the C_MASKINTS bit, otherwise behavior is UNPREDICTABLE.
Page 940 IMC300A iMOTION Controller with additional microcontroller 29 Debug System (DBG) (continued) Field Bits Type Description C_MASKINTS Mask PEDSV, SysTick and external configurable interrupts. The effects of writes to this bit are: Do not mask Mask PendSV, SysTick and external configurable interrupts. The effect of any attempt to change the value of this bit is UNPREDICTABLE unless both: •...
Page 941 IMC300A iMOTION Controller with additional microcontroller 29 Debug System (DBG) (continued) Field Bits Type Description S_LOCKKUP S_LOCKUP indicates whether the processor is locked up because of an unrecoverable exception. Not locked up. Locked up. Note: This bit is only read as 1 when accessed by a remote debugger using the DAP.
Page 942 IMC300A iMOTION Controller with additional microcontroller 29 Debug System (DBG) DBGKEY C_DE C_ST ASKI Field Bits Type Description C_DEBUGEN Halting debug enable bit Halting debug disabled. Halting debug enabled. Note: If a debugger writes to DHCSR to change the value of this bit from 0 to 1, it must also write 0 to the C_MASKINTS bit, otherwise behavior is UNPREDICTABLE.
Page 943 IMC300A iMOTION Controller with additional microcontroller 29 Debug System (DBG) (continued) Field Bits Type Description C_MASKINTS Mask PEDSV, SysTick and external configurable interrupts. The effects of writes to this bit are: Do not mask Mask PendSV, SysTick and external configurable interrupts. The effect of any attempt to change the value of this bit is UNPREDICTABLE unless both: •...
Page 944 IMC300A iMOTION Controller with additional microcontroller 29 Debug System (DBG) Field Bits Type Description REGSEL REGSEL - Specifies the ARM core register or special-purpose register to transfer 00000 -01100 ARM core register R0-R12. For example, 0b00000 specifies R0 and 0b00101 specifies R5 01101 The current SP.
Page 945 IMC300A iMOTION Controller with additional microcontroller 29 Debug System (DBG) Field Bits Type Description DBGTMP 31:0 DBGTMP - Data temporary cache, for reading and writing register. This register is UNKONWN: • on reset • when DHCSR.S_HALT = 0 • when DHCSR.S_REGRDY = 0 during execution of a DCRSR based transaction that updates the register.
Page 946 IMC300A iMOTION Controller with additional microcontroller 29 Debug System (DBG) (continued) Field Bits Type Description DWTENA DWTENA - Global enable for all features configured by the DWT unit. DWT disabled. DWT enabled. Note: When DWTENA is set to 0 DWT registers return UNKNOWN values on reads.
Page 947 IMC300A iMOTION Controller with additional microcontroller 29 Debug System (DBG) EIASAMPLE EIASAMPLE Field Bits Type Description EIASAMPLE 31:0 EIASAMPLE Executed instruction address sample register 29.8.8 Register DWT_COMPx The DWT_COMPx register provides a reference value for use by comparator x. The value is UNKNOW on reset. DWT_CTRL.NUMCOMP defines the number of implemented DWT_COMPx register, from 0 to (NUMCOMP-1).
Page 948 IMC300A iMOTION Controller with additional microcontroller 29 Debug System (DBG) DWT_MASK0 Address: Debug Halting Control and Status Register Reset Value: 0000 0000 DWT_MASK1 Address: Debug Halting Control and Status Register Reset Value: 0000 0000 MASK Field Bits Type Description MASK MASK The size of the ignore mask applied to address range matching.
Page 949 IMC300A iMOTION Controller with additional microcontroller 29 Debug System (DBG) Field Bits Type Description FUNCTION FUNCTION Select action on comparator match- 0000 Disabled. 0001 Reserved. 0010 Reserved. 0011 Reserved. 0100 PC watchpoint event - input Iaddr. 0101 Watchpoint event - input Daddr (read only) 0110 Watchpoint event - input Daddr (write only) 0111...
Page 950 IMC300A iMOTION Controller with additional microcontroller 29 Debug System (DBG) Field Bits Type Description ENABLE ENABLE the BPU BPU is disabled. BPU is enabled. Note: This bit is set to 0 on Power-on reset. KEY reads as 0 on reads, should be 1 for writes. If written as zero, the write to the register is ignored.
Page 951 IMC300A iMOTION Controller with additional microcontroller 29 Debug System (DBG) Field Bits Type Description ENABLE ENABLE the comparator Comparator is disabled. Comparator is enabled. Note: This bit is set to 0 on a Power-on reset. BP_CTRL:ENABLE must also be set to 1 to enable a comparator.
Page 952 ARM Debug Interface Architecture Specification V5 Cortex Microcontroller Software Interface Standard (CMSIS) References to ARM figures: http://www.arm.com I2C Bus Specification (Philips Semiconductors v2.1) ™ [10] Infineon iMOTION MCE Software Reference Manual http://www.infineon.com/imotion The document can be accessed through http://infocenter.arm.com Reference Manual V1.0...
Page 953 IMC300A iMOTION Controller with additional microcontroller Revision history Revision history Document Date of Description of changes version release 2020-05-22 • Initial version Reference Manual V1.0 2020-05-28...
Page 954 Infineon Technologies, All Rights Reserved. any kind, including without limitation warranties of Infineon Technologies’ products may not be used in non-infringement of intellectual property rights of any any applications where a failure of the product or third party.

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