Infineon IMC300A Series Manuals

Manuals and User Guides for Infineon IMC300A Series. We have 2 Infineon IMC300A Series manuals available for free PDF download: Manual, Getting Started Manual

Infineon IMC300A Series Manual (954 pages)

Controller with Additional Microcontroller

Brand: Infineon | Category: Controller | Size: 8.72 MB

About this Document
1
Table of Contents
3
Introduction
35
Overview
35
Block Diagram
37
Device Overview
39
CPU Subsystem
40
Central Processing Unit (CPU)
40
Math Coprocessor (MATH)
40
Programmable Multiple Priority Interrupt System (NVIC)
40
On-Chip Memories
40
Communication Peripherals
41
Universal Serial Interface Channel (USIC)
41
Controller Area Network (Multican)
41
Analog Frontend Peripherals
41
Analog to Digital Converter (ADC)
41
Analog Comparator (ACMP) and out of Range Comparator (ORC)
41
Digital to Analog Converter (DAC)
41
Temperature Sensor (DTS)
42
Timer Peripherals
42
Capture/Compare Unit 4 (CCU4)
42
Position Interface Unit (POSIF)
42
On-Chip Debug Support
42
Conventions
43
Imotion Controller User Documentation
43
Copyright Notice
43
Text Conventions
43
Bit Function Terminology
44
Register Access Modes
44
Reserved Bits
45
Abbreviations and Acronyms
45
Motion Control Engine Interface
48
Central Processing Unit (CPU)
48
Overview
48
Features
49
Block Diagram
49
Programmers Model
50
Processor Modes
50
Stacks
50
Core Registers
51
General-Purpose Registers
52
Stack Pointer
52
Link Register
53
Program Counter
53
Program Status Register
54
Application Program Status Register
54
Interrupt Program Status Register
55
Execution Program Status Register
56
Interruptible-Restartable Instructions
57
Thumb State
57
Exception Mask Registers
57
Priority Mask Register
57
CONTROL Register
58
Exceptions and Interrupts
59
Data Types
59
The Cortex Microcontroller Software Interface Standard
59
CMSIS Functions
60
Memory Model
60
Memory Regions, Types and Attributes
61
Memory System Ordering of Memory Accesses
62
Behavior of Memory Accesses
62
Software Ordering of Memory Accesses
63
Memory Endianness
63
Little-Endian Format
63
Instruction Set
64
Intrinsic Functions
66
Exception Model
66
Exception States
66
Exception Types
67
Exception Handlers
68
Vector Table
68
Vector Table Remap
69
Exception Priorities
70
Exception Entry and Return
70
Exception Entry
72
Exception Return
73
Fault Handling
73
Lockup
74
Power Management
74
Entering Sleep Mode
74
Wakeup from Sleep Mode
74
Power Management Programming Hints
75
Private Peripherals
75
About the Private Peripherals
75
System Control Block
76
System Control Block Usage Hints and Tips
76
System Timer, Systick
76
Systick Usage Hints and Tips
76
PPB Registers
76
SCS Registers
77
Register CPUID
77
Register ICSR
78
Register AIRCR
79
Register SCR
80
Register CCR
81
System Handler Priority Registers
82
Register SHPR2
83
Register SHPR3
83
Register SHCSR
84
Systick Registers
84
Register SYST_CSR
84
Register SYST_RVR
85
Register SYST_CVR
86
Register SYST_CALIB
87
MATH Coprocessor (MATH)
88
Overview
88
Features
88
Block Diagram
88
Divider Unit (DIV)
88
Division Operation
89
Start Mode Selection
90
Error Handling
90
Operand/Result Pre-/Post-Processing
92
CORDIC Coprocessor
92
Overview
92
Features
93
Functional Overview
93
Operation of the MATH
93
Normalized Result Data
94
MATH Operating Modes
95
Domains of Convergence
96
Overflow Considerations
97
MATH Data Format
97
Accuracy of MATH
98
Performance of MATH
100
Global Functions
101
Result Chaining
101
Result Chaining When Start Mode = 0
101
Handling Busy Flags When Result Chaining Is Enabled
102
Service Request Generation
102
Debug Behaviour
103
Power, Reset and Clock
104
Registers
104
Global Registers Description
105
Register GLBCON
105
Register MATH_ID
107
Register EVIER
108
Register EVFR
109
Register EVFSR
109
Register EVFCR
110
Divider Registers Description
111
Register DVD
111
Register DVS
112
Register QUOT
112
Register RMD
113
Register DIVST
113
Register DIVCON
113
CORDIC Registers Description
115
Register STATC
115
Register con
116
Cordx
118
Register CORDX
118
Register CORDY
118
Register CORDZ
118
Corrx
119
Register CORRX
119
Register CORRY
119
Register CORRZ
120
Interconnects
120
Service Request Processing
121
Overview
121
Features
121
Block Diagram
121
Service Request Distribution
122
Interrupt Subsystem (NVIC)
124
Nested Vectored Interrupt Controller (NVIC)
124
Features
124
Interrupt Node Assignment
124
Interrupt Signal Generation
126
NVIC Design Hints and Tips
126
Accessing CPU Registers Using CMSIS
127
Interrupt Priority
127
Interrupt Latency
128
General Module Interrupt Structure
129
Registers
130
NVIC Registers
131
Register NVIC_ISER
131
Register NVIC_ICER
131
Register NVIC_ISPR
132
Register NVIC_ICPR
132
Register Nvic_Iprx (X=0-7)
133
SCU Interrupt Related Registers
133
Register SCU_INTCR0
134
Register SCU_INTCR1
134
Interrupt Request Source Overview
135
Interrupt Source: SCU.SR0
135
Flash Double Bit ECC Event
135
Flash Operation Complete Event
135
SRAM Parity Error Event
135
USIC RAM Parity Error Event
136
Loss of Clock Event
136
Interrupt Source: SCU.SR1
136
Standby Clock Failure Event
136
VDDP Pre-Warning Event
137
VDDC Drops below VDROP Event
137
VDDC Rises above VCLIP Event
137
DTS Done Event
138
DTS Compare High Event
138
DTS Compare Low Event
138
WDT Pre-Warning Event
138
RTC Periodic Event
139
RTC Alarm Event
139
RTC CTR Mirror Register Updated Event
139
RTC ATIM0 Mirror Register Updated Event
140
RTC ATIM1 Mirror Register Updated Event
140
RTC TIM0 Mirror Register Updated Event
140
RTC TIM1 Mirror Register Updated Event
140
Interrupt Source: SCU.SR2
141
Out of Range Comparator X Event (X=0,4,6,7)
141
Analog Comparator X Event (X=0-2)
141
Interrupt Source: Erux.sr[3:0] (X=0-1)
142
Erux_Iouty (Y=0-3)
142
Interrupt Source: MATH.SR0
142
CORDIC End of Calculation Event
142
CORDIC Error Event
142
DIV End of Calculation Event
142
DIV Error Event
143
Interrupt Source: Usicx_Sr[5:0] (X=0-1)
143
USIC: Standard Receive Event
143
USIC: Receive Start Event
143
USIC: Alternate Receive Event
143
USIC: Transmit Shift Event
144
USIC: Transmit Buffer Event
144
USIC: Data Lost Event
144
USIC: BRG Event
145
USIC: Standard Transmit Buffer Event
145
USIC: Transmit Buffer Error Event
145
USIC: Standard Receive Buffer Event
146
USIC: Alternate Receive Buffer Event
146
USIC: Receive Buffer Error Event
146
ASC: Synchronisation Break Detected Event
147
ASC: Collision Detected Event
147
ASC: Receiver Noise Detected Event
147
ASC: Format Error in Stop Bit 0 Event
147
ASC: Format Error in Stop Bit 1 Event
148
ASC: Receive Frame Finished Event
148
ASC: Transmit Frame Finished Event
148
SSC: MSLS Event Detected Event
149
SSC: Parity Error Detected Event
149
SSC: DX2T Event Detected Event
149
IIC: Wrong TDF Code Detected Event
149
IIC: Start Condition Received Event
150
IIC: Repeated Start Condition Received Event
150
IIC: Stop Condition Received Event
150
IIC: NACK Received Event
151
IIC: Arbitration Lost Event
151
IIC: Slave Read Request Event
151
IIC: Error Detected Event
151
IIC: ACK Received Event
152
IIS: DX2T Event Detected Event
152
IIS: WA Falling Edge Event
152
IIS: WA Rising Edge Event
153
IIS: WA Generation End Event
153
Interrupt Source: VADC0_C0SR[1:0] and Vadc0_Gxsr[1:0] (X=0-1)
153
Source Event 0 Event
153
Source Event 1 Event
153
Channel Event y (Y=0-7) Event
154
Result Event y (Y=0-7) Event
154
Result Event y (Y=8-15) Event
154
Global Source Event
155
Global Result Event
155
Interrupt Source: Ccu4X_Sr[3:0] (X=0-1)
155
Event 0 Edge(S) Information from Event Selector
155
Event 1 Edge(S) Information from Event Selector
155
Event 2 Edge(S) Information from Event Selector
156
Period Match While Counting up Event
156
Compare Match While Counting up Event
156
Compare Match While Counting down Event
157
One Match While Counting down Event
157
Entering Trap State Event
157
Interrupt Source: Ccu8X_Sr[1:0] (X=0-1)
157
Event 0 Edge(S) Information from Event Selector
157
Event 1 Edge(S) Information from Event Selector
158
Event 2 Edge(S) Information from Event Selector
158
Period Match While Counting up Event
158
Compare Match While Counting up from Compare Channel 1 Event
159
Compare Match While Counting down from Compare Channel 1 Event
159
Compare Match While Counting up from Compare Channel 2 Event
159
Compare Match While Counting down from Compare Channel 2 Event
160
One Match While Counting down Event
160
Entering Trap State Event
160
Interrupt Source: Posifx.sr[1:0] (X=0-1)
160
Transition at Hall Inputs Events
160
Occurrence of Correct Hall Event
161
Occurrence of Wrong Hall Event
161
Shadow Transfer of MCM Pattern Event
161
Index Event Detection Event
162
Phase Detection Error Event
162
Quadrature Clock Generation Event
162
Period Clock Generation Event
162
Direction Change Event
163
Interrupt Source: CAN0.SR[3:0]
163
Message Transmitted Event
163
Message Received Event
163
Last Error Code Event
164
Fast Last Error Code Event
164
Alert Warning Event
164
Receive Pending Event
164
Transmit Pending Event
165
FIFO Full Event
165
Event Request Unit (ERU)
166
Features
166
Overview
166
Event Request Select Unit (ERS)
167
Event Trigger Logic (Etlx)
167
Cross Connect Matrix
169
Output Gating Unit (Oguy)
170
Power, Reset and Clock
172
Initialization and System Dependencies
172
Registers
172
ERU Registers
173
Register EXISEL
173
Register Exiconx
174
Register Exoconx
176
Interconnects
178
ERU0 Connections
178
ERU1 Connections
181
Bus System
185
Bus Interfaces
185
Memory Organization
186
Overview
186
Features
186
Cortex-M0 Address Space
186
Memory Regions
187
Memory Map
187
Memory Access
192
Flash Memory Access
192
SRAM Access
192
ROM Access
193
Memory Protection Strategy
193
Intellectual Property (IP) Protection
193
Blocking of Unauthorized External Access
193
Memory Access Protection During Run-Time
193
Bit Protection Scheme
193
Register SCU_PASSWD
194
Peripheral Privilege Access Control
195
Service Request Generation
195
Debug Behaviour
196
Power, Reset and Clock
196
Initialization and System Dependencies
196
Peripheral Access Unit (PAU)
197
Overview
197
Features
197
Peripheral Privilege Access Control
197
Peripheral Availability and Memory Size
198
Service Request Generation
199
Debug Behaviour
199
Power, Reset and Clock
199
Initialization and System Dependencies
199
PAU Registers
199
Peripheral Privilege Access Registers (Privdisn)
200
Register PRIVDIS0
200
Register PRIVDIS1
201
Register PRIVDIS2
203
Peripheral Availability Registers (Availn)
204
Register AVAIL0
205
Register AVAIL1
206
Register AVAIL2
207
Memory Size Registers
209
Register ROMSIZE
209
Register FLSIZE
210
Register RAM0SIZE
210
Flash Architecture
212
Overview
212
Features
212
Definitions
212
Logical and Physical States
212
Data Portions
213
Address Types
213
Module Specific Definitions
213
Module Components
214
Memory Cell Array
214
Sector
215
Functional Description
215
SFR Accesses
215
Memory Read
215
Memory Write
215
Memory Erase
216
Sector Erase
216
Verify
216
Erase-Protection and Write-Protection
217
Properties and Implementation of Error Correcting Code (ECC)
217
Service Request Generation
217
Power, Reset and Clock
218
Power Supply
218
Power Saving Modes
218
NVM Idle Mode
218
NVM Sleep Mode
218
Reset
218
Clock
218
Registers
218
NVM Register
219
Register NVMSTATUS
219
Register NVMPROG
220
Register NVMCONF
223
Example Sequences
224
Writing to Memory
224
Writing a Single Block
224
Writing Blocks
225
Erasing Memory
225
Erasing a Single Page
225
Erasing
225
Erasing a Single Sector
225
Erasing Sectors
226
Verifying Memory
226
Verifying a Single Block
226
Verifying Blocks
226
Writing to an Already Written Block
226
Sleep Mode
227
Timing
228
Prefetch Unit (PFU)
230
Overview
230
Block Diagram
230
Operation Mode
230
PFU Control Register
231
Register SCU_PFUCR
231
System Control Unit (SCU)
232
Overview
232
Features
232
Block Diagram
232
Miscellaneous Control Functions (GCU)
234
Service Requests Handling
234
Service Request Sources
235
SRAM Memory Content Protection
235
Summary of ID
236
Boot Via Pins
236
Power Management (PCU)
237
Functional Description
237
System States
237
Embedded Voltage Regulator (EVR)
238
Power-On Reset
238
Power Validation
239
Supply Voltage Monitoring
239
VDDC Response During Load Change
239
Flash Power Control
240
Reset Control (RCU)
240
Functional Description
240
Reset Status
241
Clock Control (CCU)
241
Features
241
Clock System and Control
242
DCO1 Oscillator Watchdog
246
Loss of DCO1 Clock Detection and Recovery
247
Standby Clock Failure
247
XTAL Oscillator Watchdog
247
Loss of External OSC_HP Clock Detection and Recovery
247
Startup Control for System Clock
248
DCLK Input - External Clock Via OSC_HP
248
Clock Gating Control
248
Calibrating DCO1 Based on Temperature
248

Infineon IMC300A Series Getting Started Manual (15 pages)

Motor Control Units

Brand: Infineon | Category: Controller | Size: 0.42 MB

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Motherboard Microcontrollers Computer Hardware Control Unit Controller

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Infineon IMC300A Series Manuals

Infineon IMC300A Series Manual (954 pages)

Table of Contents

Infineon IMC300A Series Getting Started Manual (15 pages)

Table of Contents

Table of Contents

About this Document

1 Brief Overview of MCU

2 Getting Started

3 Troubleshooting FAQ

4 Reference

Revision History

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