Overview; Purpose; Evm Basic Functions; Power Requirements - Texas Instruments DAC5686 EVM User Manual

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1

Overview

This user's guide document gives a general overview of the DAC5686 evaluation module (EVM) and
provides a general description of the features and functions to be considered while using this module.
1.1

Purpose

The DAC5686 EVM provides a platform for evaluating the DAC5686 digital-to-analog converter (DAC)
under various signal, reference, and supply conditions. This document should be used in combination with
the EVM schematic diagram supplied.
1.2

EVM Basic Functions

Digital inputs to the DAC can be provided with CMOS level signals up to 160 MSPS through two 34-pin
headers. This enables the user to provide high-speed digital data to the DAC5686 device.
The analog outputs from the DAC are available via SMA connectors. Because of its flexible design the
analog output of the DAC5686 device can be configured to drive a doubly terminated 50-Ω cable using a
4:1 or 1:1 impedance ratio transformer, or single-ended referred to AVDD.
The EVM allows for different clock configurations. The user can input a single-ended, differential
ECL/PECL or TTL/CMOS level signal, to be used to generate a single-ended or differential clock source.
See
Section 4.1
for proper configuration and operation.
Power connections to the EVM are via banana jack sockets.
In addition to the internal bandgap reference provided by the DAC5686 device, options on the EVM allow
an external reference to be provided to the DAC.
The DAC5686 EVM allows the user to program the DAC5686 internal registers with the supplied computer
parallel port cable and serial interface software. The interface allows read and write access to all registers
that define the operation mode of the DAC5686 device.
1.3

Power Requirements

The demonstration board requires a minimum of two power supplies. For non-PLL and 3.3-V I/O
operation, connect 3.3 Vdc to banana jack J7 with the return connected to J9. Connect 1.8 Vdc to banana
jack J8 and the return to J10. Jumper W2 selects the digital I/O voltage level and jumper W3 enables the
PLL.
1.3.1
Voltage Limits
Exceeding the maximum input voltages can damage EVM components. Undervoltage may cause
improper operation of some or all of the EVM components.
SLWU006E – December 2004 – Revised March 2007
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SLWU006E – December 2004 – Revised March 2007
DAC5686 EVM
User's Guide
DAC5686 EVM
5

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