Mipi Csi; Clock; Spi; Pcie1 - Thundercomm TurboX C865 Dev Kit Hardware User's Manual

50 PMIC_SPMI_DATA
52 GND
54 USB1_SS_TX_P_HS2
56 USB1_SS_TX_M_HS2
58 USB1_SS_RX_P_HS2
60 USB1_SS_RX_M_HS2

5.2.1 MIPI CSI

The Secondary High Speed Expansion Connector supports 2 4-lane MIPI-CSI bus (MIPI-CSI1/MIPI-
CSI2). All MIPI-CSI signals are routed directly to/from the SM8250.

5.2.2 Clock

The C865 DEV KIT implements another 4 CSI clocks on the Secondary High Speed Expansion
Connector, CLK1/CSI1_MCLK, GPIO_95 for CSI1; CLK2/CSI2_MCLK, GPIO_96 for CSI2;
CLK4/CSI4_MCLK, GPIO98 for CSI4 and CLK5/CSI5_MCLK, GPIO99 for CSI5. These signals are
driven at 1.8V.

5.2.3 SPI

The C865 DEV KIT implements another SPI interface on the Secondary High Speed Expansion
Connector that connect to SM8250 QUP14. These signals are driven at 1.8V.

SPI1_CLK : Connects to QUP 14 of SM8250 SoC, Be configured as CLK

SPI1_CS

SPI1_MOSI

SPI1_MISO

5.2.4 PCIe1

The C865 DEV KIT has 2 2-lane PCIe interfaces. PCIe1 1-lane is available on the Secondary High
Speed Expansion Connector.
`www.thundercomm.com.
: Connects to QUP 14 of SM8250 SoC. Be configured to CS.
: Connects to QUP 14 of SM8250 SoC. Be configured to MOSI.
: Connects to QUP 14 of SM8250 SoC. Be configured to MISO.
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