Pat Trig; Digital Bus I/O - Keysight Technologies N5166B CXG User Manual

Signal Generator Overview
Rear Panel Overview (N5166B, N5171B, N5172B, N5181B, & N5182B)

PAT TRIG

Connector female BNC
Signal A TTL/CMOS low to TTL/CMOS high, or TTL/CMOS high to TTL/CMOS low edge trigger.
The input to this connector triggers the internal digital modulation pattern generator to start a
single pattern output or to stop and re–synchronize a pattern that is being continuously output.
To synchronize the trigger with the data bit clock, the trigger edge is latched, then sampled
during the falling edge of the internal data bit clock.
This is the external trigger for all ARB waveform generator triggers.
Minimum Trigger Input Pulse
Width
Minimum Trigger Delay (trigger edge to first bit of frame) = 1.5 to 2.5 bit clock periods
Damage Levels < −4 and > +8 V

DIGITAL BUS I/O

This is a proprietary bus used by Keysight Technologies signal creation software. This connector is
not operational for general purpose use. Signals are present only when a signal creation software
option is installed (for details, refer to http://www.keysight.com/find/signalcreation).
The X-Series' Digital BUS I/O connector can be used for enabling
operation with the Keysight Technologies N5106A PXB MIMO Receiver
Tester.
34
(high or low) = 10 ns
Keysight CXG, EXG, and MXG X-Series Signal Generators User's Guide