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7. For a two-clock system configuration, design the layout to ensure separation of the oscillator circuits
that generate the clocks for input to the encoder clock input pin ECK (pin 88) and system drive clock
input pin MCK (pin 43). Arrange them as close as possible to each pin. Noise may occur if the clocks
interfere with each other.
8. EVR 0-2 (pins 63, 64, and 66, respectively) are DAC output pins. Connect a bypass capacitor of
approximately 0.1 uF between each pin and ground.
9. IOC and IOY (pins 67 and 75) are analog output pins. Separating them too much makes them more
susceptible to noise, so keep the wiring as short as possible. Ensure that these lines are designed not
to cross the pattern of AVD, VG, IREF, or VREF.
VGC and VGY (pins 69 and 72) are pins for connection with a capacitor for DAC. Connect a bypass
capacitor of approximately 0.1 uF between each pin and ground.
10. ECK (pin 88) is an input pin for the encoder clock, that is, for X'tal oscillator input. Make the signal line
as short as possible and surround it with a ground shield so that it will not be affected by nearby circuits.
We also recommend positioning X'tal components and the board's inner layer away from other circuits
and removing the board's inner layer pattern so they are not affected by floating capacitance.
Additionally, ESCI and ESCO (pins 86 and 87) are I/O pins for the CXD3172AR's internal oscillator cell.
We recommend designing the configuration so that these pins are used in the oscillator circuit of the
clock providing input to ECK. If the clock sent to ECK is generated by external means such as an
inverter, it enlarges the oscillator circuit, so nearby circuits may be affected by noise.
11. If pins 0-15 are used for digital output, make the signal lines as short as possible so that the
surrounding analog circuits will not be affected by noise. Cover the surrounding area with a ground
shield to separate the signal lines from analog circuits.
23
- SS-HQ1 Application Notes -
Ver.1.0.0 January 7, 2005
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