Vs Lock Mode (Vsl) - Sony SS-HQ1 Application Notes

12.2.6. VS Lock Mode (VSL)

In this mode, the camera's vertical and horizontal phases are synchronized to an external video signal.
The reset operation is performed in the vertical direction, and the PLL operation is performed in the horizontal
direction. SGMODE is set to 2[h]. (See Table 12.2-5.)
System Configuration
The VS Lock Mode master signal is the external video signal (EXT-VIDEO). The 1Vpp external video
luminance signal (EXT-VIDEO-Y), which has passed through an external LPF and had its subcarrier
component removed, is input to the EXVIDEOY (pin 57) pin.
Inside the CXD3172AR, the input EXT-VIDEO-Y signal is divided between a vertical signal (EXT-VD) and a
horizontal signal (EXT-HD). EXT-VD resets the vertical counter inside the CXD3172AR. The EXT-HD signal is
phase-compared against the MCK-frequency-divided HD (MCK-HD) signal inside the CXD3172AR.
In addition, in VS Lock Mode (VSL), the 27.000MHz clock is used for input to ECK (pin 88). In this case, the
MODESEL (operation mode) setting is as shown in Table 12.2-13. We recommend using X'tal oscillation for
the VCXO on the MCK side.
A system block diagram is shown in Fig 12.2-22. The external input signal is presented in Table 12.2-24.
VCXO
EXT-VIDEO
Pin Name(Pin No)
S0(44pin)
EXVIDEOY(57pin)
EXVIDEO(58pin)
* EXT-VIDEO should be passed through an LPF before being input to EXVIDEOY (pin 57). This serves to
remove the subcarrier component, and is a countermeasure against noise in cases where no external video
signal is input.
LPF
(27.000MHz)
(H-PLL)
42 86
MCK
43
CXD3172AR
57 58
LPF
Fig 12.2-22 VS Lock (VSL) mode
Table 12.2-24 External I/O signals (VS Lock (VSL) Mode)
I/O
IN
IN
OUT
X'tal
87 88
47
S2
48
S3
49
S4
44 46
I/O signals
3.3V connection
EXT-VIDEO-Y (1Vpp: analog signal)
DC bias supply to EXVIDEOY (pin 57)
210
- SS-HQ1 Application Notes -
Ver.1.0.0 January 7, 2005
3.3V